The GENEVE TLV option matching is done using a flex parser.
Recent update in firmware, requires that in order to match on the
GENEVE TLV option the "geneve_tlv_option_0_exist" bit should be set.
Add the new "geneve_tlv_option_0_exist" setting when translating the
GENEVE TLV option item.
Signed-off-by: Shiri Kuzin <shi...@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viachesl...@nvidia.com>
---
drivers/common/mlx5/mlx5_prm.h | 3 ++-
drivers/net/mlx5/mlx5_flow_dv.c | 2 ++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 26761f5bd3..3e4e6fa216 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -853,7 +853,8 @@ struct mlx5_ifc_fte_match_set_misc_bits {
u8 vxlan_vni[0x18];
u8 reserved_at_b8[0x8];
u8 geneve_vni[0x18];
- u8 reserved_at_e4[0x7];
+ u8 reserved_at_e4[0x6];
+ u8 geneve_tlv_option_0_exist[0x1];
u8 geneve_oam[0x1];
u8 reserved_at_e0[0xc];
u8 outer_ipv6_flow_label[0x14];
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index c50649a107..f009689cff 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -8939,6 +8939,8 @@ flow_dv_translate_item_geneve_opt(struct rte_eth_dev
*dev, void *matcher,
MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
geneve_opt_v->option_len + 1);
}
+ MLX5_SET(fte_match_set_misc, misc_m, geneve_tlv_option_0_exist, 1);
+ MLX5_SET(fte_match_set_misc, misc_v, geneve_tlv_option_0_exist, 1);
/* Set the data. */
if (geneve_opt_v->data) {
memcpy(&opt_data_key, geneve_opt_v->data,
--
2.27.0
