Re: [dpdk-dev] [PATCH v5 1/2] vhost: support inflight share memory protocol feature

[Tiwei Bie]

On Wed, Aug 07, 2019 at 02:24:59AM +0800, JinYu wrote:
> This patch introduces two new messages VHOST_USER_GET_INFLIGHT_FD
> and VHOST_USER_SET_INFLIGHT_FD to support transferring a shared
> buffer between qemu and backend.
> 
> Firstly, qemu uses VHOST_USER_GET_INFLIGHT_FD to get the
> shared buffer from backend. Then qemu should send it back
> through VHOST_USER_SET_INFLIGHT_FD each time we start vhost-user.
> 
> This shared buffer is used to process inflight I/O when backend
> reconnect.
> 
> Signed-off-by: Lin Li 
> Signed-off-by: Xun Ni 
> Signed-off-by: Yu Zhang 
> Signed-off-by: JinYu 

s/JinYu/Jin Yu/

> ---
> v1 - specify the APIs are split-ring only
> v2 - fix APIs and judge split or packed
> v3 - Add rte_vhost_ prefix and fix one issue.
> v4 - add the packed ring support
> v5 - revise get_vring_base func depend on Tiwei's suggestion
> ---
>  lib/librte_vhost/rte_vhost.h   | 255 ++-
>  lib/librte_vhost/rte_vhost_version.map |  12 +
>  lib/librte_vhost/vhost.c   | 396 +-
>  lib/librte_vhost/vhost.h   |  61 ++--
>  lib/librte_vhost/vhost_user.c  | 437 -
>  lib/librte_vhost/vhost_user.h  |  13 +-
>  6 files changed, 1128 insertions(+), 46 deletions(-)

This patch is too big, please divide it into small patches.
E.g. rte_vhost_vq_is_packed() can be introduced in a separate patch.

> 
> diff --git a/lib/librte_vhost/rte_vhost.h b/lib/librte_vhost/rte_vhost.h
> index 0226b3eff..3f01429b1 100644
> --- a/lib/librte_vhost/rte_vhost.h
> +++ b/lib/librte_vhost/rte_vhost.h
> @@ -11,6 +11,7 @@
>   */
>  
>  #include 
> +#include 
>  #include 
>  
>  #include 
> @@ -71,6 +72,10 @@ extern "C" {
>  #define VHOST_USER_PROTOCOL_F_HOST_NOTIFIER 11
>  #endif
>  
> +#ifndef VHOST_USER_PROTOCOL_F_INFLIGHT_SHMFD
> +#define VHOST_USER_PROTOCOL_F_INFLIGHT_SHMFD 12
> +#endif
> +
>  /** Indicate whether protocol features negotiation is supported. */
>  #ifndef VHOST_USER_F_PROTOCOL_FEATURES
>  #define VHOST_USER_F_PROTOCOL_FEATURES   30
> @@ -98,10 +103,92 @@ struct rte_vhost_memory {
>   struct rte_vhost_mem_region regions[];
>  };
>  
> +struct inflight_desc_packed {
> + uint8_t inflight;
> + uint8_t padding;
> + uint16_t next;
> + uint16_t last;
> + uint16_t num;
> + uint64_t counter;
> + uint16_t id;
> + uint16_t flags;
> + uint32_t len;
> + uint64_t addr;
> +};

Why struct inflight_desc_split doesn't have to be part of
vhost API but struct inflight_desc_packed has to be?

> +
> +struct inflight_info_packed {
> + uint64_t features;
> + uint16_t version;
> + uint16_t desc_num;
> + uint16_t free_head;
> + uint16_t old_free_head;
> + uint16_t used_idx;
> + uint16_t old_used_idx;
> + uint8_t used_wrap_counter;
> + uint8_t old_used_wrap_counter;
> + uint8_t padding[7];
> + struct inflight_desc_packed desc[0];
> +};
> +
> +struct rte_vhost_resubmit_desc {
> + uint16_t index;
> + uint64_t counter;
> +};
> +
> +struct rte_vhost_resubmit_info {
> + struct rte_vhost_resubmit_desc  *resubmit_list;
> + uint16_t resubmit_num;
> +};
> +
> +struct rte_vhost_ring_inflight {
> + union {
> + struct inflight_info_split *inflight_split;

struct inflight_info_split is used but not declared.

> + struct inflight_info_packed *inflight_packed;
> + };
> +
> + struct rte_vhost_resubmit_info *resubmit_inflight;
> +};
> +
> +/*
> + * Declare below packed ring defines unconditionally
> + * as Kernel header might use different names.
> + */
> +#ifndef VIRTIO_F_RING_PACKED
> +#define VIRTIO_F_RING_PACKED 34
> +
> +#define VRING_DESC_F_AVAIL   (1ULL << 7)
> +#define VRING_DESC_F_USED(1ULL << 15)

You shouldn't put above macros under VIRTIO_F_RING_PACKED as
kernel doesn't define them. And the build will be broken when
kernel defines VIRTIO_F_RING_PACKED.

Besides, it seems not a good idea to make them parts of vhost
API.

> +
> +struct vring_packed_desc {
> + uint64_t addr;
> + uint32_t len;
> + uint16_t id;
> + uint16_t flags;
> +};
> +
> +#define VRING_EVENT_F_ENABLE 0x0
> +#define VRING_EVENT_F_DISABLE 0x1
> +#define VRING_EVENT_F_DESC 0x2
> +struct vring_packed_desc_event {
> + uint16_t off_wrap;
> + uint16_t flags;
> +};

You just need to declare instead of defining
vring_packed_desc/vring_packed_desc_event in vhost header.

> +#endif
> +
>  struct rte_vhost_vring {
> - struct vring_desc   *desc;
> - struct vring_avail  *avail;
> - struct vring_used   *used;
> + union {
> + struct vring_desc   *desc;
> + struct vring_packed_desc *desc_packed;
> + };
> + union {
> + struct vring_avail  *avail;
> + struct vring_packed_desc_event *driver_event;
> + };
> + union {
> + struct vring_used   *used;
> + struct vring_packed_desc_event *device_event;
> + };

Re: [dpdk-dev] [PATCH v4 1/2] app/test: add unit test cases for mbuf library APIs

[Olivier Matz]

Hi,

Few minor comments below. You can add my ack in the v5 once fixed.

On Thu, Aug 08, 2019 at 02:34:19PM +0100, Lavanya Govindarajan wrote:
> Added new unit test cases to cover the below
> functions defined in rte_mbuf.h
> rte_validate_tx_offload,
> rte_pktmbuf_alloc_bulk,
> rte_pktmbuf_read,
> rte_pktmbuf_ext_shinfo_init_helper,
> rte_pktmbuf_attach_extbuf,
> rte_mbuf_ext_refcnt_read,
> rte_mbuf_ext_refcnt_update,
> rte_mbuf_ext_refcnt_set,
> rte_pktmbuf_detach_extbuf
> 
> Signed-off-by: Lavanya Govindarajan 
> Reviewed-by: Reshma Pattan 
> ---
>  app/test/test_mbuf.c | 756 ++-
>  1 file changed, 753 insertions(+), 3 deletions(-)

[...]

> +/*
> + * Negative testing for allocating a bulk of mbufs
> + */
> +static int
> +test_neg_pktmbuf_alloc_bulk(struct rte_mempool *pktmbuf_pool)
> +{
> + int loop, ret = 0;
> + unsigned int idx;
> + int neg_alloc_counts[] = {
> + MEMPOOL_CACHE_SIZE - NB_MBUF,
> + NB_MBUF + 1,
> + NB_MBUF * 8,
> + UINT_MAX
> + };

It should be unsigned int instead of int.

> + struct rte_mbuf *mbufs[NB_MBUF * 8] = { 0 };
> +
> + for (idx = 0; idx < RTE_DIM(neg_alloc_counts); idx++) {
> + ret = rte_pktmbuf_alloc_bulk(pktmbuf_pool, mbufs,
> + neg_alloc_counts[idx]);
> + if (ret == 0) {
> + printf("%s: Bulk alloc must fail! count(%u); ret(%d)\n",
> + __func__, neg_alloc_counts[idx], ret);
> + for (loop = 0; loop < neg_alloc_counts[idx] &&
> + mbufs[loop] != NULL; loop++)
> + rte_pktmbuf_free(mbufs[loop]);
> + return -1;
> + }
> + }
> + return 0;
> +}

[...]

> +static int
> +test_pktmbuf_read_from_chain(struct rte_mempool *pktmbuf_pool)
> +{
> + struct rte_mbuf *m;
> + /* add testcases with different segments len, offset and read len */
> + struct test_case test_cases[] = {
> + { .seg_lengths = { 100, 100, 100 },
> + .seg_count = 3,
> + .flags = MBUF_NO_HEADER,
> + .read_off = 0, .read_len = 300 },
> + { .seg_lengths = { 100, 125, 150 },
> + .seg_count = 3,
> + .flags = MBUF_NO_HEADER,
> + .read_off = 99, .read_len = 201 },
> + { .seg_lengths = { 100, 100 },
> + .seg_count = 2,
> + .flags = MBUF_NO_HEADER,
> + .read_off = 0,
> + .read_len = 100 },
> + { .seg_lengths = { 100, 200 },
> + .seg_count = 2,
> + .flags = MBUF_HEADER,
> + .read_off = sizeof(struct rte_ether_hdr),
> + .read_len = 150 },
> + { .seg_lengths = { 1000, 100 },
> + .seg_count = 2,
> + .flags = MBUF_NO_HEADER,
> + .read_off = 0,
> + .read_len = 1000 },
> + { .seg_lengths = { 1024, 0, 100 },
> + .seg_count = 3,
> + .flags = MBUF_NO_HEADER,
> + .read_off = 100,
> + .read_len = 1001 },
> + { .seg_lengths = { 1000, 1, 1000 },
> + .seg_count = 3,
> + .flags = MBUF_NO_HEADER,
> + .read_off = 1000,
> + .read_len = 2 },
> + { .seg_lengths = { MBUF_TEST_DATA_LEN, MBUF_TEST_DATA_LEN2,
> +  MBUF_TEST_DATA_LEN3, 800, 10 },
> + .seg_count = 5,
> + .flags = MBUF_NEG_TEST_READ,
> + .read_off = 1000,
> + .read_len = MBUF_DATA_SIZE },
> + };

The indentation is not very clear.

What about:

struct test_case test_cases[] = {
{
.seg_lengths = { 100, 100, 100 },
.seg_count = 3,
.flags = MBUF_NO_HEADER,
.read_off = 0,
.read_len = 300,
},
{
.seg_lengths = { 100, 125, 150 },
.seg_count = 3,
.flags = MBUF_NO_HEADER,
.read_off = 99,
.read_len = 201,
},
...

Or, if you prefer something shorter:

struct test_case test_cases[] = {
/* seg_lengths, seg_count, flags, read_off, read_len */
{ { 100, 100, 100 }, 3, MBUF_NO_HEADER, 0, 300, },
{ { 100, 125, 150 }, 3, MBUF_NO_HEADER, 99, 201, },
...

[...]

>  test_mbuf(void)
>  {
> @@ -1133,7 +1736,8 @@ test_mbuf(void)
>  
>   /* create pktmbuf pool if it does not exist */
>   pktmbuf_pool = rte_pktmbuf_pool_create("test_pktmbuf_pool",
> - NB_MBUF, 32, 0, MBUF_DATA_SIZE, SOCKET_ID_ANY);
> + NB_MBUF, MEMPOOL_CACHE_SIZE, 0, MBUF_DATA_SIZE,
> + SOCKET_ID_ANY);
>  
>   if (pktmbuf_pool == NULL) {
>   print

Re: [dpdk-dev] [PATCH v4 2/2] app/test: add unit test cases to mbuf

[Olivier Matz]

On Thu, Aug 08, 2019 at 02:34:20PM +0100, Lavanya Govindarajan wrote:
> From: Pallantla Poornima 
> 
> Added UT for the below four functions in test_mbuf.c
> rte_get_rx_ol_flag_list
> rte_get_tx_ol_flag_list
> rte_get_rx_ol_flag_name
> rte_get_tx_ol_flag_name
> 
> Signed-off-by: Pallantla Poornima 

I suggest to change the patch title from
"app/test: add unit test cases to mbuf"
to
"app/test: add unit test for mbuf flag names"

> ---
>  app/test/test_mbuf.c | 260 +++
>  1 file changed, 260 insertions(+)
> 
> diff --git a/app/test/test_mbuf.c b/app/test/test_mbuf.c
> index 28f3216c0..1a943518d 100644
> --- a/app/test/test_mbuf.c
> +++ b/app/test/test_mbuf.c
> @@ -42,6 +42,7 @@
>  #define MBUF_TEST_DATA_LEN3 256
>  #define MBUF_TEST_HDR1_LEN  20
>  #define MBUF_TEST_HDR2_LEN  30
> +#define MBUF_TEST_LEN   250
>  #define MBUF_TEST_ALL_HDRS_LEN  (MBUF_TEST_HDR1_LEN+MBUF_TEST_HDR2_LEN)
>  #define MBUF_TEST_SEG_SIZE  64
>  #define MBUF_TEST_BURST 8
> @@ -1132,6 +1133,245 @@ test_tx_offload(void)
>   return (v1 == v2) ? 0 : -EINVAL;
>  }
>  
> +
> +static int
> +test_get_rx_ol_flag_list(void)
> +{
> + int len, ret = 0;
> + char buf[256] = "";
> + int buflen = 0;
> +
> + /* Test case to check with null buffer */
> + ret = rte_get_rx_ol_flag_list(0, NULL, 0);
> + if (ret != -1)
> + GOTO_FAIL("%s expected: -1, received = %d\n", __func__, ret);
> +
> + /* Test case to check with zero buffer len */
> + ret = rte_get_rx_ol_flag_list(PKT_RX_L4_CKSUM_MASK, buf, 0);
> + if (ret != -1)
> + GOTO_FAIL("%s expected: -1, received = %d\n", __func__, ret);
> +
> + buflen = strlen(buf);
> + if (buflen != 0)
> + GOTO_FAIL("%s buffer should be empty, received = %d\n",
> + __func__, buflen);
> +
> + /* Test case to check with reduced buffer len */
> + len = sizeof(buf) - MBUF_TEST_LEN;
> + ret = rte_get_rx_ol_flag_list(0, buf, len);

Why using a #define for MBUF_TEST_LEN and not for char buf[256]?
Also, MBUF_TEST_LEN is not a very clear name.

So, I'd prefer to have an hardcoded value:

len = 5;
ret = rte_get_rx_ol_flag_list(0, buf, len);


> + if (ret != -1)
> + GOTO_FAIL("%s expected: -1, received = %d\n", __func__, ret);
> +
> + buflen = strlen(buf);
> + if (buflen != (len - 1))
> + GOTO_FAIL("%s invalid buffer length retrieved, expected: %d,"
> + "received = %d\n", __func__,
> + (len - 1), buflen);
> +
> + /* Test case to check with zero mask value */
> + ret = rte_get_rx_ol_flag_list(0, buf, sizeof(buf));
> + if (ret != 0)
> + GOTO_FAIL("%s expected: 0, received = %d\n", __func__, ret);
> +
> + buflen = strlen(buf);
> + if (buflen == 0)
> + GOTO_FAIL("%s expected: %s, received length = 0\n", __func__,
> + "non-zero, buffer should not be empty");
> +
> + /* Test case to check with valid mask value */
> + ret = rte_get_rx_ol_flag_list(PKT_RX_SEC_OFFLOAD, buf, sizeof(buf));
> + if (ret != 0)
> + GOTO_FAIL("%s expected: 0, received = %d\n", __func__, ret);
> +
> + buflen = strlen(buf);
> + if (buflen == 0)
> + GOTO_FAIL("%s expected: %s, received length = 0\n", __func__,
> + "non-zero, buffer should not be empty");
> +
> +
> + return 0;
> +fail:
> + return -1;
> +}
> +
> +static int
> +test_get_tx_ol_flag_list(void)
> +{

Same comment as rx.

[...]

> +struct flag_name {
> + uint64_t flag;
> + const char *name;
> +};
> +
> +static int
> +test_get_rx_ol_flag_name(void)
> +{
> + uint16_t i;
> + const char *flag_str = NULL;
> + const struct flag_name rx_flags[] = {
> + { PKT_RX_VLAN, "PKT_RX_VLAN" },
> + { PKT_RX_RSS_HASH, "PKT_RX_RSS_HASH" },
> + { PKT_RX_FDIR, "PKT_RX_FDIR"},
> + { PKT_RX_L4_CKSUM_BAD, "PKT_RX_L4_CKSUM_BAD"},
> + { PKT_RX_L4_CKSUM_GOOD, "PKT_RX_L4_CKSUM_GOOD"},
> + { PKT_RX_L4_CKSUM_NONE, "PKT_RX_L4_CKSUM_NONE"},
> + { PKT_RX_IP_CKSUM_BAD, "PKT_RX_IP_CKSUM_BAD"},
> + { PKT_RX_IP_CKSUM_GOOD, "PKT_RX_IP_CKSUM_GOOD"},
> + { PKT_RX_IP_CKSUM_NONE, "PKT_RX_IP_CKSUM_NONE"},
> + { PKT_RX_EIP_CKSUM_BAD, "PKT_RX_EIP_CKSUM_BAD" },
> + { PKT_RX_VLAN_STRIPPED, "PKT_RX_VLAN_STRIPPED" },
> + { PKT_RX_IEEE1588_PTP, "PKT_RX_IEEE1588_PTP"},
> + { PKT_RX_IEEE1588_TMST, "PKT_RX_IEEE1588_TMST"},
> + { PKT_RX_FDIR_ID, "PKT_RX_FDIR_ID"},
> + { PKT_RX_FDIR_FLX, "PKT_RX_FDIR_FLX"},
> + { PKT_RX_QINQ_STRIPPED, "PKT_RX_QINQ_STRIPPED" },
> + { PKT_RX_LRO, "PKT_RX_LRO" },
> + { PKT_RX_TIMESTAMP, "PKT_RX_TIMESTAMP"},
> + { PKT_RX_SEC_OFFLOAD, "PKT_RX_SEC_

Re: [dpdk-dev] [PATCH] remove unneeded eal header inclusion

[Bruce Richardson]

On Mon, Aug 12, 2019 at 12:25:03PM +0100, Wiles, Keith wrote:
> 
> 
> > On Aug 12, 2019, at 1:53 AM, David Marchand  
> > wrote:
> > 
> > Restrict this header inclusion to its real users.
> > 
> > Fixes: 028669bc9f0d ("eal: hide shared memory config")
> > 
> > Signed-off-by: David Marchand 
> 
> The only thing I would suggest is to add the name of the header file in the 
> subject or body of the commit, as currently it is not obvious reading the 
> commit title or body.
> 
> Regards,
> Keith

+1

[dpdk-dev] [PATCH 00/12] FIPS improvements

[michaelsh]

From: Michael Shamis 

Added support for ECB mode in TDES and AES.
Fixed some bugs in TDES and AES-GCM.

Michael Shamis (12):
  examples/fips: added support for SHA algorithm in FIPS tests
  examples/fips: added support for TDES ECB mode in FIPS tests
  examples/fips: added support AES ECB mode in FIPS tests
  examples/fips: fix bad return code in fips_test_parse_header()
  examples/fips: AES-GCM vectors will use aead structure
  examples/fips: set initial IV in AES-GCM if configured only salt value
  examples/fips: keep digest after crypto text
  examples/fips: AES-GCM decryption vectors fix
  examples/fips: fix KEY and PT output prints for TDES mode
  examples/fips: supported IV, PT and CT init for TDES ECB mode
  examples/fips: algorithm definition by folder if it's not in file
  examples/fips: erroneous overwrite of PLAINTEXT after DECRYPT

 examples/fips_validation/fips_validation.c|  92 ++--
 examples/fips_validation/fips_validation.h|   7 +
 .../fips_validation/fips_validation_aes.c |   1 +
 .../fips_validation/fips_validation_gcm.c |  39 +++-
 .../fips_validation/fips_validation_tdes.c|   7 +
 examples/fips_validation/main.c   | 204 +++---
 6 files changed, 301 insertions(+), 49 deletions(-)

-- 
2.23.0

[dpdk-dev] [PATCH 02/12] examples/fips: added support for TDES ECB mode in FIPS tests

[michaelsh]

From: Michael Shamis 

Signed-off-by: Michael Shamis 
---
 examples/fips_validation/fips_validation.c|  1 +
 examples/fips_validation/fips_validation.h|  7 +
 .../fips_validation/fips_validation_tdes.c|  7 +
 examples/fips_validation/main.c   | 27 ---
 4 files changed, 38 insertions(+), 4 deletions(-)

diff --git a/examples/fips_validation/fips_validation.c 
b/examples/fips_validation/fips_validation.c
index 80fd482a1..fe3bcc386 100644
--- a/examples/fips_validation/fips_validation.c
+++ b/examples/fips_validation/fips_validation.c
@@ -259,6 +259,7 @@ fips_test_init(const char *req_file_path, const char 
*rsp_file_path,
 
fips_test_clear();
 
+   strcpy(info.file_name, req_file_path);
info.algo = FIPS_TEST_ALGO_MAX;
if (parse_file_type(req_file_path) < 0) {
RTE_LOG(ERR, USER1, "File %s type not supported\n",
diff --git a/examples/fips_validation/fips_validation.h 
b/examples/fips_validation/fips_validation.h
index b604db9ec..d487fb005 100644
--- a/examples/fips_validation/fips_validation.h
+++ b/examples/fips_validation/fips_validation.h
@@ -105,6 +105,11 @@ enum fips_tdes_test_types {
TDES_MMT /* Multi block Message Test */
 };
 
+enum fips_tdes_test_mode {
+   TDES_MODE_CBC = 0,
+   TDES_MODE_ECB
+};
+
 enum fips_ccm_test_types {
CCM_VADT= 1, /* Variable Associated Data Test */
CCM_VPT, /* Variable Payload Test */
@@ -130,6 +135,7 @@ struct hmac_interim_data {
 
 struct tdes_interim_data {
enum fips_tdes_test_types test_type;
+   enum fips_tdes_test_mode test_mode;
uint32_t nb_keys;
 };
 
@@ -156,6 +162,7 @@ struct fips_test_interim_info {
char *vec[MAX_LINE_PER_VECTOR];
uint32_t nb_vec_lines;
char device_name[MAX_STRING_SIZE];
+   char file_name[MAX_STRING_SIZE];
 
union {
struct aesavs_interim_data aes_data;
diff --git a/examples/fips_validation/fips_validation_tdes.c 
b/examples/fips_validation/fips_validation_tdes.c
index 15ee434e1..d7f4d58b0 100644
--- a/examples/fips_validation/fips_validation_tdes.c
+++ b/examples/fips_validation/fips_validation_tdes.c
@@ -12,6 +12,7 @@
 
 #define NEW_LINE_STR   "#"
 #define TEST_TYPE_KEY  " for CBC"
+#define TEST_TYPE_ECB_KEY  " for ECB"
 #define TEST_CBCI_KEY  " for CBCI"
 
 #define ENC_STR"[ENCRYPT]"
@@ -250,6 +251,12 @@ parse_test_tdes_init(void)
if (strstr(line, test_types[j].desc)) {
info.interim_info.tdes_data.test_type =
test_types[j].type;
+   if (strstr(line, TEST_TYPE_ECB_KEY))
+   info.interim_info.tdes_data.test_mode =
+   TDES_MODE_ECB;
+   else
+   info.interim_info.tdes_data.test_mode =
+   TDES_MODE_CBC;
break;
}
}
diff --git a/examples/fips_validation/main.c b/examples/fips_validation/main.c
index 813534068..7a379bc99 100644
--- a/examples/fips_validation/main.c
+++ b/examples/fips_validation/main.c
@@ -689,16 +689,24 @@ prepare_tdes_xform(struct rte_crypto_sym_xform *xform)
 
xform->type = RTE_CRYPTO_SYM_XFORM_CIPHER;
 
-   cipher_xform->algo = RTE_CRYPTO_CIPHER_3DES_CBC;
+   if (info.interim_info.tdes_data.test_mode == TDES_MODE_CBC)
+   cipher_xform->algo = RTE_CRYPTO_CIPHER_3DES_CBC;
+   else
+   cipher_xform->algo = RTE_CRYPTO_CIPHER_3DES_ECB;
cipher_xform->op = (info.op == FIPS_TEST_ENC_AUTH_GEN) ?
RTE_CRYPTO_CIPHER_OP_ENCRYPT :
RTE_CRYPTO_CIPHER_OP_DECRYPT;
cipher_xform->key.data = vec.cipher_auth.key.val;
cipher_xform->key.length = vec.cipher_auth.key.len;
-   cipher_xform->iv.length = vec.iv.len;
-   cipher_xform->iv.offset = IV_OFF;
 
-   cap_idx.algo.cipher = RTE_CRYPTO_CIPHER_3DES_CBC;
+   if (cipher_xform->algo == RTE_CRYPTO_CIPHER_3DES_CBC) {
+   cipher_xform->iv.length = vec.iv.len;
+   cipher_xform->iv.offset = IV_OFF;
+   } else {
+   cipher_xform->iv.length = 0;
+   cipher_xform->iv.offset = 0;
+   }
+   cap_idx.algo.cipher = cipher_xform->algo;
cap_idx.type = RTE_CRYPTO_SYM_XFORM_CIPHER;
 
cap = rte_cryptodev_sym_capability_get(env.dev_id, &cap_idx);
@@ -1387,6 +1395,17 @@ init_test_ops(void)
test_ops.test = fips_generic_test;
break;
default:
+   if (strstr(info.file_name, "TECB") ||
+   strstr(info.file_name, "TCBC")) {
+   info.algo = FIPS_TEST_ALGO_TDES;
+   test_ops.prepare_op = pre

[dpdk-dev] [PATCH 03/12] examples/fips: added support AES ECB mode in FIPS tests

[michaelsh]

From: Michael Shamis 

Signed-off-by: Michael Shamis 
---
 .../fips_validation/fips_validation_aes.c |  1 +
 examples/fips_validation/main.c   | 96 +--
 2 files changed, 91 insertions(+), 6 deletions(-)

diff --git a/examples/fips_validation/fips_validation_aes.c 
b/examples/fips_validation/fips_validation_aes.c
index 8cbc158eb..010a82627 100644
--- a/examples/fips_validation/fips_validation_aes.c
+++ b/examples/fips_validation/fips_validation_aes.c
@@ -44,6 +44,7 @@ struct aes_test_algo {
enum rte_crypto_cipher_algorithm algo;
 } const algo_con[] = {
{"CBC", RTE_CRYPTO_CIPHER_AES_CBC},
+   {"ECB", RTE_CRYPTO_CIPHER_AES_ECB},
 };
 
 static int
diff --git a/examples/fips_validation/main.c b/examples/fips_validation/main.c
index 7a379bc99..c83763b13 100644
--- a/examples/fips_validation/main.c
+++ b/examples/fips_validation/main.c
@@ -649,16 +649,24 @@ prepare_aes_xform(struct rte_crypto_sym_xform *xform)
 
xform->type = RTE_CRYPTO_SYM_XFORM_CIPHER;
 
-   cipher_xform->algo = RTE_CRYPTO_CIPHER_AES_CBC;
+   if (info.interim_info.aes_data.cipher_algo == RTE_CRYPTO_CIPHER_AES_CBC)
+   cipher_xform->algo = RTE_CRYPTO_CIPHER_AES_CBC;
+   else
+   cipher_xform->algo = RTE_CRYPTO_CIPHER_AES_ECB;
+
cipher_xform->op = (info.op == FIPS_TEST_ENC_AUTH_GEN) ?
RTE_CRYPTO_CIPHER_OP_ENCRYPT :
RTE_CRYPTO_CIPHER_OP_DECRYPT;
cipher_xform->key.data = vec.cipher_auth.key.val;
cipher_xform->key.length = vec.cipher_auth.key.len;
-   cipher_xform->iv.length = vec.iv.len;
-   cipher_xform->iv.offset = IV_OFF;
-
-   cap_idx.algo.cipher = RTE_CRYPTO_CIPHER_AES_CBC;
+   if (cipher_xform->algo == RTE_CRYPTO_CIPHER_AES_CBC) {
+   cipher_xform->iv.length = vec.iv.len;
+   cipher_xform->iv.offset = IV_OFF;
+   } else {
+   cipher_xform->iv.length = 0;
+   cipher_xform->iv.offset = 0;
+   }
+   cap_idx.algo.cipher = cipher_xform->algo;
cap_idx.type = RTE_CRYPTO_SYM_XFORM_CIPHER;
 
cap = rte_cryptodev_sym_capability_get(env.dev_id, &cap_idx);
@@ -1059,7 +1067,6 @@ fips_mct_tdes_test(void)
fprintf(info.fp_wr, "Bypass\n");
return 0;
}
-
return ret;
}
 
@@ -1160,6 +1167,80 @@ fips_mct_tdes_test(void)
return 0;
 }
 
+static int
+fips_mct_aes_ecb_test(void)
+{
+#define AES_BLOCK_SIZE 16
+#define AES_EXTERN_ITER100
+#define AES_INTERN_ITER1000
+   struct fips_val val, val_key;
+   uint8_t prev_out[AES_BLOCK_SIZE] = {0};
+   uint32_t i, j, k;
+   int ret;
+
+   for (i = 0; i < AES_EXTERN_ITER; i++) {
+   if (i != 0)
+   update_info_vec(i);
+
+   fips_test_write_one_case();
+
+   for (j = 0; j < AES_INTERN_ITER; j++) {
+   ret = fips_run_test();
+   if (ret < 0) {
+   if (ret == -EPERM) {
+   fprintf(info.fp_wr, "Bypass\n");
+   return 0;
+   }
+
+   return ret;
+   }
+
+   get_writeback_data(&val);
+
+   if (info.op == FIPS_TEST_ENC_AUTH_GEN)
+   memcpy(vec.pt.val, val.val, AES_BLOCK_SIZE);
+   else
+   memcpy(vec.ct.val, val.val, AES_BLOCK_SIZE);
+
+   if (j == AES_INTERN_ITER - 1)
+   continue;
+
+   memcpy(prev_out, val.val, AES_BLOCK_SIZE);
+   }
+
+   info.parse_writeback(&val);
+   fprintf(info.fp_wr, "\n");
+
+   if (i == AES_EXTERN_ITER - 1)
+   continue;
+
+   /** update key */
+   memcpy(&val_key, &vec.cipher_auth.key, sizeof(val_key));
+   for (k = 0; k < vec.cipher_auth.key.len; k++) {
+   switch (vec.cipher_auth.key.len) {
+   case 16:
+   val_key.val[k] ^= val.val[k];
+   break;
+   case 24:
+   if (k < 8)
+   val_key.val[k] ^= prev_out[k + 8];
+   else
+   val_key.val[k] ^= val.val[k - 8];
+   break;
+   case 32:
+   if (k < 16)
+   val_key.val[k] ^= prev_out[k];
+   else
+   val_key.val[k] ^= 

[dpdk-dev] [PATCH 01/12] examples/fips: added support for SHA algorithm in FIPS tests

[michaelsh]

From: Michael Shamis 

Signed-off-by: Michael Shamis 
---
 examples/fips_validation/fips_validation.c | 12 +++-
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/examples/fips_validation/fips_validation.c 
b/examples/fips_validation/fips_validation.c
index 8d43b267e..80fd482a1 100644
--- a/examples/fips_validation/fips_validation.c
+++ b/examples/fips_validation/fips_validation.c
@@ -145,11 +145,13 @@ fips_test_parse_header(void)
if (ret < 0)
return 0;
} else if (strstr(info.vec[i], "SHA-")) {
-   algo_parsed = 1;
-   info.algo = FIPS_TEST_ALGO_SHA;
-   ret = parse_test_sha_init();
-   if (ret < 0)
-   return ret;
+   if (info.algo != FIPS_TEST_ALGO_HMAC) {
+   algo_parsed = 1;
+   info.algo = FIPS_TEST_ALGO_SHA;
+   ret = parse_test_sha_init();
+   if (ret < 0)
+   return ret;
+   }
}
}
 
-- 
2.23.0

[dpdk-dev] [PATCH 09/12] examples/fips: fix KEY and PT output prints for TDES mode

[michaelsh]

From: Michael Shamis 

Signed-off-by: Michael Shamis 
---
 examples/fips_validation/fips_validation.c | 20 
 1 file changed, 20 insertions(+)

diff --git a/examples/fips_validation/fips_validation.c 
b/examples/fips_validation/fips_validation.c
index 91e6d48e7..ba513672e 100644
--- a/examples/fips_validation/fips_validation.c
+++ b/examples/fips_validation/fips_validation.c
@@ -11,6 +11,10 @@
 
 #include "fips_validation.h"
 
+#define COUNT0_STR "COUNT = 0  "
+#define KEY_STR"KEY"
+#define NK_STR "NumKey"
+
 #define skip_white_spaces(pos) \
 ({ \
__typeof__(pos) _p = (pos); \
@@ -68,6 +72,22 @@ fips_test_fetch_one_block(void)
if (size == 0)
break;
 
+   /* if first line is KEY-line then insert COUNT-line */
+   if (i == 0) {
+   if (strstr(info.one_line_text, KEY_STR)) {
+   info.vec[0] = calloc(1, sizeof(COUNT0_STR));
+   strlcpy(info.vec[0],
+   COUNT0_STR,
+   sizeof(COUNT0_STR));
+   i = 1;
+   info.nb_vec_lines = 1;
+   }
+   }
+
+   /* don't copy NumKey-line */
+   if (strstr(info.one_line_text, NK_STR))
+   break;
+
info.vec[i] = calloc(1, size + 5);
if (info.vec[i] == NULL)
goto error_exit;
-- 
2.23.0

[dpdk-dev] [PATCH 06/12] examples/fips: set initial IV in AES-GCM if configured only salt value

[michaelsh]

From: Michael Shamis 

Configurated AES-GCM IV may include only salt value which length
is 12B. In this case driver should set second part of IV to
initial value = 0x1.

Signed-off-by: Michael Shamis 
---
 examples/fips_validation/main.c | 11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/examples/fips_validation/main.c b/examples/fips_validation/main.c
index c83763b13..895bfa7d8 100644
--- a/examples/fips_validation/main.c
+++ b/examples/fips_validation/main.c
@@ -25,6 +25,7 @@
 #define CRYPTODEV_BK_DIR_KEY   "broken-test-dir"
 #define CRYPTODEV_ENC_KEYWORD  "enc"
 #define CRYPTODEV_DEC_KEYWORD  "dec"
+#define IV_SALT_LEN 12
 
 struct fips_test_vector vec;
 struct fips_test_interim_info info;
@@ -580,10 +581,16 @@ prepare_aead_op(void)
__rte_crypto_op_reset(env.op, RTE_CRYPTO_OP_TYPE_SYMMETRIC);
rte_pktmbuf_reset(env.mbuf);
 
-   if (info.algo == FIPS_TEST_ALGO_AES_CCM)
+   if (info.algo == FIPS_TEST_ALGO_AES_CCM) {
memcpy(iv + 1, vec.iv.val, vec.iv.len);
-   else
+   } else {
memcpy(iv, vec.iv.val, vec.iv.len);
+   /* Set initial IV if specified only salt IV value */
+   if (vec.iv.len == IV_SALT_LEN) {
+   memset(&iv[vec.iv.len], 0, 4);
+   iv[vec.iv.len + 3] = 1;
+   }
+   }
 
sym->m_src = env.mbuf;
sym->aead.data.offset = 0;
-- 
2.23.0

[dpdk-dev] [PATCH 04/12] examples/fips: fix bad return code in fips_test_parse_header()

[michaelsh]

From: Michael Shamis 

Returning correct error value by fips_test_parse_header()
allows graceful exit of fips application.

Signed-off-by: Michael Shamis 
---
 examples/fips_validation/fips_validation.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/examples/fips_validation/fips_validation.c 
b/examples/fips_validation/fips_validation.c
index fe3bcc386..91e6d48e7 100644
--- a/examples/fips_validation/fips_validation.c
+++ b/examples/fips_validation/fips_validation.c
@@ -125,13 +125,13 @@ fips_test_parse_header(void)
info.algo = FIPS_TEST_ALGO_AES_CMAC;
ret = parse_test_cmac_init();
if (ret < 0)
-   return 0;
+   return ret;
} else if (strstr(info.vec[i], "CCM")) {
algo_parsed = 1;
info.algo = FIPS_TEST_ALGO_AES_CCM;
ret = parse_test_ccm_init();
if (ret < 0)
-   return 0;
+   return ret;
} else if (strstr(info.vec[i], "HMAC")) {
algo_parsed = 1;
info.algo = FIPS_TEST_ALGO_HMAC;
@@ -143,7 +143,7 @@ fips_test_parse_header(void)
info.algo = FIPS_TEST_ALGO_TDES;
ret = parse_test_tdes_init();
if (ret < 0)
-   return 0;
+   return ret;
} else if (strstr(info.vec[i], "SHA-")) {
if (info.algo != FIPS_TEST_ALGO_HMAC) {
algo_parsed = 1;
-- 
2.23.0

[dpdk-dev] [PATCH 11/12] examples/fips: algorithm definition by folder if it's not in file

[michaelsh]

From: Michael Shamis 

In order to find algorithm used the folder name if it is
not defined within the file.

Signed-off-by: Michael Shamis 
---
 examples/fips_validation/fips_validation.c | 42 ++
 1 file changed, 42 insertions(+)

diff --git a/examples/fips_validation/fips_validation.c 
b/examples/fips_validation/fips_validation.c
index ba513672e..fcc0c985d 100644
--- a/examples/fips_validation/fips_validation.c
+++ b/examples/fips_validation/fips_validation.c
@@ -248,6 +248,48 @@ fips_test_parse_header(void)
fprintf(info.fp_wr, "%s\n", info.vec[i]);
}
 
+   /* use folder name if algorithm is not found yet*/
+   if (info.algo == FIPS_TEST_ALGO_MAX) {
+   if (strstr(info.file_name, "AESVS")) {
+   info.algo = FIPS_TEST_ALGO_AES;
+   ret = parse_test_aes_init();
+   if (ret < 0)
+   return ret;
+   } else if (strstr(info.file_name, "GCM")) {
+   info.algo = FIPS_TEST_ALGO_AES_GCM;
+   ret = parse_test_gcm_init();
+   if (ret < 0)
+   return ret;
+   } else if (strstr(info.file_name, "CMAC")) {
+   info.algo = FIPS_TEST_ALGO_AES_CMAC;
+   ret = parse_test_cmac_init();
+   if (ret < 0)
+   return ret;
+   } else if (strstr(info.file_name, "CCM")) {
+   info.algo = FIPS_TEST_ALGO_AES_CCM;
+   ret = parse_test_ccm_init();
+   if (ret < 0)
+   return ret;
+   } else if (strstr(info.file_name, "HMAC")) {
+   info.algo = FIPS_TEST_ALGO_HMAC;
+   ret = parse_test_hmac_init();
+   if (ret < 0)
+   return ret;
+   } else if (strstr(info.file_name, "TDES")) {
+   info.algo = FIPS_TEST_ALGO_TDES;
+   ret = parse_test_tdes_init();
+   if (ret < 0)
+   return ret;
+   } else if (strstr(info.file_name, "SHA-")) {
+   if (info.algo != FIPS_TEST_ALGO_HMAC) {
+   info.algo = FIPS_TEST_ALGO_SHA;
+   ret = parse_test_sha_init();
+   if (ret < 0)
+   return ret;
+   }
+   }
+   }
+
return 0;
 }
 
-- 
2.23.0

[dpdk-dev] [PATCH 07/12] examples/fips: keep digest after crypto text

[michaelsh]

From: Michael Shamis 

Fix of GCM FIPS bug: ICV was not copied after the crypto text
in decryption operation so SAM failed to check authentication
in GCM mode.

Signed-off-by: Michael Shamis 
---
 examples/fips_validation/main.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/examples/fips_validation/main.c b/examples/fips_validation/main.c
index 895bfa7d8..1d621f60a 100644
--- a/examples/fips_validation/main.c
+++ b/examples/fips_validation/main.c
@@ -636,6 +636,10 @@ prepare_aead_op(void)
}
 
memcpy(ct, vec.ct.val, vec.ct.len);
+
+   /* keep digest after crypto text */
+   memcpy(ct + vec.ct.len, vec.aead.digest.val,
+   vec.aead.digest.len);
sym->aead.data.length = vec.ct.len;
sym->aead.digest.data = vec.aead.digest.val;
sym->aead.digest.phys_addr = rte_malloc_virt2iova(
-- 
2.23.0

[dpdk-dev] [PATCH 05/12] examples/fips: AES-GCM vectors will use aead structure

[michaelsh]

From: Michael Shamis 

Before the fix AES-GCM vectores were defined by cipher_auth
structure but handled by aead structure and that leads to
FIPS test failure.

Signed-off-by: Michael Shamis 
---
 examples/fips_validation/fips_validation_gcm.c | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/examples/fips_validation/fips_validation_gcm.c 
b/examples/fips_validation/fips_validation_gcm.c
index 0509b101a..ea48ddf70 100644
--- a/examples/fips_validation/fips_validation_gcm.c
+++ b/examples/fips_validation/fips_validation_gcm.c
@@ -34,29 +34,29 @@
 #define NEG_TEST_STR   "FAIL"
 
 struct fips_test_callback gcm_dec_vectors[] = {
-   {KEY_STR, parse_uint8_known_len_hex_str, &vec.cipher_auth.key},
+   {KEY_STR, parse_uint8_known_len_hex_str, &vec.aead.key},
{IV_STR, parse_uint8_known_len_hex_str, &vec.iv},
{CT_STR, parse_uint8_known_len_hex_str, &vec.ct},
-   {AAD_STR, parse_uint8_known_len_hex_str, &vec.cipher_auth.aad},
+   {AAD_STR, parse_uint8_known_len_hex_str, &vec.aead.aad},
{TAG_STR, parse_uint8_known_len_hex_str,
-   &vec.cipher_auth.digest},
+   &vec.aead.digest},
{NULL, NULL, NULL} /**< end pointer */
 };
 struct fips_test_callback gcm_interim_vectors[] = {
-   {KEYLEN_STR, parser_read_uint32_bit_val, &vec.cipher_auth.key},
+   {KEYLEN_STR, parser_read_uint32_bit_val, &vec.aead.key},
{IVLEN_STR, parser_read_uint32_bit_val, &vec.iv},
{PTLEN_STR, parser_read_uint32_bit_val, &vec.pt},
-   {AADLEN_STR, parser_read_uint32_bit_val, &vec.cipher_auth.aad},
+   {AADLEN_STR, parser_read_uint32_bit_val, &vec.aead.aad},
{TAGLEN_STR, parser_read_uint32_bit_val,
-   &vec.cipher_auth.digest},
+   &vec.aead.digest},
{NULL, NULL, NULL} /**< end pointer */
 };
 
 struct fips_test_callback gcm_enc_vectors[] = {
-   {KEY_STR, parse_uint8_known_len_hex_str, &vec.cipher_auth.key},
+   {KEY_STR, parse_uint8_known_len_hex_str, &vec.aead.key},
{IV_STR, parse_uint8_known_len_hex_str, &vec.iv},
{PT_STR, parse_uint8_known_len_hex_str, &vec.pt},
-   {AAD_STR, parse_uint8_known_len_hex_str, &vec.cipher_auth.aad},
+   {AAD_STR, parse_uint8_known_len_hex_str, &vec.aead.aad},
{NULL, NULL, NULL} /**< end pointer */
 };
 
-- 
2.23.0

[dpdk-dev] [PATCH 10/12] examples/fips: supported IV, PT and CT init for TDES ECB mode

[michaelsh]

From: Michael Shamis 

Signed-off-by: Michael Shamis 
---
 examples/fips_validation/main.c | 66 +
 1 file changed, 50 insertions(+), 16 deletions(-)

diff --git a/examples/fips_validation/main.c b/examples/fips_validation/main.c
index 1d621f60a..3eda0f554 100644
--- a/examples/fips_validation/main.c
+++ b/examples/fips_validation/main.c
@@ -1064,6 +1064,7 @@ fips_mct_tdes_test(void)
uint8_t prev_in[TDES_BLOCK_SIZE] = {0};
uint32_t i, j, k;
int ret;
+   int test_mode = info.interim_info.tdes_data.test_mode;
 
for (i = 0; i < TDES_EXTERN_ITER; i++) {
if (i != 0)
@@ -1090,25 +1091,50 @@ fips_mct_tdes_test(void)
memcpy(prev_out, val.val, TDES_BLOCK_SIZE);
 
if (info.op == FIPS_TEST_ENC_AUTH_GEN) {
-   memcpy(vec.pt.val, vec.iv.val,
-   TDES_BLOCK_SIZE);
-   memcpy(vec.iv.val, val.val,
-   TDES_BLOCK_SIZE);
+   if (test_mode == TDES_MODE_ECB) {
+   memcpy(vec.pt.val, val.val,
+  TDES_BLOCK_SIZE);
+   } else {
+   memcpy(vec.pt.val, vec.iv.val,
+  TDES_BLOCK_SIZE);
+   memcpy(vec.iv.val, val.val,
+  TDES_BLOCK_SIZE);
+   }
+
} else {
-   memcpy(vec.iv.val, vec.ct.val,
-   TDES_BLOCK_SIZE);
-   memcpy(vec.ct.val, val.val,
-   TDES_BLOCK_SIZE);
+   if (test_mode == TDES_MODE_ECB) {
+   memcpy(vec.ct.val, val.val,
+  TDES_BLOCK_SIZE);
+   } else {
+   memcpy(vec.iv.val, vec.ct.val,
+  TDES_BLOCK_SIZE);
+   memcpy(vec.ct.val, val.val,
+  TDES_BLOCK_SIZE);
+   }
}
continue;
}
 
if (info.op == FIPS_TEST_ENC_AUTH_GEN) {
-   memcpy(vec.iv.val, val.val, TDES_BLOCK_SIZE);
-   memcpy(vec.pt.val, prev_out, TDES_BLOCK_SIZE);
+   if (test_mode == TDES_MODE_ECB) {
+   memcpy(vec.pt.val, val.val,
+  TDES_BLOCK_SIZE);
+   } else {
+   memcpy(vec.iv.val, val.val,
+  TDES_BLOCK_SIZE);
+   memcpy(vec.pt.val, prev_out,
+  TDES_BLOCK_SIZE);
+   }
} else {
-   memcpy(vec.iv.val, vec.ct.val, TDES_BLOCK_SIZE);
-   memcpy(vec.ct.val, val.val, TDES_BLOCK_SIZE);
+   if (test_mode == TDES_MODE_ECB) {
+   memcpy(vec.ct.val, val.val,
+  TDES_BLOCK_SIZE);
+   } else {
+   memcpy(vec.iv.val, vec.ct.val,
+  TDES_BLOCK_SIZE);
+   memcpy(vec.ct.val, val.val,
+  TDES_BLOCK_SIZE);
+   }
}
 
if (j == TDES_INTERN_ITER - 1)
@@ -1167,11 +1193,19 @@ fips_mct_tdes_test(void)
val_key.val[k] : (val_key.val[k] ^ 0x1);
 
if (info.op == FIPS_TEST_ENC_AUTH_GEN) {
-   memcpy(vec.iv.val, val.val, TDES_BLOCK_SIZE);
-   memcpy(vec.pt.val, prev_out, TDES_BLOCK_SIZE);
+   if (test_mode == TDES_MODE_ECB) {
+   memcpy(vec.pt.val, val.val, TDES_BLOCK_SIZE);
+   } else {
+   memcpy(vec.iv.val, val.val, TDES_BLOC

[dpdk-dev] [PATCH 08/12] examples/fips: AES-GCM decryption vectors fix

[michaelsh]

From: Michael Shamis 

AES-GCM CAVS vectors for decryption set PTlen (plain text length)
but provide crypto text and application expected CTlen to be not
null. Now we assign PTlen to CTlen in decryption scenario and
it allows to application to handle AES-GCM decryption vectors.

Signed-off-by: Michael Shamis 
---
 .../fips_validation/fips_validation_gcm.c | 23 ++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/examples/fips_validation/fips_validation_gcm.c 
b/examples/fips_validation/fips_validation_gcm.c
index ea48ddf70..f68b4ea82 100644
--- a/examples/fips_validation/fips_validation_gcm.c
+++ b/examples/fips_validation/fips_validation_gcm.c
@@ -33,10 +33,15 @@
 
 #define NEG_TEST_STR   "FAIL"
 
+static int
+parse_uint8_known_len_hex_str_dec(const char *key,
+   char *src,
+   struct fips_val *val);
+
 struct fips_test_callback gcm_dec_vectors[] = {
{KEY_STR, parse_uint8_known_len_hex_str, &vec.aead.key},
{IV_STR, parse_uint8_known_len_hex_str, &vec.iv},
-   {CT_STR, parse_uint8_known_len_hex_str, &vec.ct},
+   {CT_STR, parse_uint8_known_len_hex_str_dec, &vec.ct},
{AAD_STR, parse_uint8_known_len_hex_str, &vec.aead.aad},
{TAG_STR, parse_uint8_known_len_hex_str,
&vec.aead.digest},
@@ -123,3 +128,19 @@ parse_test_gcm_init(void)
 
return 0;
 }
+
+static int
+parse_uint8_known_len_hex_str_dec(const char *key,
+   char *src,
+   struct fips_val *val)
+{
+   /* AES-GCM CAVS vectors for decryption set PTlen (plain text length)
+* but provide crypto text.
+* In order to compensate the behavior we assign PTlen to CTlen
+* (crypto text length) which is used for calculations
+*/
+   if (info.op == FIPS_TEST_DEC_AUTH_VERIF)
+   vec.ct.len = vec.pt.len;
+
+   return parse_uint8_known_len_hex_str(key, src, val);
+}
-- 
2.23.0

[dpdk-dev] [PATCH 12/12] examples/fips: erroneous overwrite of PLAINTEXT after DECRYPT

[michaelsh]

From: Michael Shamis 

fix erroneous overwrite of PLAINTEXT-line after [DECRYPT] tag

Signed-off-by: Michael Shamis 
---
 examples/fips_validation/fips_validation.c | 11 +++
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/examples/fips_validation/fips_validation.c 
b/examples/fips_validation/fips_validation.c
index fcc0c985d..4d0f240b8 100644
--- a/examples/fips_validation/fips_validation.c
+++ b/examples/fips_validation/fips_validation.c
@@ -401,10 +401,13 @@ fips_test_parse_one_case(void)
}
 
if (is_interim) {
-   for (i = 0; i < info.nb_vec_lines; i++)
-   fprintf(info.fp_wr, "%s\n", info.vec[i]);
-   fprintf(info.fp_wr, "\n");
-   return 1;
+   if (!(strstr(info.vec[0], "DECRYPT") &&
+ info.nb_vec_lines > 1)) {
+   for (i = 0; i < info.nb_vec_lines; i++)
+   fprintf(info.fp_wr, "%s\n", info.vec[i]);
+   fprintf(info.fp_wr, "\n");
+   return 1;
+   }
}
 
for (i = 0; i < info.nb_vec_lines; i++) {
-- 
2.23.0

Re: [dpdk-dev] [PATCH 1/2] timer: use rte_mp_msg to pass TSC hz to secondary procs

[Bruce Richardson]

On Thu, Aug 15, 2019 at 04:27:35AM -0700, Jim Harris wrote:
> rte_eal_init() is much faster in secondary processes since
> hugepages don't need to be zeroed.  But there's still
> non-trivial delays in the timer subsystem initialization
> due to the 100ms sleep used to calculate TSC hz.  So use
> the rte_mp_msg framework to allow secondary processes
> to get the TSC hz from the primary process.
> 
> This cuts rte_eal_init() execution time in a secondary
> process from 165ms to 66ms in my test program.
> 
> Signed-off-by: Jim Harris 
> ---

Rather than messaging, can we not just move the CPU frequency to being
stored in a shared memory location? It's not something where different
processes are going to need to be provided with different values.

Re: [dpdk-dev] [PATCH 0/2] IXGBE vPMD changes for aarch64

[Ferruh Yigit]

On 8/26/2019 3:52 AM, Ruifeng Wang (Arm Technology China) wrote:
> Hi Xiaolong,
> 
>> -Original Message-
>> From: Ye Xiaolong 
>> Sent: Sunday, August 25, 2019 09:34
>> To: Ruifeng Wang (Arm Technology China) 
>> Cc: jer...@marvell.com; Gavin Hu (Arm Technology China)
>> ; dev@dpdk.org; Honnappa Nagarahalli
>> ; nd 
>> Subject: Re: [dpdk-dev] [PATCH 0/2] IXGBE vPMD changes for aarch64
>>
>> Hi,
>>
>> Thanks for the patches, could you also provide the Fixes tag and cc stable?
>> The patchset looks good to me.
> 
> Code changes in both patches are not for bug fixing.
> Patch 1/2 includes fix for code comments. I don't think it deserves a Fixes 
> tag or backporting. Can we skip the Fixes tag?

In 1/2 a memory barrier is removed, it means it was wrong to add it at first
place and you are fixing it, no?


Performance improvements are in gray are, but if there is no ABI/API break why
not take is performance fix and backport and have the performance improvement in
LTS?
Also I think taking as much as possible may help to maintain LTS, since it
reduces the chance of conflict in later commits, LTS is two years and these
small things can accumulate and make getting important fixes hard by time.

Is there any specific reason not to backport these patches to LTS releases?


> 
>>
>> Thanks,
>> Xiaolong
>>
>> On 08/13, Ruifeng Wang wrote:
>>> Couple of changes to IXGBE vector PMD on aarch64 platform.
>>> An unnecessary memory barrier was identified and removed.
>>> Also part of processing was replaced with NEON intrinsics.
>>> Both of the changes will help to improve performance.
>>>
>>> Ruifeng Wang (2):
>>>  net/ixgbe: remove barrier in vPMD for aarch64
>>>  net/ixgbe: use neon intrinsics to count packet for aarch64
>>>
>>> drivers/net/ixgbe/ixgbe_rxtx_vec_neon.c | 32 -
>>> 1 file changed, 16 insertions(+), 16 deletions(-)
>>>
>>> --
>>> 2.17.1
>>>

[dpdk-dev] [PATCH 02/63] net/ice/base: add function to get FW mode

[Qi Zhang]

Add a helper function to get FW mode. The FW mode can be normal,
debug, recovery or rollback.

This makes ice_is_fw_in_rec_mode redundant, so remove it.

Signed-off-by: Anirudh Venkataramanan 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_common.c | 23 ---
 drivers/net/ice/base/ice_common.h |  4 ++--
 2 files changed, 18 insertions(+), 9 deletions(-)

diff --git a/drivers/net/ice/base/ice_common.c 
b/drivers/net/ice/base/ice_common.c
index 52fd8c897..681740cee 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -4102,16 +4102,25 @@ ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
 }
 
 /**
- * ice_is_fw_in_rec_mode
+ * ice_get_fw_mode - returns FW mode
  * @hw: pointer to the HW struct
- *
- * This function returns true if fw is in recovery mode
  */
-bool ice_is_fw_in_rec_mode(struct ice_hw *hw)
+enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw)
 {
-   u32 reg;
+#define ICE_FW_MODE_DBG_M BIT(0)
+#define ICE_FW_MODE_REC_M BIT(1)
+#define ICE_FW_MODE_ROLLBACK_M BIT(2)
+   u32 fw_mode;
 
/* check the current FW mode */
-   reg = rd32(hw, GL_MNG_FWSM);
-   return (reg & GL_MNG_FWSM_FW_MODES_M) > ICE_FW_MODE_DBG;
+   fw_mode = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_MODES_M;
+
+   if (fw_mode & ICE_FW_MODE_DBG_M)
+   return ICE_FW_MODE_DBG;
+   else if (fw_mode & ICE_FW_MODE_REC_M)
+   return ICE_FW_MODE_REC;
+   else if (fw_mode & ICE_FW_MODE_ROLLBACK_M)
+   return ICE_FW_MODE_ROLLBACK;
+   else
+   return ICE_FW_MODE_NORMAL;
 }
diff --git a/drivers/net/ice/base/ice_common.h 
b/drivers/net/ice/base/ice_common.h
index 2063295ce..1d8701d64 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -14,7 +14,7 @@ enum ice_fw_modes {
ICE_FW_MODE_NORMAL,
ICE_FW_MODE_DBG,
ICE_FW_MODE_REC,
-   ICE_FW_MODE_DBG_REC
+   ICE_FW_MODE_ROLLBACK
 };
 
 enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw);
@@ -198,8 +198,8 @@ ice_stat_update40(struct ice_hw *hw, u32 reg, bool 
prev_stat_loaded,
 void
 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
  u64 *prev_stat, u64 *cur_stat);
+enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw);
 enum ice_status
 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
 struct ice_aqc_get_elem *buf);
-bool ice_is_fw_in_rec_mode(struct ice_hw *hw);
 #endif /* _ICE_COMMON_H_ */
-- 
2.13.6

[dpdk-dev] [PATCH 03/63] net/ice/base: add support for NVM rollback detection

[Qi Zhang]

This patch adds code to detect NVM rollback. The rollback detection
is done as part of the HW init flow. When NVM rollback is detected,
a warning message is printed along with the FW/NVM version data.
To do this, this patch adds a helper function ice_get_nvm_version.

Also, a pointer to hw->nvm is already available in ice_init_nvm. Just use
this instead of &hw->nvm.

Signed-off-by: Anirudh Venkataramanan 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_common.c | 46 +++
 drivers/net/ice/base/ice_common.h |  4 
 drivers/net/ice/base/ice_nvm.c|  6 ++---
 drivers/net/ice/base/ice_type.h   |  4 +++-
 4 files changed, 56 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ice/base/ice_common.c 
b/drivers/net/ice/base/ice_common.c
index 681740cee..4968808fa 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -814,6 +814,49 @@ static void ice_get_itr_intrl_gran(struct ice_hw *hw)
 }
 
 /**
+ * ice_get_nvm_version - get cached NVM version data
+ * @hw: pointer to the hardware structure
+ * @oem_ver: 8 bit NVM version
+ * @oem_build: 16 bit NVM build number
+ * @oem_patch: 8 NVM patch number
+ * @ver_hi: high 16 bits of the NVM version
+ * @ver_lo: low 16 bits of the NVM version
+ */
+void
+ice_get_nvm_version(struct ice_hw *hw, u8 *oem_ver, u16 *oem_build,
+   u8 *oem_patch, u8 *ver_hi, u8 *ver_lo)
+{
+   struct ice_nvm_info *nvm = &hw->nvm;
+
+   *oem_ver = (u8)((nvm->oem_ver & ICE_OEM_VER_MASK) >> ICE_OEM_VER_SHIFT);
+   *oem_patch = (u8)(nvm->oem_ver & ICE_OEM_VER_PATCH_MASK);
+   *oem_build = (u16)((nvm->oem_ver & ICE_OEM_VER_BUILD_MASK) >>
+  ICE_OEM_VER_BUILD_SHIFT);
+   *ver_hi = (nvm->ver & ICE_NVM_VER_HI_MASK) >> ICE_NVM_VER_HI_SHIFT;
+   *ver_lo = (nvm->ver & ICE_NVM_VER_LO_MASK) >> ICE_NVM_VER_LO_SHIFT;
+}
+
+/**
+ * ice_print_rollback_msg - print FW rollback message
+ * @hw: pointer to the hardware structure
+ */
+void ice_print_rollback_msg(struct ice_hw *hw)
+{
+   char nvm_str[ICE_NVM_VER_LEN] = { 0 };
+   u8 oem_ver, oem_patch, ver_hi, ver_lo;
+   u16 oem_build;
+
+   ice_get_nvm_version(hw, &oem_ver, &oem_build, &oem_patch, &ver_hi,
+   &ver_lo);
+   SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d", ver_hi,
+ver_lo, hw->nvm.eetrack, oem_ver, oem_build, oem_patch);
+
+   ice_warn(hw,
+"Firmware rollback mode detected. Current version is NVM: %s, 
FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) 
Ethernet Adapters and Devices User Guide for details on firmware rollback mode",
+nvm_str, hw->fw_maj_ver, hw->fw_min_ver);
+}
+
+/**
  * ice_init_hw - main hardware initialization routine
  * @hw: pointer to the hardware structure
  */
@@ -848,6 +891,9 @@ enum ice_status ice_init_hw(struct ice_hw *hw)
if (status)
goto err_unroll_cqinit;
 
+   if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK)
+   ice_print_rollback_msg(hw);
+
/* Enable FW logging. Not fatal if this fails. */
status = ice_cfg_fw_log(hw, true);
if (status)
diff --git a/drivers/net/ice/base/ice_common.h 
b/drivers/net/ice/base/ice_common.h
index 1d8701d64..009c052ca 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -198,7 +198,11 @@ ice_stat_update40(struct ice_hw *hw, u32 reg, bool 
prev_stat_loaded,
 void
 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
  u64 *prev_stat, u64 *cur_stat);
+void
+ice_get_nvm_version(struct ice_hw *hw, u8 *oem_ver, u16 *oem_build,
+   u8 *oem_patch, u8 *ver_hi, u8 *ver_lo);
 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw);
+void ice_print_rollback_msg(struct ice_hw *hw);
 enum ice_status
 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
 struct ice_aqc_get_elem *buf);
diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c
index f4567ca8f..c0f9e353e 100644
--- a/drivers/net/ice/base/ice_nvm.c
+++ b/drivers/net/ice/base/ice_nvm.c
@@ -292,7 +292,7 @@ enum ice_status ice_init_nvm(struct ice_hw *hw)
return status;
}
 
-   status = ice_read_sr_word(hw, ICE_SR_NVM_DEV_STARTER_VER, &hw->nvm.ver);
+   status = ice_read_sr_word(hw, ICE_SR_NVM_DEV_STARTER_VER, &nvm->ver);
if (status) {
ice_debug(hw, ICE_DBG_INIT,
  "Failed to read DEV starter version.\n");
@@ -310,7 +310,7 @@ enum ice_status ice_init_nvm(struct ice_hw *hw)
return status;
}
 
-   hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo;
+   nvm->eetrack = (eetrack_hi << 16) | eetrack_lo;
 
status = ice_read_sr_word(hw, ICE_SR_BOOT_CFG_PTR, &cfg_ptr);
if (status) {
@@ -331,7 +331,7 @@ enum ice_status ice_init_nvm(st

[dpdk-dev] [PATCH 01/63] net/ice/base: enhance NVM read

[Qi Zhang]

Add an option to read NVM from flash directly.

Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_adminq_cmd.h | 22 ++
 drivers/net/ice/base/ice_dcb.h|  1 +
 drivers/net/ice/base/ice_nvm.c| 12 +---
 3 files changed, 32 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ice/base/ice_adminq_cmd.h 
b/drivers/net/ice/base/ice_adminq_cmd.h
index 7afdb6578..b5faa5bf6 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -1684,6 +1684,28 @@ struct ice_aqc_nvm {
__le32 addr_low;
 };
 
+/* NVM Module_Type ID, needed offset and read_len for struct ice_aqc_nvm. */
+#define ICE_AQC_NVM_SECTOR_UNIT4096 /* In Bytes */
+#define ICE_AQC_NVM_WORD_UNIT  2 /* In Bytes */
+
+#define ICE_AQC_NVM_START_POINT0
+#define ICE_AQC_NVM_EMP_SR_PTR_OFFSET  0x90
+#define ICE_AQC_NVM_EMP_SR_PTR_RD_LEN  2 /* In Bytes */
+#define ICE_AQC_NVM_EMP_SR_PTR_M   MAKEMASK(0x7FFF, 0)
+#define ICE_AQC_NVM_EMP_SR_PTR_TYPE_S  15
+#define ICE_AQC_NVM_EMP_SR_PTR_TYPE_M  BIT(15)
+#define ICE_AQC_NVM_EMP_SR_PTR_TYPE_SECTOR 1
+
+#define ICE_AQC_NVM_LLDP_CFG_PTR_OFFSET0x46
+#define ICE_AQC_NVM_LLDP_CFG_HEADER_LEN2 /* In Bytes */
+#define ICE_AQC_NVM_LLDP_CFG_PTR_RD_LEN2 /* In Bytes */
+
+#define ICE_AQC_NVM_LLDP_PRESERVED_MOD_ID  0x129
+#define ICE_AQC_NVM_CUR_LLDP_PERSIST_RD_OFFSET 2 /* In Bytes */
+#define ICE_AQC_NVM_LLDP_STATUS_M  MAKEMASK(0xF, 0)
+#define ICE_AQC_NVM_LLDP_STATUS_M_LEN  4 /* In Bits */
+#define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */
+
 
 /* Used for 0x0704 as well as for 0x0705 commands */
 struct ice_aqc_nvm_cfg {
diff --git a/drivers/net/ice/base/ice_dcb.h b/drivers/net/ice/base/ice_dcb.h
index 47127096b..9a0968f5b 100644
--- a/drivers/net/ice/base/ice_dcb.h
+++ b/drivers/net/ice/base/ice_dcb.h
@@ -6,6 +6,7 @@
 #define _ICE_DCB_H_
 
 #include "ice_type.h"
+#include "ice_common.h"
 
 #define ICE_DCBX_OFFLOAD_DIS   0
 #define ICE_DCBX_OFFLOAD_ENABLED   1
diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c
index 6178cd4ac..f4567ca8f 100644
--- a/drivers/net/ice/base/ice_nvm.c
+++ b/drivers/net/ice/base/ice_nvm.c
@@ -13,13 +13,15 @@
  * @length: length of the section to be read (in bytes from the offset)
  * @data: command buffer (size [bytes] = length)
  * @last_command: tells if this is the last command in a series
+ * @read_shadow_ram: tell if this is a shadow RAM read
  * @cd: pointer to command details structure or NULL
  *
  * Read the NVM using the admin queue commands (0x0701)
  */
 static enum ice_status
 ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length,
-   void *data, bool last_command, struct ice_sq_cd *cd)
+   void *data, bool last_command, bool read_shadow_ram,
+   struct ice_sq_cd *cd)
 {
struct ice_aq_desc desc;
struct ice_aqc_nvm *cmd;
@@ -34,6 +36,9 @@ ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 
offset, u16 length,
 
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_read);
 
+   if (!read_shadow_ram && module_typeid == ICE_AQC_NVM_START_POINT)
+   cmd->cmd_flags |= ICE_AQC_NVM_FLASH_ONLY;
+
/* If this is the last command in a series, set the proper flag. */
if (last_command)
cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;
@@ -104,8 +109,9 @@ ice_read_sr_aq(struct ice_hw *hw, u32 offset, u16 words, 
u16 *data,
 * So do this conversion while calling ice_aq_read_nvm.
 */
if (!status)
-   status = ice_aq_read_nvm(hw, 0, 2 * offset, 2 * words, data,
-last_command, NULL);
+   status = ice_aq_read_nvm(hw, ICE_AQC_NVM_START_POINT,
+2 * offset, 2 * words, data,
+last_command, true, NULL);
 
return status;
 }
-- 
2.13.6

[dpdk-dev] [PATCH 05/63] net/ice/base: store number of functions for the device

[Qi Zhang]

Store the number of functions the device has.  This value can be
very useful when calculating how to best allocate global resources.

Signed-off-by: Kevin Scott 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_common.c | 6 +-
 drivers/net/ice/base/ice_type.h   | 1 +
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ice/base/ice_common.c 
b/drivers/net/ice/base/ice_common.c
index 58dd01ea1..fa97b792e 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -2114,6 +2114,10 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 
cap_count,
ice_debug(hw, ICE_DBG_INIT,
  "%s: valid functions = %d\n", prefix,
  caps->valid_functions);
+
+   /* store func count for resource management purposes */
+   if (dev_p)
+   dev_p->num_funcs = ice_hweight32(number);
break;
case ICE_AQC_CAPS_VSI:
if (dev_p) {
@@ -2230,7 +2234,7 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 
cap_count,
 * physical ports; i.e. some features are not supported or function
 * differently on devices with more than 4 ports.
 */
-   if (caps && (ice_hweight32(caps->valid_functions) > 4)) {
+   if (hw->dev_caps.num_funcs > 4) {
/* Max 4 TCs per port */
caps->maxtc = 4;
ice_debug(hw, ICE_DBG_INIT,
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 2d010e643..88846e042 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -359,6 +359,7 @@ struct ice_hw_dev_caps {
struct ice_hw_common_caps common_cap;
u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
u32 num_flow_director_fltr; /* Number of FD filters available */
+   u32 num_funcs;
 };
 
 
-- 
2.13.6

[dpdk-dev] [PATCH 04/63] net/ice/base: add support to init RXDID descs fields

[Qi Zhang]

Add new switch cases to init RXDID descs MD fields.

Signed-off-by: Junfeng Guo 
Signed-off-by: Haiyue Wang 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_common.c| 91 
 drivers/net/ice/base/ice_lan_tx_rx.h |  6 +++
 2 files changed, 97 insertions(+)

diff --git a/drivers/net/ice/base/ice_common.c 
b/drivers/net/ice/base/ice_common.c
index 4968808fa..58dd01ea1 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -19,6 +19,16 @@
 (((mdid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \
  GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M))
 
+#define ICE_PROG_FLEX_ENTRY_EXTRACT(hw, rxdid, protid, off, idx) \
+   wr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(rxdid), \
+((ICE_RX_OPC_EXTRACT << \
+  GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \
+ GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \
+(((protid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \
+ GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M) | \
+(((off) << GLFLXP_RXDID_FLX_WRD_##idx##_EXTRACTION_OFFSET_S) & \
+ GLFLXP_RXDID_FLX_WRD_##idx##_EXTRACTION_OFFSET_M))
+
 #define ICE_PROG_FLG_ENTRY(hw, rxdid, flg_0, flg_1, flg_2, flg_3, idx) \
wr32((hw), GLFLXP_RXDID_FLAGS(rxdid, idx), \
 (((flg_0) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) & \
@@ -412,6 +422,8 @@ static void ice_init_flex_flags(struct ice_hw *hw, enum 
ice_rxdid prof_id)
  */
 static void ice_init_flex_flds(struct ice_hw *hw, enum ice_rxdid prof_id)
 {
+   enum ice_prot_id protid_0, protid_1;
+   u16 offset_0, offset_1;
enum ice_flex_mdid mdid;
 
switch (prof_id) {
@@ -428,7 +440,80 @@ static void ice_init_flex_flds(struct ice_hw *hw, enum 
ice_rxdid prof_id)
 
ice_init_flex_flags(hw, prof_id);
break;
+   case ICE_RXDID_COMMS_GENERIC:
+   case ICE_RXDID_COMMS_AUX_VLAN:
+   case ICE_RXDID_COMMS_AUX_IPV4:
+   case ICE_RXDID_COMMS_AUX_IPV6:
+   case ICE_RXDID_COMMS_AUX_IPV6_FLOW:
+   case ICE_RXDID_COMMS_AUX_TCP:
+   ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_LOW, 0);
+   ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_HIGH, 1);
+   ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_FLOW_ID_LOWER, 2);
+   ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_FLOW_ID_HIGH, 3);
+
+   if (prof_id == ICE_RXDID_COMMS_AUX_VLAN) {
+   /* FlexiMD.4: VLAN1 - single or EVLAN (first for QinQ).
+* FlexiMD.5: VLAN2 - C-VLAN (second for QinQ).
+*/
+   protid_0 = ICE_PROT_EVLAN_O;
+   offset_0 = 0;
+   protid_1 = ICE_PROT_VLAN_O;
+   offset_1 = 0;
+   } else if (prof_id == ICE_RXDID_COMMS_AUX_IPV4) {
+   /* FlexiMD.4: IPHDR1 - IPv4 header word 4, "TTL" and
+* "Protocol" fields.
+* FlexiMD.5: IPHDR0 - IPv4 header word 0, "Ver",
+* "Hdr Len" and "Type of Service" fields.
+*/
+   protid_0 = ICE_PROT_IPV4_OF_OR_S;
+   offset_0 = 8;
+   protid_1 = ICE_PROT_IPV4_OF_OR_S;
+   offset_1 = 0;
+   } else if (prof_id == ICE_RXDID_COMMS_AUX_IPV6) {
+   /* FlexiMD.4: IPHDR1 - IPv6 header word 3,
+* "Next Header" and "Hop Limit" fields.
+* FlexiMD.5: IPHDR0 - IPv6 header word 0,
+* "Ver", "Traffic class" and high 4 bits of
+* "Flow Label" fields.
+*/
+   protid_0 = ICE_PROT_IPV6_OF_OR_S;
+   offset_0 = 6;
+   protid_1 = ICE_PROT_IPV6_OF_OR_S;
+   offset_1 = 0;
+   } else if (prof_id == ICE_RXDID_COMMS_AUX_IPV6_FLOW) {
+   /* FlexiMD.4: IPHDR1 - IPv6 header word 1,
+* 16 low bits of the "Flow Label" field.
+* FlexiMD.5: IPHDR0 - IPv6 header word 0,
+* "Ver", "Traffic class" and high 4 bits
+* of "Flow Label" fields.
+*/
+   protid_0 = ICE_PROT_IPV6_OF_OR_S;
+   offset_0 = 2;
+   protid_1 = ICE_PROT_IPV6_OF_OR_S;
+   offset_1 = 0;
+   } else if (prof_id == ICE_RXDID_COMMS_AUX_TCP) {
+   /* FlexiMD.4: TCPHDR - TCP header word 6,
+* "Data Offset" and "Flags" fields.
+* FlexiMD.5: Reserved
+*/
+   protid_0 = ICE_PROT_TCP_IL;
+   

[dpdk-dev] [PATCH 00/63] net/ice/base: update base code

[Qi Zhang]

Key Features:

1) Add PPPoE, GTP protocol support for switch, FDIR, RSS
2) Add Flexible Descriptor support.
3) Improved package download.
4) Improved RSS to support inner header
5) Improved recipe management for switch rule
 
Qi Zhang (63):
  net/ice/base: enhance NVM read
  net/ice/base: add function to get FW mode
  net/ice/base: add support for NVM rollback detection
  net/ice/base: add support to init RXDID descs fields
  net/ice/base: store number of functions for the device
  net/ice/base: add read PBA module function
  net/ice/base: correct argument port info
  net/ice/base: remove debug code
  net/ice/base: add SFF EEPROM AQ Command
  net/ice/base: improve debug print message
  net/ice/base: add capabilities when in safe mode
  net/ice/base: add helper functions for PHY caching
  net/ice/base: add support for reading REPC statistics
  net/ice/base: adjust DCB INIT for SW mode
  net/ice/base: add NVM pkg flag
  net/ice/base: move VSI to VSI group
  net/ice/base: enable masking for RSS and FD field vectors
  net/ice/base: resolve static analysis issues
  net/ice/base: fix memory leak issue
  net/ice/base: check root pointer for validity
  net/ice/base: fix type-mismatch
  net/ice/base: correct overrun Coverty hit
  net/ice/base: update Boot Configuration Section read of NVM
  net/ice/base: add support for NVM access commands
  net/ice/base: add support for GTP and PPPoE protocols
  net/ice/base: add locks for flow functions
  net/ice/base: improve switch advanced rule
  net/ice/base: move function declaration
  net/ice/base: add 16-byte Flex Rx Descriptor
  net/ice/base: add 32-byte Flex Rx Desc for Comms package
  net/ice/base: update flag bits to current specification
  net/ice/base: add more opcode and macros
  net/ice/base: set status when global cfg lock is unavailable
  net/ice/base: initialize driver NVM data earlier
  net/ice/base: add function to configure Tx AQ command
  net/ice/base: add support for not locking sideband queue
  net/ice/base: associate recipes by profile type
  net/ice/base: return switch error on invalid match criteria
  net/ice/base: update UDP tunnel switch training packets
  net/ice/base: improve switch chained recipe
  net/ice/base: move and add some help function and macros
  net/ice/base: add routine for tunnel port query
  net/ice/base: ptype group consolidation
  net/ice/base: fix for RSS hash on inner UDP port
  net/ice/base: packet encapsulation for RSS
  net/ice/base: add RSS support for PPPoE and GTPU
  net/ice/base: remove unnecessary conditional check
  net/ice/base: fix flag settings in AQ call
  net/ice/base: refactor removal of VLAN promiscuous rules
  net/ice/base: maximize switch recipe words per line
  net/ice/base: update switch training packets with open ports
  net/ice/base: remove unnecessary dummy packet finding
  net/ice/base: remove unnecessary if branch
  net/ice/base: correct abbreviations
  net/ice/base: update to register definition file
  net/ice/base: replace open-code duplication
  net/ice/base: delay less
  net/ice/base: add AQC get link topology handle support
  net/ice/base: remove Rx flex descriptor programming
  net/ice/base: enable RSS with ether layer for PPPoE
  net/ice/base: add GENEVE offset
  net/ice/base: update profile to recipe bitmap array
  net/ice/base: ignore inverse switch recipes

 drivers/net/ice/base/ice_adminq_cmd.h| 221 
 drivers/net/ice/base/ice_bitops.h|  31 ++
 drivers/net/ice/base/ice_common.c| 902 ++
 drivers/net/ice/base/ice_common.h|  48 +-
 drivers/net/ice/base/ice_controlq.c  |  54 +-
 drivers/net/ice/base/ice_controlq.h  |   7 +-
 drivers/net/ice/base/ice_dcb.c   |   6 +-
 drivers/net/ice/base/ice_dcb.h   |   1 +
 drivers/net/ice/base/ice_devids.h|   6 +
 drivers/net/ice/base/ice_flex_pipe.c | 923 ++-
 drivers/net/ice/base/ice_flex_pipe.h |  17 +-
 drivers/net/ice/base/ice_flex_type.h |  35 +-
 drivers/net/ice/base/ice_flow.c  | 368 
 drivers/net/ice/base/ice_flow.h  | 107 +++-
 drivers/net/ice/base/ice_hw_autogen.h|  34 ++
 drivers/net/ice/base/ice_lan_tx_rx.h |  76 ++-
 drivers/net/ice/base/ice_nvm.c   | 294 +-
 drivers/net/ice/base/ice_nvm.h   |  91 +++
 drivers/net/ice/base/ice_osdep.h |   2 +-
 drivers/net/ice/base/ice_protocol_type.h |  40 +-
 drivers/net/ice/base/ice_sched.c |  87 +--
 drivers/net/ice/base/ice_sched.h |   8 +-
 drivers/net/ice/base/ice_switch.c| 784 ++
 drivers/net/ice/base/ice_switch.h|   5 +
 drivers/net/ice/base/ice_type.h  |  77 ++-
 25 files changed, 3142 insertions(+), 1082 deletions(-)
 create mode 100644 drivers/net/ice/base/ice_nvm.h

-- 
2.13.6

[dpdk-dev] [PATCH 06/63] net/ice/base: add read PBA module function

[Qi Zhang]

New support function added - ice_get_pfa_module_tlv(), the driver or
other modules can make use of this function to read the pfa area.

Signed-off-by: Tarun Singh 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_common.c | 66 +++
 drivers/net/ice/base/ice_common.h |  3 ++
 2 files changed, 69 insertions(+)

diff --git a/drivers/net/ice/base/ice_common.c 
b/drivers/net/ice/base/ice_common.c
index fa97b792e..0356537a4 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -1283,6 +1283,72 @@ enum ice_status ice_reset(struct ice_hw *hw, enum 
ice_reset_req req)
return ice_check_reset(hw);
 }
 
+/**
+ * ice_get_pfa_module_tlv - Reads sub module TLV from NVM PFA
+ * @hw: pointer to hardware structure
+ * @module_tlv: pointer to module TLV to return
+ * @module_tlv_len: pointer to module TLV length to return
+ * @module_type: module type requested
+ *
+ * Finds the requested sub module TLV type from the Preserved Field
+ * Area (PFA) and returns the TLV pointer and length. The caller can
+ * use these to read the variable length TLV value.
+ */
+enum ice_status
+ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
+  u16 module_type)
+{
+   enum ice_status status;
+   u16 pfa_len, pfa_ptr;
+   u16 next_tlv;
+
+   status = ice_read_sr_word(hw, ICE_SR_PFA_PTR, &pfa_ptr);
+   if (status != ICE_SUCCESS) {
+   ice_debug(hw, ICE_DBG_INIT, "Preserved Field Array pointer.\n");
+   return status;
+   }
+   status = ice_read_sr_word(hw, pfa_ptr, &pfa_len);
+   if (status != ICE_SUCCESS) {
+   ice_debug(hw, ICE_DBG_INIT, "Failed to read PFA length.\n");
+   return status;
+   }
+   /* Starting with first TLV after PFA length, iterate through the list
+* of TLVs to find the requested one.
+*/
+   next_tlv = pfa_ptr + 1;
+   while (next_tlv < pfa_ptr + pfa_len) {
+   u16 tlv_sub_module_type;
+   u16 tlv_len;
+
+   /* Read TLV type */
+   status = ice_read_sr_word(hw, next_tlv, &tlv_sub_module_type);
+   if (status != ICE_SUCCESS) {
+   ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV 
type.\n");
+   break;
+   }
+   /* Read TLV length */
+   status = ice_read_sr_word(hw, next_tlv + 1, &tlv_len);
+   if (status != ICE_SUCCESS) {
+   ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV 
length.\n");
+   break;
+   }
+   if (tlv_sub_module_type == module_type) {
+   if (tlv_len) {
+   *module_tlv = next_tlv;
+   *module_tlv_len = tlv_len;
+   return ICE_SUCCESS;
+   }
+   return ICE_ERR_INVAL_SIZE;
+   }
+   /* Check next TLV, i.e. current TLV pointer + length + 2 words
+* (for current TLV's type and length)
+*/
+   next_tlv = next_tlv + tlv_len + 2;
+   }
+   /* Module does not exist */
+   return ICE_ERR_DOES_NOT_EXIST;
+}
+
 
 
 /**
diff --git a/drivers/net/ice/base/ice_common.h 
b/drivers/net/ice/base/ice_common.h
index 009c052ca..c5170f705 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -21,6 +21,9 @@ enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw);
 
 enum ice_status ice_init_hw(struct ice_hw *hw);
 void ice_deinit_hw(struct ice_hw *hw);
+enum ice_status
+ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
+  u16 module_type);
 enum ice_status ice_check_reset(struct ice_hw *hw);
 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req);
 
-- 
2.13.6

[dpdk-dev] [PATCH 08/63] net/ice/base: remove debug code

[Qi Zhang]

Remove firmware logging debug code.

Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_adminq_cmd.h |  88 --
 drivers/net/ice/base/ice_common.c | 223 --
 drivers/net/ice/base/ice_common.h |   1 -
 drivers/net/ice/base/ice_type.h   |  20 ---
 4 files changed, 332 deletions(-)

diff --git a/drivers/net/ice/base/ice_adminq_cmd.h 
b/drivers/net/ice/base/ice_adminq_cmd.h
index b5faa5bf6..9e5853cca 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -2176,87 +2176,6 @@ struct ice_aqc_event_lan_overflow {
 
 
 
-/* Configure Firmware Logging Command (indirect 0xFF09)
- * Logging Information Read Response (indirect 0xFF10)
- * Note: The 0xFF10 command has no input parameters.
- */
-struct ice_aqc_fw_logging {
-   u8 log_ctrl;
-#define ICE_AQC_FW_LOG_AQ_EN   BIT(0)
-#define ICE_AQC_FW_LOG_UART_EN BIT(1)
-   u8 rsvd0;
-   u8 log_ctrl_valid; /* Not used by 0xFF10 Response */
-#define ICE_AQC_FW_LOG_AQ_VALIDBIT(0)
-#define ICE_AQC_FW_LOG_UART_VALID  BIT(1)
-   u8 rsvd1[5];
-   __le32 addr_high;
-   __le32 addr_low;
-};
-
-
-enum ice_aqc_fw_logging_mod {
-   ICE_AQC_FW_LOG_ID_GENERAL = 0,
-   ICE_AQC_FW_LOG_ID_CTRL,
-   ICE_AQC_FW_LOG_ID_LINK,
-   ICE_AQC_FW_LOG_ID_LINK_TOPO,
-   ICE_AQC_FW_LOG_ID_DNL,
-   ICE_AQC_FW_LOG_ID_I2C,
-   ICE_AQC_FW_LOG_ID_SDP,
-   ICE_AQC_FW_LOG_ID_MDIO,
-   ICE_AQC_FW_LOG_ID_ADMINQ,
-   ICE_AQC_FW_LOG_ID_HDMA,
-   ICE_AQC_FW_LOG_ID_LLDP,
-   ICE_AQC_FW_LOG_ID_DCBX,
-   ICE_AQC_FW_LOG_ID_DCB,
-   ICE_AQC_FW_LOG_ID_NETPROXY,
-   ICE_AQC_FW_LOG_ID_NVM,
-   ICE_AQC_FW_LOG_ID_AUTH,
-   ICE_AQC_FW_LOG_ID_VPD,
-   ICE_AQC_FW_LOG_ID_IOSF,
-   ICE_AQC_FW_LOG_ID_PARSER,
-   ICE_AQC_FW_LOG_ID_SW,
-   ICE_AQC_FW_LOG_ID_SCHEDULER,
-   ICE_AQC_FW_LOG_ID_TXQ,
-   ICE_AQC_FW_LOG_ID_RSVD,
-   ICE_AQC_FW_LOG_ID_POST,
-   ICE_AQC_FW_LOG_ID_WATCHDOG,
-   ICE_AQC_FW_LOG_ID_TASK_DISPATCH,
-   ICE_AQC_FW_LOG_ID_MNG,
-   ICE_AQC_FW_LOG_ID_SYNCE,
-   ICE_AQC_FW_LOG_ID_MAX,
-};
-
-/* This is the buffer for both of the logging commands.
- * The entry array size depends on the datalen parameter in the descriptor.
- * There will be a total of datalen / 2 entries.
- */
-struct ice_aqc_fw_logging_data {
-   __le16 entry[1];
-#define ICE_AQC_FW_LOG_ID_S0
-#define ICE_AQC_FW_LOG_ID_M(0xFFF << ICE_AQC_FW_LOG_ID_S)
-
-#define ICE_AQC_FW_LOG_CONF_SUCCESS0   /* Used by response */
-#define ICE_AQC_FW_LOG_CONF_BAD_INDX   BIT(12) /* Used by response */
-
-#define ICE_AQC_FW_LOG_EN_S12
-#define ICE_AQC_FW_LOG_EN_M(0xF << ICE_AQC_FW_LOG_EN_S)
-#define ICE_AQC_FW_LOG_INFO_EN BIT(12) /* Used by command */
-#define ICE_AQC_FW_LOG_INIT_EN BIT(13) /* Used by command */
-#define ICE_AQC_FW_LOG_FLOW_EN BIT(14) /* Used by command */
-#define ICE_AQC_FW_LOG_ERR_EN  BIT(15) /* Used by command */
-};
-
-
-/* Get/Clear FW Log (indirect 0xFF11) */
-struct ice_aqc_get_clear_fw_log {
-   u8 flags;
-#define ICE_AQC_FW_LOG_CLEAR   BIT(0)
-#define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1)
-   u8 rsvd1[7];
-   __le32 addr_high;
-   __le32 addr_low;
-};
-
 
 /**
  * struct ice_aq_desc - Admin Queue (AQ) descriptor
@@ -2337,8 +2256,6 @@ struct ice_aq_desc {
struct ice_aqc_get_vsi_resp get_vsi_resp;
struct ice_aqc_download_pkg download_pkg;
struct ice_aqc_get_pkg_info_list get_pkg_info_list;
-   struct ice_aqc_fw_logging fw_logging;
-   struct ice_aqc_get_clear_fw_log get_clear_fw_log;
struct ice_aqc_set_mac_lb set_mac_lb;
struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
struct ice_aqc_get_res_alloc get_res;
@@ -2558,11 +2475,6 @@ enum ice_adminq_opc {
 
/* Standalone Commands/Events */
ice_aqc_opc_event_lan_overflow  = 0x1001,
-
-   /* debug commands */
-   ice_aqc_opc_fw_logging  = 0xFF09,
-   ice_aqc_opc_fw_logging_info = 0xFF10,
-   ice_aqc_opc_get_clear_fw_log= 0xFF11
 };
 
 #endif /* _ICE_ADMINQ_CMD_H_ */
diff --git a/drivers/net/ice/base/ice_common.c 
b/drivers/net/ice/base/ice_common.c
index b4f0b964d..43c06948f 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -653,223 +653,6 @@ static void ice_cleanup_fltr_mgmt_struct(struct ice_hw 
*hw)
ice_free(hw, sw);
 }
 
-#define ICE_FW_LOG_DESC_SIZE(n)(sizeof(struct ice_aqc_fw_logging_data) 
+ \
-   (((n) - 1) * sizeof(((struct ice_aqc_fw_logging_data *)0)->entry)))
-#define ICE_FW_LOG_DESC_SIZE_MAX   \
-   ICE_FW_LOG_DESC_SIZE(ICE_AQC_FW_LOG_ID_MAX)
-
-/**
- * ice_get_fw_log_cfg - get 

[dpdk-dev] [PATCH 07/63] net/ice/base: correct argument port info

[Qi Zhang]

correct argument pi(port_info) passed in function
ice_sched_get_first_node(), otherwise it will return the incorrect
node.

functions ice_sched_get_agg_node and ice_sched_cfg_sibl_node_prio:
change argument from hw to pi for it to align to correct port.

Moved saving tc node bw info from hardware structure(hw) to port info
structure(pi). This change allows multiple ports to save and replay
the information correctly.

Signed-off-by: Tarun Singh 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_common.c |  2 +-
 drivers/net/ice/base/ice_common.h |  2 +-
 drivers/net/ice/base/ice_sched.c  | 70 ---
 drivers/net/ice/base/ice_sched.h  |  4 +--
 drivers/net/ice/base/ice_type.h   |  2 +-
 5 files changed, 41 insertions(+), 39 deletions(-)

diff --git a/drivers/net/ice/base/ice_common.c 
b/drivers/net/ice/base/ice_common.c
index 0356537a4..b4f0b964d 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -4158,7 +4158,7 @@ static enum ice_status ice_replay_pre_init(struct ice_hw 
*hw)
  &sw->recp_list[i].filt_replay_rules);
ice_sched_replay_agg_vsi_preinit(hw);
 
-   return ice_sched_replay_tc_node_bw(hw);
+   return ice_sched_replay_tc_node_bw(hw->port_info);
 }
 
 /**
diff --git a/drivers/net/ice/base/ice_common.h 
b/drivers/net/ice/base/ice_common.h
index c5170f705..4ecfa6b9b 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -184,7 +184,7 @@ enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 
vsi_handle);
 void ice_replay_post(struct ice_hw *hw);
 void ice_sched_replay_agg_vsi_preinit(struct ice_hw *hw);
 void ice_sched_replay_agg(struct ice_hw *hw);
-enum ice_status ice_sched_replay_tc_node_bw(struct ice_hw *hw);
+enum ice_status ice_sched_replay_tc_node_bw(struct ice_port_info *pi);
 enum ice_status ice_replay_vsi_agg(struct ice_hw *hw, u16 vsi_handle);
 enum ice_status
 ice_sched_replay_q_bw(struct ice_port_info *pi, struct ice_q_ctx *q_ctx);
diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c
index 2d80af731..d16f256c9 100644
--- a/drivers/net/ice/base/ice_sched.c
+++ b/drivers/net/ice/base/ice_sched.c
@@ -1480,7 +1480,7 @@ ice_sched_get_vsi_node(struct ice_port_info *pi, struct 
ice_sched_node *tc_node,
 
 /**
  * ice_sched_get_agg_node - Get an aggregator node based on aggregator ID
- * @hw: pointer to the HW struct
+ * @pi: pointer to the port information structure
  * @tc_node: pointer to the TC node
  * @agg_id: aggregator ID
  *
@@ -1488,14 +1488,17 @@ ice_sched_get_vsi_node(struct ice_port_info *pi, struct 
ice_sched_node *tc_node,
  * a given TC branch
  */
 static struct ice_sched_node *
-ice_sched_get_agg_node(struct ice_hw *hw, struct ice_sched_node *tc_node,
+ice_sched_get_agg_node(struct ice_port_info *pi, struct ice_sched_node 
*tc_node,
   u32 agg_id)
 {
struct ice_sched_node *node;
+   struct ice_hw *hw = pi->hw;
u8 agg_layer;
 
+   if (!hw)
+   return NULL;
agg_layer = ice_sched_get_agg_layer(hw);
-   node = ice_sched_get_first_node(hw->port_info, tc_node, agg_layer);
+   node = ice_sched_get_first_node(pi, tc_node, agg_layer);
 
/* Check whether it already exists */
while (node) {
@@ -2251,7 +2254,7 @@ ice_sched_move_vsi_to_agg(struct ice_port_info *pi, u16 
vsi_handle, u32 agg_id,
if (!tc_node)
return ICE_ERR_CFG;
 
-   agg_node = ice_sched_get_agg_node(pi->hw, tc_node, agg_id);
+   agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id);
if (!agg_node)
return ICE_ERR_DOES_NOT_EXIST;
 
@@ -2388,7 +2391,7 @@ ice_sched_rm_agg_cfg(struct ice_port_info *pi, u32 
agg_id, u8 tc)
if (!tc_node)
return ICE_ERR_CFG;
 
-   agg_node = ice_sched_get_agg_node(hw, tc_node, agg_id);
+   agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id);
if (!agg_node)
return ICE_ERR_DOES_NOT_EXIST;
 
@@ -2497,7 +2500,7 @@ ice_sched_add_agg_cfg(struct ice_port_info *pi, u32 
agg_id, u8 tc)
if (!tc_node)
return ICE_ERR_CFG;
 
-   agg_node = ice_sched_get_agg_node(hw, tc_node, agg_id);
+   agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id);
/* Does Agg node already exist ? */
if (agg_node)
return status;
@@ -3445,7 +3448,6 @@ ice_cfg_vsi_q_priority(struct ice_port_info *pi, u16 
num_qs, u32 *q_ids,
   u8 *q_prio)
 {
enum ice_status status = ICE_ERR_PARAM;
-   struct ice_hw *hw = pi->hw;
u16 i;
 
ice_acquire_lock(&pi->sched_lock);
@@ -3460,7 +3462,7 @@ ice_cfg_vsi_q_priority(struct ice_port_info *pi, u16 
num_qs, u32 *q_ids,
break;
}
/* Configure Priority */
-   status = ice_sched_cfg_sibl_node_prio(hw, node, q_prio[i

[dpdk-dev] [PATCH 09/63] net/ice/base: add SFF EEPROM AQ Command

[Qi Zhang]

read/write module eeprom on i2c bus.

Signed-off-by: Scott W Taylor 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_adminq_cmd.h | 29 ++
 drivers/net/ice/base/ice_common.c | 46 +++
 drivers/net/ice/base/ice_common.h |  5 +++-
 3 files changed, 79 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ice/base/ice_adminq_cmd.h 
b/drivers/net/ice/base/ice_adminq_cmd.h
index 9e5853cca..4de69dd7a 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -1660,6 +1660,33 @@ struct ice_aqc_set_port_id_led {
 
 
 
+/* Read/Write SFF EEPROM command (indirect 0x06EE) */
+struct ice_aqc_sff_eeprom {
+   u8 lport_num;
+   u8 lport_num_valid;
+#define ICE_AQC_SFF_PORT_NUM_VALID BIT(0)
+   __le16 i2c_bus_addr;
+#define ICE_AQC_SFF_I2CBUS_7BIT_M  0x7F
+#define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF
+#define ICE_AQC_SFF_I2CBUS_TYPE_M  BIT(10)
+#define ICE_AQC_SFF_I2CBUS_TYPE_7BIT   0
+#define ICE_AQC_SFF_I2CBUS_TYPE_10BIT  ICE_AQC_SFF_I2CBUS_TYPE_M
+#define ICE_AQC_SFF_SET_EEPROM_PAGE_S  11
+#define ICE_AQC_SFF_SET_EEPROM_PAGE_M  (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S)
+#define ICE_AQC_SFF_NO_PAGE_CHANGE 0
+#define ICE_AQC_SFF_SET_23_ON_MISMATCH 1
+#define ICE_AQC_SFF_SET_22_ON_MISMATCH 2
+#define ICE_AQC_SFF_IS_WRITE   BIT(15)
+   __le16 i2c_mem_addr;
+   __le16 eeprom_page;
+#define  ICE_AQC_SFF_EEPROM_BANK_S 0
+#define  ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S)
+#define  ICE_AQC_SFF_EEPROM_PAGE_S 8
+#define  ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S)
+   __le32 addr_high;
+   __le32 addr_low;
+};
+
 /* NVM Read command (indirect 0x0701)
  * NVM Erase commands (direct 0x0702)
  * NVM Update commands (indirect 0x0703)
@@ -2218,6 +2245,7 @@ struct ice_aq_desc {
struct ice_aqc_get_phy_caps get_phy;
struct ice_aqc_set_phy_cfg set_phy;
struct ice_aqc_restart_an restart_an;
+   struct ice_aqc_sff_eeprom read_write_sff_param;
struct ice_aqc_set_port_id_led set_port_id_led;
struct ice_aqc_get_sw_cfg get_sw_conf;
struct ice_aqc_sw_rules sw_rules;
@@ -2431,6 +2459,7 @@ enum ice_adminq_opc {
ice_aqc_opc_set_port_option = 0x06EB,
ice_aqc_opc_set_gpio= 0x06EC,
ice_aqc_opc_get_gpio= 0x06ED,
+   ice_aqc_opc_sff_eeprom  = 0x06EE,
 
/* NVM commands */
ice_aqc_opc_nvm_read= 0x0701,
diff --git a/drivers/net/ice/base/ice_common.c 
b/drivers/net/ice/base/ice_common.c
index 43c06948f..cd94995f4 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -2860,6 +2860,52 @@ ice_aq_set_port_id_led(struct ice_port_info *pi, bool 
is_orig_mode,
 }
 
 /**
+ * ice_aq_sff_eeprom
+ * @hw: pointer to the HW struct
+ * @lport: bits [7:0] = logical port, bit [8] = logical port valid
+ * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default)
+ * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding.
+ * @page: QSFP page
+ * @set_page: set or ignore the page
+ * @data: pointer to data buffer to be read/written to the I2C device.
+ * @length: 1-16 for read, 1 for write.
+ * @write: 0 read, 1 for write.
+ * @cd: pointer to command details structure or NULL
+ *
+ * Read/Write SFF EEPROM (0x06EE)
+ */
+enum ice_status
+ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
+ u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
+ bool write, struct ice_sq_cd *cd)
+{
+   struct ice_aqc_sff_eeprom *cmd;
+   struct ice_aq_desc desc;
+   enum ice_status status;
+
+   if (!data || (mem_addr & 0xff00))
+   return ICE_ERR_PARAM;
+
+   ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom);
+   cmd = &desc.params.read_write_sff_param;
+   desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD | ICE_AQ_FLAG_BUF);
+   cmd->lport_num = (u8)(lport & 0xff);
+   cmd->lport_num_valid = (u8)((lport >> 8) & 0x01);
+   cmd->i2c_bus_addr = CPU_TO_LE16(((bus_addr >> 1) &
+ICE_AQC_SFF_I2CBUS_7BIT_M) |
+   ((set_page <<
+ ICE_AQC_SFF_SET_EEPROM_PAGE_S) &
+ICE_AQC_SFF_SET_EEPROM_PAGE_M));
+   cmd->i2c_mem_addr = CPU_TO_LE16(mem_addr & 0xff);
+   cmd->eeprom_page = CPU_TO_LE16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S);
+   if (write)
+   cmd->i2c_bus_addr |= CPU_TO_LE16(ICE_AQC_SFF_IS_WRITE);
+
+   status = ice_aq_send_cmd(hw, &desc, data, length, cd);
+   return status;
+}
+
+/**
  * __ice_aq_get_set_rss_lut
  * @hw: pointer to the hardware str

[dpdk-dev] [PATCH 10/63] net/ice/base: improve debug print message

[Qi Zhang]

Improve debug print message.

Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_common.c   | 41 +++--
 drivers/net/ice/base/ice_controlq.c | 10 +
 2 files changed, 27 insertions(+), 24 deletions(-)

diff --git a/drivers/net/ice/base/ice_common.c 
b/drivers/net/ice/base/ice_common.c
index cd94995f4..ae7837149 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -1955,7 +1955,7 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 
cap_count,
case ICE_AQC_CAPS_VALID_FUNCTIONS:
caps->valid_functions = number;
ice_debug(hw, ICE_DBG_INIT,
- "%s: valid functions = %d\n", prefix,
+ "%s: valid_functions (bitmap) = %d\n", prefix,
  caps->valid_functions);
 
/* store func count for resource management purposes */
@@ -1966,17 +1966,17 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 
cap_count,
if (dev_p) {
dev_p->num_vsi_allocd_to_host = number;
ice_debug(hw, ICE_DBG_INIT,
- "%s: num VSI alloc to host = %d\n",
+ "%s: num_vsi_allocd_to_host = %d\n",
  prefix,
  dev_p->num_vsi_allocd_to_host);
} else if (func_p) {
func_p->guar_num_vsi =
ice_get_num_per_func(hw, ICE_MAX_VSI);
ice_debug(hw, ICE_DBG_INIT,
- "%s: num guaranteed VSI (fw) = %d\n",
+ "%s: guar_num_vsi (fw) = %d\n",
  prefix, number);
ice_debug(hw, ICE_DBG_INIT,
- "%s: num guaranteed VSI = %d\n",
+ "%s: guar_num_vsi = %d\n",
  prefix, func_p->guar_num_vsi);
}
break;
@@ -1985,51 +1985,51 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 
cap_count,
caps->active_tc_bitmap = logical_id;
caps->maxtc = phys_id;
ice_debug(hw, ICE_DBG_INIT,
- "%s: DCB = %d\n", prefix, caps->dcb);
+ "%s: dcb = %d\n", prefix, caps->dcb);
ice_debug(hw, ICE_DBG_INIT,
- "%s: active TC bitmap = %d\n", prefix,
+ "%s: active_tc_bitmap = %d\n", prefix,
  caps->active_tc_bitmap);
ice_debug(hw, ICE_DBG_INIT,
- "%s: TC max = %d\n", prefix, caps->maxtc);
+ "%s: maxtc = %d\n", prefix, caps->maxtc);
break;
case ICE_AQC_CAPS_RSS:
caps->rss_table_size = number;
caps->rss_table_entry_width = logical_id;
ice_debug(hw, ICE_DBG_INIT,
- "%s: RSS table size = %d\n", prefix,
+ "%s: rss_table_size = %d\n", prefix,
  caps->rss_table_size);
ice_debug(hw, ICE_DBG_INIT,
- "%s: RSS table width = %d\n", prefix,
+ "%s: rss_table_entry_width = %d\n", prefix,
  caps->rss_table_entry_width);
break;
case ICE_AQC_CAPS_RXQS:
caps->num_rxq = number;
caps->rxq_first_id = phys_id;
ice_debug(hw, ICE_DBG_INIT,
- "%s: num Rx queues = %d\n", prefix,
+ "%s: num_rxq = %d\n", prefix,
  caps->num_rxq);
ice_debug(hw, ICE_DBG_INIT,
- "%s: Rx first queue ID = %d\n", prefix,
+ "%s: rxq_first_id = %d\n", prefix,
  caps->rxq_first_id);
break;
case ICE_AQC_CAPS_TXQS:
caps->num_txq = number;
caps->txq_first_id = phys_id;
ice_debug(hw, ICE_DBG_INIT,
- "%s: num Tx queues = %d\n", prefix,
+ "%s: num_txq = %d\n", prefix,
  caps->num_txq);
ice_debug(hw, 

[dpdk-dev] [PATCH 12/63] net/ice/base: add helper functions for PHY caching

[Qi Zhang]

Add additional functions to aide in caching PHY
configuration.  In order to cache the initial modes,
we need to determine the operating mode based on
capabilities.   Add helper functions for flow control
and FEC to take a set of capabilities and return the
operating mode matching those capabilities.  Also add
a helper function to determine whether a PHY capability
matches a PHY configuration.

Introduce a mask for valid link speeds and unwrap
ice_copy_caps_to_cfg() for more builds so that we can utilize
it in more places.

Signed-off-by: Tony Nguyen 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_adminq_cmd.h |  1 +
 drivers/net/ice/base/ice_common.c | 83 +++
 drivers/net/ice/base/ice_common.h |  9 +++-
 3 files changed, 91 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ice/base/ice_adminq_cmd.h 
b/drivers/net/ice/base/ice_adminq_cmd.h
index 4de69dd7a..cc42180ea 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -1598,6 +1598,7 @@ struct ice_aqc_get_link_status_data {
 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3   2
 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4   3
__le16 link_speed;
+#define ICE_AQ_LINK_SPEED_M0x7FF
 #define ICE_AQ_LINK_SPEED_10MB BIT(0)
 #define ICE_AQ_LINK_SPEED_100MBBIT(1)
 #define ICE_AQ_LINK_SPEED_1000MB   BIT(2)
diff --git a/drivers/net/ice/base/ice_common.c 
b/drivers/net/ice/base/ice_common.c
index 9907d9dae..6b28f6230 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -2613,6 +2613,53 @@ ice_cache_phy_user_req(struct ice_port_info *pi,
 }
 
 /**
+ * ice_caps_to_fc_mode
+ * @caps: PHY capabilities
+ *
+ * Convert PHY FC capabilities to ice FC mode
+ */
+enum ice_fc_mode ice_caps_to_fc_mode(u8 caps)
+{
+   if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE &&
+   caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
+   return ICE_FC_FULL;
+
+   if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE)
+   return ICE_FC_TX_PAUSE;
+
+   if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
+   return ICE_FC_RX_PAUSE;
+
+   return ICE_FC_NONE;
+}
+
+/**
+ * ice_caps_to_fec_mode
+ * @caps: PHY capabilities
+ * @fec_options: Link FEC options
+ *
+ * Convert PHY FEC capabilities to ice FEC mode
+ */
+enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options)
+{
+   if (caps & ICE_AQC_PHY_EN_AUTO_FEC)
+   return ICE_FEC_AUTO;
+
+   if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
+  ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
+  ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN |
+  ICE_AQC_PHY_FEC_25G_KR_REQ))
+   return ICE_FEC_BASER;
+
+   if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ |
+  ICE_AQC_PHY_FEC_25G_RS_544_REQ |
+  ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN))
+   return ICE_FEC_RS;
+
+   return ICE_FEC_NONE;
+}
+
+/**
  * ice_set_fc
  * @pi: port information structure
  * @aq_failures: pointer to status code, specific to ice_set_fc routine
@@ -2719,6 +2766,42 @@ ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, 
bool ena_auto_link_update)
 }
 
 /**
+ * ice_phy_caps_equals_cfg
+ * @phy_caps: PHY capabilities
+ * @phy_cfg: PHY configuration
+ *
+ * Helper function to determine if PHY capabilities matches PHY
+ * configuration
+ */
+bool
+ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps,
+   struct ice_aqc_set_phy_cfg_data *phy_cfg)
+{
+   u8 caps_mask, cfg_mask;
+
+   if (!phy_caps || !phy_cfg)
+   return false;
+
+   /* These bits are not common between capabilities and configuration.
+* Do not use them to determine equality.
+*/
+   caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE |
+ ICE_AQC_PHY_EN_MOD_QUAL);
+   cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
+
+   if (phy_caps->phy_type_low != phy_cfg->phy_type_low ||
+   phy_caps->phy_type_high != phy_cfg->phy_type_high ||
+   ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) ||
+   phy_caps->low_power_ctrl != phy_cfg->low_power_ctrl ||
+   phy_caps->eee_cap != phy_cfg->eee_cap ||
+   phy_caps->eeer_value != phy_cfg->eeer_value ||
+   phy_caps->link_fec_options != phy_cfg->link_fec_opt)
+   return false;
+
+   return true;
+}
+
+/**
  * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
  * @caps: PHY ability structure to copy date from
  * @cfg: PHY configuration structure to copy data to
diff --git a/drivers/net/ice/base/ice_common.h 
b/drivers/net/ice/base/ice_common.h
index df1fecec5..a8104dfa2 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -139,14 +1

[dpdk-dev] [PATCH 11/63] net/ice/base: add capabilities when in safe mode

[Qi Zhang]

The dynamic device personalization (DDP) file download onto the device
can fail, and when this happens the driver has to transition to "safe
mode" where only basic functionality is possible.

The device though doesn't understand safe mode, and so the opcodes to
discover device/function capabilities (0x000A and 0x000B) return all
the capabilities of the device, which includes capabilities that the
driver cannot support when in safe mode.

The initialization flows in the driver are based on the capabilities
information (obtained by the driver with the above mentioned opcodes).
To reuse the same initialization flows in safe mode, it becomes
necessary for the driver to override the currently stored capabilities
information with safe mode capabilities. This is done by a new function
introduced in this patch - ice_set_safe_mode_caps.

Signed-off-by: Anirudh Venkataramanan 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_common.c | 64 +++
 drivers/net/ice/base/ice_common.h |  2 ++
 2 files changed, 66 insertions(+)

diff --git a/drivers/net/ice/base/ice_common.c 
b/drivers/net/ice/base/ice_common.c
index ae7837149..9907d9dae 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -2172,6 +2172,70 @@ ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc 
opc)
 }
 
 /**
+ * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode
+ * @hw: pointer to the hardware structure
+ */
+void ice_set_safe_mode_caps(struct ice_hw *hw)
+{
+   struct ice_hw_func_caps *func_caps = &hw->func_caps;
+   struct ice_hw_dev_caps *dev_caps = &hw->dev_caps;
+   u32 valid_func, rxq_first_id, txq_first_id;
+   u32 msix_vector_first_id, max_mtu;
+   u32 num_funcs;
+
+   /* cache some func_caps values that should be restored after memset */
+   valid_func = func_caps->common_cap.valid_functions;
+   txq_first_id = func_caps->common_cap.txq_first_id;
+   rxq_first_id = func_caps->common_cap.rxq_first_id;
+   msix_vector_first_id = func_caps->common_cap.msix_vector_first_id;
+   max_mtu = func_caps->common_cap.max_mtu;
+
+   /* unset func capabilities */
+   memset(func_caps, 0, sizeof(*func_caps));
+
+   /* restore cached values */
+   func_caps->common_cap.valid_functions = valid_func;
+   func_caps->common_cap.txq_first_id = txq_first_id;
+   func_caps->common_cap.rxq_first_id = rxq_first_id;
+   func_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
+   func_caps->common_cap.max_mtu = max_mtu;
+
+   /* one Tx and one Rx queue in safe mode */
+   func_caps->common_cap.num_rxq = 1;
+   func_caps->common_cap.num_txq = 1;
+
+   /* two MSIX vectors, one for traffic and one for misc causes */
+   func_caps->common_cap.num_msix_vectors = 2;
+   func_caps->guar_num_vsi = 1;
+
+   /* cache some dev_caps values that should be restored after memset */
+   valid_func = dev_caps->common_cap.valid_functions;
+   txq_first_id = dev_caps->common_cap.txq_first_id;
+   rxq_first_id = dev_caps->common_cap.rxq_first_id;
+   msix_vector_first_id = dev_caps->common_cap.msix_vector_first_id;
+   max_mtu = dev_caps->common_cap.max_mtu;
+   num_funcs = dev_caps->num_funcs;
+
+   /* unset dev capabilities */
+   memset(dev_caps, 0, sizeof(*dev_caps));
+
+   /* restore cached values */
+   dev_caps->common_cap.valid_functions = valid_func;
+   dev_caps->common_cap.txq_first_id = txq_first_id;
+   dev_caps->common_cap.rxq_first_id = rxq_first_id;
+   dev_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
+   dev_caps->common_cap.max_mtu = max_mtu;
+   dev_caps->num_funcs = num_funcs;
+
+   /* one Tx and one Rx queue per function in safe mode */
+   dev_caps->common_cap.num_rxq = num_funcs;
+   dev_caps->common_cap.num_txq = num_funcs;
+
+   /* two MSIX vectors per function */
+   dev_caps->common_cap.num_msix_vectors = 2 * num_funcs;
+}
+
+/**
  * ice_get_caps - get info about the HW
  * @hw: pointer to the hardware structure
  */
diff --git a/drivers/net/ice/base/ice_common.h 
b/drivers/net/ice/base/ice_common.h
index d865021bf..df1fecec5 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -61,6 +61,8 @@ void ice_clear_pxe_mode(struct ice_hw *hw);
 
 enum ice_status ice_get_caps(struct ice_hw *hw);
 
+void ice_set_safe_mode_caps(struct ice_hw *hw);
+
 /* Define a macro that will align a pointer to point to the next memory address
  * that falls on the given power of 2 (i.e., 2, 4, 8, 16, 32, 64...). For
  * example, given the variable pointer = 0x1006, then after the following call:
-- 
2.13.6

[dpdk-dev] [PATCH 15/63] net/ice/base: add NVM pkg flag

[Qi Zhang]

Add flag for case where active package has been loaded from NVM.

Signed-off-by: Ashish Shah 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_flex_pipe.c | 1 +
 drivers/net/ice/base/ice_type.h  | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/net/ice/base/ice_flex_pipe.c 
b/drivers/net/ice/base/ice_flex_pipe.c
index afb867877..5a5dbff5b 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -1144,6 +1144,7 @@ static enum ice_status ice_get_pkg_info(struct ice_hw *hw)
   pkg_info->pkg_info[i].name,
   sizeof(hw->active_pkg_name),
   ICE_NONDMA_TO_NONDMA);
+   hw->active_pkg_in_nvm = pkg_info->pkg_info[i].is_in_nvm;
}
if (pkg_info->pkg_info[i].is_active_at_boot)
flags[place++] = 'B';
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 0dba94a53..79d7bb1dd 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -773,6 +773,7 @@ struct ice_hw {
/* Active package version (currently active) */
struct ice_pkg_ver active_pkg_ver;
u8 active_pkg_name[ICE_PKG_NAME_SIZE];
+   u8 active_pkg_in_nvm;
 
/* Driver's package ver - (from the Metadata seg) */
struct ice_pkg_ver pkg_ver;
-- 
2.13.6

[dpdk-dev] [PATCH 13/63] net/ice/base: add support for reading REPC statistics

[Qi Zhang]

The GLV_REPC register contains statistics for tracking received packets
that are discarded due to certain errors.

This register behaves differently from some of the other related
statistics registers in two ways. First, it contains two 16bit
statistics, and thus cannot be read as a 32bit or 40bit statistic.

Second, the two stats do not roll over, but instead cap at 0x.

Add a new ice_stat_update_repc function which will read the register and
increment the appropriate statistics in the ice_eth_stats structure.

Since the register does not roll over, make use of the "Write Clear"
behavior, and write to the register to reset it every time we read it.

Add extra space for the two statistics that are counted by this
register, rx_errors, and rx_no_desc.

For now, wrap the new function and stats counters in !LINUX_SUPPORT.
This can later be removed if and when the Linux driver implements
support for reading the statistics.

Signed-off-by: Jacob Keller 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_common.c | 51 +++
 drivers/net/ice/base/ice_common.h |  3 +++
 drivers/net/ice/base/ice_type.h   |  2 ++
 3 files changed, 56 insertions(+)

diff --git a/drivers/net/ice/base/ice_common.c 
b/drivers/net/ice/base/ice_common.c
index 6b28f6230..36434ee42 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -4253,6 +4253,57 @@ ice_stat_update32(struct ice_hw *hw, u32 reg, bool 
prev_stat_loaded,
*prev_stat = new_data;
 }
 
+/**
+ * ice_stat_update_repc - read GLV_REPC stats from chip and update stat values
+ * @hw: ptr to the hardware info
+ * @vsi_handle: VSI handle
+ * @prev_stat_loaded: bool to specify if the previous stat values are loaded
+ * @cur_stats: ptr to current stats structure
+ *
+ * The GLV_REPC statistic register actually tracks two 16bit statistics, and
+ * thus cannot be read using the normal ice_stat_update32 function.
+ *
+ * Read the GLV_REPC register associated with the given VSI, and update the
+ * rx_no_desc and rx_error values in the ice_eth_stats structure.
+ *
+ * Because the statistics in GLV_REPC stick at 0x, the register must be
+ * cleared each time it's read.
+ *
+ * Note that the GLV_RDPC register also counts the causes that would trigger
+ * GLV_REPC. However, it does not give the finer grained detail about why the
+ * packets are being dropped. The GLV_REPC values can be used to distinguish
+ * whether Rx packets are dropped due to errors or due to no available
+ * descriptors.
+ */
+void
+ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded,
+struct ice_eth_stats *cur_stats)
+{
+   u16 vsi_num, no_desc, error_cnt;
+   u32 repc;
+
+   if (!ice_is_vsi_valid(hw, vsi_handle))
+   return;
+
+   vsi_num = ice_get_hw_vsi_num(hw, vsi_handle);
+
+   /* If we haven't loaded stats yet, just clear the current value */
+   if (!prev_stat_loaded) {
+   wr32(hw, GLV_REPC(vsi_num), 0);
+   return;
+   }
+
+   repc = rd32(hw, GLV_REPC(vsi_num));
+   no_desc = (repc & GLV_REPC_NO_DESC_CNT_M) >> GLV_REPC_NO_DESC_CNT_S;
+   error_cnt = (repc & GLV_REPC_ERROR_CNT_M) >> GLV_REPC_ERROR_CNT_S;
+
+   /* Clear the count by writing to the stats register */
+   wr32(hw, GLV_REPC(vsi_num), 0);
+
+   cur_stats->rx_no_desc += no_desc;
+   cur_stats->rx_errors += error_cnt;
+}
+
 
 /**
  * ice_sched_query_elem - query element information from HW
diff --git a/drivers/net/ice/base/ice_common.h 
b/drivers/net/ice/base/ice_common.h
index a8104dfa2..1fd256a42 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -211,6 +211,9 @@ void
 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
  u64 *prev_stat, u64 *cur_stat);
 void
+ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded,
+struct ice_eth_stats *cur_stats);
+void
 ice_get_nvm_version(struct ice_hw *hw, u8 *oem_ver, u16 *oem_build,
u8 *oem_patch, u8 *ver_hi, u8 *ver_lo);
 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw);
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 7194cb9ec..0dba94a53 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -833,6 +833,8 @@ struct ice_eth_stats {
u64 tx_broadcast;   /* bptc */
u64 tx_discards;/* tdpc */
u64 tx_errors;  /* tepc */
+   u64 rx_no_desc; /* repc */
+   u64 rx_errors;  /* repc */
 };
 
 #define ICE_MAX_UP 8
-- 
2.13.6

[dpdk-dev] [PATCH 16/63] net/ice/base: move VSI to VSI group

[Qi Zhang]

Add function to add a VSI to a given VSIG and update package with this
entry. The usual flow in XLT management would iterate through all
characteristics of the input VSI and create a new VSIG and TCAMs till a
matching characteristic is found. When a match is found the VSI is moved
into a matching VSIG and entries are collapsed, leading to added package
update calls. This function serves as an optimization if we know
beforehand that the input VSI has characteristics same as VSI configured
previously added to a VSIG. This is particularly useful for VF VSIs
which are all usually programmed with the same configurations.

Signed-off-by: Vignesh Sridhar 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_flex_pipe.c | 41 
 drivers/net/ice/base/ice_flex_pipe.h |  2 ++
 drivers/net/ice/base/ice_flow.c  | 28 
 drivers/net/ice/base/ice_flow.h  |  4 +++-
 4 files changed, 74 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ice/base/ice_flex_pipe.c 
b/drivers/net/ice/base/ice_flex_pipe.c
index 5a5dbff5b..00e1ec7bd 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -4772,6 +4772,47 @@ ice_find_prof_vsig(struct ice_hw *hw, enum ice_block 
blk, u64 hdl, u16 *vsig)
 }
 
 /**
+ * ice_add_vsi_flow - add VSI flow
+ * @hw: pointer to the HW struct
+ * @blk: hardware block
+ * @vsi: input VSI
+ * @vsig: target VSIG to include the input VSI
+ *
+ * Calling this function will add the VSI to a given VSIG and
+ * update the HW tables accordingly. This call can be used to
+ * add multiple VSIs to a VSIG if we know beforehand that those
+ * VSIs have the same characteristics of the VSIG. This will
+ * save time in generating a new VSIG and TCAMs till a match is
+ * found and subsequent rollback when a matching VSIG is found.
+ */
+enum ice_status
+ice_add_vsi_flow(struct ice_hw *hw, enum ice_block blk, u16 vsi, u16 vsig)
+{
+   struct ice_chs_chg *tmp, *del;
+   struct LIST_HEAD_TYPE chg;
+   enum ice_status status;
+
+   /* if target VSIG is default the move is invalid */
+   if ((vsig & ICE_VSIG_IDX_M) == ICE_DEFAULT_VSIG)
+   return ICE_ERR_PARAM;
+
+   INIT_LIST_HEAD(&chg);
+
+   /* move VSI to the VSIG that matches */
+   status = ice_move_vsi(hw, blk, vsi, vsig, &chg);
+   /* update hardware if success */
+   if (!status)
+   status = ice_upd_prof_hw(hw, blk, &chg);
+
+   LIST_FOR_EACH_ENTRY_SAFE(del, tmp, &chg, ice_chs_chg, list_entry) {
+   LIST_DEL(&del->list_entry);
+   ice_free(hw, del);
+   }
+
+   return status;
+}
+
+/**
  * ice_add_prof_id_flow - add profile flow
  * @hw: pointer to the HW struct
  * @blk: hardware block
diff --git a/drivers/net/ice/base/ice_flex_pipe.h 
b/drivers/net/ice/base/ice_flex_pipe.h
index 2801e1b50..f01dfbb98 100644
--- a/drivers/net/ice/base/ice_flex_pipe.h
+++ b/drivers/net/ice/base/ice_flex_pipe.h
@@ -50,6 +50,8 @@ ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, 
u8 ptypes[],
 struct ice_prof_map *
 ice_search_prof_id(struct ice_hw *hw, enum ice_block blk, u64 id);
 enum ice_status
+ice_add_vsi_flow(struct ice_hw *hw, enum ice_block blk, u16 vsi, u16 vsig);
+enum ice_status
 ice_add_prof_id_flow(struct ice_hw *hw, enum ice_block blk, u16 vsi, u64 hdl);
 enum ice_status
 ice_rem_prof_id_flow(struct ice_hw *hw, enum ice_block blk, u16 vsi, u64 hdl);
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index 36d31fa13..fb9041b3e 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -1112,6 +1112,34 @@ ice_flow_rem_prof_sync(struct ice_hw *hw, enum ice_block 
blk,
 }
 
 /**
+ * ice_flow_assoc_vsig_vsi - associate a VSI with VSIG
+ * @hw: pointer to the hardware structure
+ * @blk: classification stage
+ * @vsi_handle: software VSI handle
+ * @vsig: target VSI group
+ *
+ * Assumption: the caller has already verified that the VSI to
+ * be added has the same characteristics as the VSIG and will
+ * thereby have access to all resources added to that VSIG.
+ */
+enum ice_status
+ice_flow_assoc_vsig_vsi(struct ice_hw *hw, enum ice_block blk, u16 vsi_handle,
+   u16 vsig)
+{
+   enum ice_status status;
+
+   if (!ice_is_vsi_valid(hw, vsi_handle) || blk >= ICE_BLK_COUNT)
+   return ICE_ERR_PARAM;
+
+   ice_acquire_lock(&hw->fl_profs_locks[blk]);
+   status = ice_add_vsi_flow(hw, blk, ice_get_hw_vsi_num(hw, vsi_handle),
+ vsig);
+   ice_release_lock(&hw->fl_profs_locks[blk]);
+
+   return status;
+}
+
+/**
  * ice_flow_assoc_prof - associate a VSI with a flow profile
  * @hw: pointer to the hardware structure
  * @blk: classification stage
diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h
index c6442dc14..3a0fd23c4 100644
--- a/drivers/net/ice/base/ice_flow.h
++

[dpdk-dev] [PATCH 18/63] net/ice/base: resolve static analysis issues

[Qi Zhang]

Coverity complains first_free can be -1 resulting in a negative shift left
when k equals 0; i.e. the expression 1 << (first_free - k). Fix this by
explicitly checking for this case.

Cc: sta...@dpdk.org

Signed-off-by: Dan Nowlin 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_flex_pipe.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ice/base/ice_flex_pipe.c 
b/drivers/net/ice/base/ice_flex_pipe.c
index 29888df76..73362c909 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -4200,7 +4200,7 @@ ice_update_fd_swap(struct ice_hw *hw, u16 prof_id, struct 
ice_fv_word *es)
index = i + 1;
 
/* check for room */
-   if (first_free + 1 < ice_fd_pairs[index].count)
+   if (first_free + 1 < (s8)ice_fd_pairs[index].count)
return ICE_ERR_MAX_LIMIT;
 
/* place in extraction sequence */
@@ -4210,6 +4210,9 @@ ice_update_fd_swap(struct ice_hw *hw, u16 prof_id, struct 
ice_fv_word *es)
es[first_free - k].off =
ice_fd_pairs[index].off + (k * 2);
 
+   if (k > first_free)
+   return ICE_ERR_OUT_OF_RANGE;
+
/* keep track of non-relevant fields */
mask_sel |= 1 << (first_free - k);
}
-- 
2.13.6

[dpdk-dev] [PATCH 14/63] net/ice/base: adjust DCB INIT for SW mode

[Qi Zhang]

Adjust ice_init_dcb to set the is_sw_lldp boolean
in the case where the FW has been detected to be
in an untenable state such that the driver
should forcibly make sure it is off.

This will ensure that the FW is in a known state.

Signed-off-by: Dave Ertman 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_dcb.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ice/base/ice_dcb.c b/drivers/net/ice/base/ice_dcb.c
index a6fbedd18..7048dbd02 100644
--- a/drivers/net/ice/base/ice_dcb.c
+++ b/drivers/net/ice/base/ice_dcb.c
@@ -966,9 +966,9 @@ enum ice_status ice_init_dcb(struct ice_hw *hw, bool 
enable_mib_change)
pi->dcbx_status == ICE_DCBX_STATUS_NOT_STARTED) {
/* Get current DCBX configuration */
ret = ice_get_dcb_cfg(pi);
-   pi->is_sw_lldp = (hw->adminq.sq_last_status == ICE_AQ_RC_EPERM);
if (ret)
return ret;
+   pi->is_sw_lldp = false;
} else if (pi->dcbx_status == ICE_DCBX_STATUS_DIS) {
return ICE_ERR_NOT_READY;
}
@@ -976,8 +976,8 @@ enum ice_status ice_init_dcb(struct ice_hw *hw, bool 
enable_mib_change)
/* Configure the LLDP MIB change event */
if (enable_mib_change) {
ret = ice_aq_cfg_lldp_mib_change(hw, true, NULL);
-   if (!ret)
-   pi->is_sw_lldp = false;
+   if (ret)
+   pi->is_sw_lldp = true;
}
 
return ret;
-- 
2.13.6

[dpdk-dev] [PATCH 17/63] net/ice/base: enable masking for RSS and FD field vectors

[Qi Zhang]

Allow masking per word field on RSS and FD field vectors.

Signed-off-by: Dan Nowlin 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_flex_pipe.c | 540 ++-
 drivers/net/ice/base/ice_flex_pipe.h |   5 +
 drivers/net/ice/base/ice_flex_type.h |  17 ++
 drivers/net/ice/base/ice_flow.c  |  21 +-
 4 files changed, 578 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ice/base/ice_flex_pipe.c 
b/drivers/net/ice/base/ice_flex_pipe.c
index 00e1ec7bd..29888df76 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -2500,6 +2500,102 @@ ice_vsig_add_mv_vsi(struct ice_hw *hw, enum ice_block 
blk, u16 vsi, u16 vsig)
 }
 
 /**
+ * ice_prof_has_mask_idx - determine if profile index masking is identical
+ * @hw: pointer to the hardware structure
+ * @blk: HW block
+ * @prof: profile to check
+ * @idx: profile index to check
+ * @masks: masks to match
+ */
+static bool
+ice_prof_has_mask_idx(struct ice_hw *hw, enum ice_block blk, u8 prof, u16 idx,
+ u16 mask)
+{
+   bool expect_no_mask = false;
+   bool found = false;
+   bool match = false;
+   u16 i;
+
+   /* If mask is 0x or 0x, then there is no masking */
+   if (mask == 0 || mask == 0x)
+   expect_no_mask = true;
+
+   /* Scan the enabled masks on this profile, for the specified idx */
+   for (i = 0; i < ICE_PROFILE_MASK_COUNT; i++)
+   if (hw->blk[blk].es.mask_ena[prof] & BIT(i))
+   if (hw->blk[blk].masks.masks[i].in_use &&
+   hw->blk[blk].masks.masks[i].idx == idx) {
+   found = true;
+   if (hw->blk[blk].masks.masks[i].mask == mask)
+   match = true;
+   break;
+   }
+
+   if (expect_no_mask) {
+   if (found)
+   return false;
+   } else {
+   if (!match)
+   return false;
+   }
+
+   return true;
+}
+
+/**
+ * ice_prof_has_mask - determine if profile masking is identical
+ * @hw: pointer to the hardware structure
+ * @blk: HW block
+ * @prof: profile to check
+ * @masks: masks to match
+ */
+static bool
+ice_prof_has_mask(struct ice_hw *hw, enum ice_block blk, u8 prof, u16 *masks)
+{
+   u16 i;
+
+   /* es->mask_ena[prof] will have the mask */
+   for (i = 0; i < hw->blk[blk].es.fvw; i++)
+   if (!ice_prof_has_mask_idx(hw, blk, prof, i, masks[i]))
+   return false;
+
+   return true;
+}
+
+/**
+ * ice_find_prof_id_with_mask - find profile ID for a given field vector
+ * @hw: pointer to the hardware structure
+ * @blk: HW block
+ * @fv: field vector to search for
+ * @masks: masks for fv
+ * @prof_id: receives the profile ID
+ */
+static enum ice_status
+ice_find_prof_id_with_mask(struct ice_hw *hw, enum ice_block blk,
+  struct ice_fv_word *fv, u16 *masks, u8 *prof_id)
+{
+   struct ice_es *es = &hw->blk[blk].es;
+   u16 i;
+
+   for (i = 0; i < es->count; i++) {
+   u16 off = i * es->fvw;
+   u16 j;
+
+   if (memcmp(&es->t[off], fv, es->fvw * sizeof(*fv)))
+   continue;
+
+   /* check if masks settings are the same for this profile */
+   if (!ice_prof_has_mask(hw, blk, i, masks))
+   continue;
+
+   *prof_id = i;
+   return ICE_SUCCESS;
+   }
+
+   return ICE_ERR_DOES_NOT_EXIST;
+}
+
+/**
  * ice_find_prof_id - find profile ID for a given field vector
  * @hw: pointer to the hardware structure
  * @blk: HW block
@@ -2687,6 +2783,334 @@ ice_prof_inc_ref(struct ice_hw *hw, enum ice_block blk, 
u8 prof_id)
 }
 
 /**
+ * ice_write_prof_mask_reg - write profile mask register
+ * @hw: pointer to the HW struct
+ * @blk: hardware block
+ * @mask_idx: mask index
+ * @idx: index of the FV which will use the mask
+ * @mask: the 16-bit mask
+ */
+static void
+ice_write_prof_mask_reg(struct ice_hw *hw, enum ice_block blk, u16 mask_idx,
+   u16 idx, u16 mask)
+{
+   u32 offset;
+   u32 val;
+
+   switch (blk) {
+   case ICE_BLK_RSS:
+   offset = GLQF_HMASK(mask_idx);
+   val = (idx << GLQF_HMASK_MSK_INDEX_S) &
+   GLQF_HMASK_MSK_INDEX_M;
+   val |= (mask << GLQF_HMASK_MASK_S) & GLQF_HMASK_MASK_M;
+   break;
+   case ICE_BLK_FD:
+   offset = GLQF_FDMASK(mask_idx);
+   val = (idx << GLQF_FDMASK_MSK_INDEX_S) &
+   GLQF_FDMASK_MSK_INDEX_M;
+   val |= (mask << GLQF_FDMASK_MASK_S) &
+   GLQF_FDMASK_MASK_M;
+   break;
+   default:
+   ice_debug(hw, ICE_DBG_PKG, "No profile masks for block %d

[dpdk-dev] [PATCH 19/63] net/ice/base: fix memory leak issue

[Qi Zhang]

Need to free new ice_vsig_prof if no valid ptype can be found.

Fixes: d935fb5bb091 ("net/ice/base: fix packet type size")
Cc: sta...@dpdk.org

Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_flex_pipe.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ice/base/ice_flex_pipe.c 
b/drivers/net/ice/base/ice_flex_pipe.c
index 73362c909..7daaf10b0 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -4918,8 +4918,10 @@ ice_add_prof_to_lst(struct ice_hw *hw, enum ice_block 
blk,
p->tcam[i].prof_id = map->prof_id;
p->tcam[i].tcam_idx = ICE_INVALID_TCAM;
 
-   if (ice_ptg_find_ptype(hw, blk, map->ptype[i], &ptg))
+   if (ice_ptg_find_ptype(hw, blk, map->ptype[i], &ptg)) {
+   ice_free(hw, p);
return ICE_ERR_CFG;
+   }
 
p->tcam[i].ptg = ptg;
}
-- 
2.13.6

[dpdk-dev] [PATCH 20/63] net/ice/base: check root pointer for validity

[Qi Zhang]

ice_sched_get_tc_node uses pi->root without checking for NULL. Add a
check to prevent NULL pointer dereference.

Signed-off-by: Anirudh Venkataramanan 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_sched.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c
index d16f256c9..84a033f1c 100644
--- a/drivers/net/ice/base/ice_sched.c
+++ b/drivers/net/ice/base/ice_sched.c
@@ -284,7 +284,7 @@ struct ice_sched_node *ice_sched_get_tc_node(struct 
ice_port_info *pi, u8 tc)
 {
u8 i;
 
-   if (!pi)
+   if (!pi || !pi->root)
return NULL;
for (i = 0; i < pi->root->num_children; i++)
if (pi->root->children[i]->tc_num == tc)
-- 
2.13.6

[dpdk-dev] [PATCH 22/63] net/ice/base: correct overrun Coverty hit

[Qi Zhang]

Added boundary check for layer_num in function ice_sched_rm_rl_profile,
and ice_sched_add_rl_profile.

Cc: sta...@dpdk.org

Tarun Singh 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_sched.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c
index 01c8defae..1cfc3bc20 100644
--- a/drivers/net/ice/base/ice_sched.c
+++ b/drivers/net/ice/base/ice_sched.c
@@ -3799,10 +3799,12 @@ ice_sched_add_rl_profile(struct ice_port_info *pi,
struct ice_aqc_rl_profile_generic_elem *buf;
struct ice_aqc_rl_profile_info *rl_prof_elem;
u16 profiles_added = 0, num_profiles = 1;
-   enum ice_status status = ICE_ERR_PARAM;
+   enum ice_status status;
struct ice_hw *hw;
u8 profile_type;
 
+   if (layer_num >= ICE_AQC_TOPO_MAX_LEVEL_NUM)
+   return NULL;
switch (rl_type) {
case ICE_MIN_BW:
profile_type = ICE_AQC_RL_PROFILE_TYPE_CIR;
@@ -4049,6 +4051,8 @@ ice_sched_rm_rl_profile(struct ice_port_info *pi, u8 
layer_num, u8 profile_type,
struct ice_aqc_rl_profile_info *rl_prof_elem;
enum ice_status status = ICE_SUCCESS;
 
+   if (layer_num >= ICE_AQC_TOPO_MAX_LEVEL_NUM)
+   return ICE_ERR_PARAM;
/* Check the existing list for RL profile */
LIST_FOR_EACH_ENTRY(rl_prof_elem, &pi->rl_prof_list[layer_num],
ice_aqc_rl_profile_info, list_entry)
-- 
2.13.6

[dpdk-dev] [PATCH 21/63] net/ice/base: fix type-mismatch

[Qi Zhang]

The iterators are u8, but the values being compared against are u16s.
It may not ever be the case that the comparison is against a value
larger than the upper bound of the smaller type, but code analysis tools
don't know that.

Fixes: 93e84b1bfc92 ("net/ice/base: add basic Tx scheduler")
Cc: sta...@dpdk.org

Signed-off-by: Jeb Cramer 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_sched.c | 9 -
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c
index 84a033f1c..01c8defae 100644
--- a/drivers/net/ice/base/ice_sched.c
+++ b/drivers/net/ice/base/ice_sched.c
@@ -735,7 +735,7 @@ ice_sched_del_rl_profile(struct ice_hw *hw,
  */
 static void ice_sched_clear_rl_prof(struct ice_port_info *pi)
 {
-   u8 ln;
+   u16 ln;
 
for (ln = 0; ln < pi->hw->num_tx_sched_layers; ln++) {
struct ice_aqc_rl_profile_info *rl_prof_elem;
@@ -2181,12 +2181,11 @@ static enum ice_status
 ice_sched_move_nodes(struct ice_port_info *pi, struct ice_sched_node *parent,
 u16 num_items, u32 *list)
 {
+   enum ice_status status = ICE_SUCCESS;
struct ice_aqc_move_elem *buf;
struct ice_sched_node *node;
-   enum ice_status status = ICE_SUCCESS;
+   u16 i, grps_movd = 0;
struct ice_hw *hw;
-   u16 grps_movd = 0;
-   u8 i;
 
hw = pi->hw;
 
@@ -2802,7 +2801,7 @@ ice_sched_assoc_vsi_to_agg(struct ice_port_info *pi, u32 
agg_id,
  */
 static void ice_sched_rm_unused_rl_prof(struct ice_port_info *pi)
 {
-   u8 ln;
+   u16 ln;
 
for (ln = 0; ln < pi->hw->num_tx_sched_layers; ln++) {
struct ice_aqc_rl_profile_info *rl_prof_elem;
-- 
2.13.6

[dpdk-dev] [PATCH 23/63] net/ice/base: update Boot Configuration Section read of NVM

[Qi Zhang]

Boot Configuration Section Block has been moved to the
Preserved Field Area (PFA) of NVM. So, this patch updates
the NVM reads that involve Boot Configuration Section.

Signed-off-by: Md Fahad Iqbal Polash 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_devids.h |  6 +++
 drivers/net/ice/base/ice_nvm.c| 39 +-
 drivers/net/ice/base/ice_nvm.h| 87 +++
 drivers/net/ice/base/ice_type.h   |  4 +-
 4 files changed, 124 insertions(+), 12 deletions(-)
 create mode 100644 drivers/net/ice/base/ice_nvm.h

diff --git a/drivers/net/ice/base/ice_devids.h 
b/drivers/net/ice/base/ice_devids.h
index 5f1ac0422..c9a567fb1 100644
--- a/drivers/net/ice/base/ice_devids.h
+++ b/drivers/net/ice/base/ice_devids.h
@@ -13,5 +13,11 @@
 #define ICE_DEV_ID_E810C_QSFP  0x1592
 /* Intel(R) Ethernet Controller E810-C for SFP */
 #define ICE_DEV_ID_E810C_SFP   0x1593
+/* Intel(R) Ethernet Connection C822N for backplane */
+#define ICE_DEV_ID_C822N_BACKPLANE 0x1890
+/* Intel(R) Ethernet Connection C822N for QSFP */
+#define ICE_DEV_ID_C822N_QSFP  0x1891
+/* Intel(R) Ethernet Connection C822N for SFP */
+#define ICE_DEV_ID_C822N_SFP   0x1892
 
 #endif /* _ICE_DEVIDS_H_ */
diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c
index c0f9e353e..95a6c9ab6 100644
--- a/drivers/net/ice/base/ice_nvm.c
+++ b/drivers/net/ice/base/ice_nvm.c
@@ -263,9 +263,9 @@ enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 
offset, u16 *data)
 enum ice_status ice_init_nvm(struct ice_hw *hw)
 {
struct ice_nvm_info *nvm = &hw->nvm;
-   u16 oem_hi, oem_lo, cfg_ptr;
+   u16 oem_hi, oem_lo, boot_cfg_tlv, boot_cfg_tlv_len;
u16 eetrack_lo, eetrack_hi;
-   enum ice_status status = ICE_SUCCESS;
+   enum ice_status status;
u32 fla, gens_stat;
u8 sr_size;
 
@@ -284,12 +284,12 @@ enum ice_status ice_init_nvm(struct ice_hw *hw)
fla = rd32(hw, GLNVM_FLA);
if (fla & GLNVM_FLA_LOCKED_M) { /* Normal programming mode */
nvm->blank_nvm_mode = false;
-   } else { /* Blank programming mode */
+   } else {
+   /* Blank programming mode */
nvm->blank_nvm_mode = true;
-   status = ICE_ERR_NVM_BLANK_MODE;
ice_debug(hw, ICE_DBG_NVM,
  "NVM init error: unsupported blank mode.\n");
-   return status;
+   return ICE_ERR_NVM_BLANK_MODE;
}
 
status = ice_read_sr_word(hw, ICE_SR_NVM_DEV_STARTER_VER, &nvm->ver);
@@ -312,19 +312,37 @@ enum ice_status ice_init_nvm(struct ice_hw *hw)
 
nvm->eetrack = (eetrack_hi << 16) | eetrack_lo;
 
-   status = ice_read_sr_word(hw, ICE_SR_BOOT_CFG_PTR, &cfg_ptr);
+   /* the following devices do not have boot_cfg_tlv yet */
+   if (hw->device_id == ICE_DEV_ID_C822N_BACKPLANE ||
+   hw->device_id == ICE_DEV_ID_C822N_QSFP ||
+   hw->device_id == ICE_DEV_ID_C822N_SFP)
+   return status;
+
+   status = ice_get_pfa_module_tlv(hw, &boot_cfg_tlv, &boot_cfg_tlv_len,
+   ICE_SR_BOOT_CFG_PTR);
if (status) {
-   ice_debug(hw, ICE_DBG_INIT, "Failed to read 
BOOT_CONFIG_PTR.\n");
+   ice_debug(hw, ICE_DBG_INIT,
+ "Failed to read Boot Configuration Block TLV.\n");
return status;
}
 
-   status = ice_read_sr_word(hw, (cfg_ptr + ICE_NVM_OEM_VER_OFF), &oem_hi);
+   /* Boot Configuration Block must have length at least 2 words
+* (Combo Image Version High and Combo Image Version Low)
+*/
+   if (boot_cfg_tlv_len < 2) {
+   ice_debug(hw, ICE_DBG_INIT,
+ "Invalid Boot Configuration Block TLV size.\n");
+   return ICE_ERR_INVAL_SIZE;
+   }
+
+   status = ice_read_sr_word(hw, (boot_cfg_tlv + ICE_NVM_OEM_VER_OFF),
+ &oem_hi);
if (status) {
ice_debug(hw, ICE_DBG_INIT, "Failed to read OEM_VER hi.\n");
return status;
}
 
-   status = ice_read_sr_word(hw, (cfg_ptr + (ICE_NVM_OEM_VER_OFF + 1)),
+   status = ice_read_sr_word(hw, (boot_cfg_tlv + ICE_NVM_OEM_VER_OFF + 1),
  &oem_lo);
if (status) {
ice_debug(hw, ICE_DBG_INIT, "Failed to read OEM_VER lo.\n");
@@ -332,7 +350,8 @@ enum ice_status ice_init_nvm(struct ice_hw *hw)
}
 
nvm->oem_ver = ((u32)oem_hi << 16) | oem_lo;
-   return status;
+
+   return ICE_SUCCESS;
 }
 
 
diff --git a/drivers/net/ice/base/ice_nvm.h b/drivers/net/ice/base/ice_nvm.h
new file mode 100644
index 0..da76b2674
--- /dev/null
+++ b/drivers/net/ice/base/ice_nvm.h
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2001-2019
+ */
+
+#ifndef _ICE_NVM_H_
+#defin

[dpdk-dev] [PATCH 24/63] net/ice/base: add support for NVM access commands

[Qi Zhang]

Add a new structure, ice_nvm_access, used to request access to read or
write certain NVM related registers.

The structure is used by NVM Update to request read or write of specific
NVM registers in order to perform updates.

Additionally, there is a command to request the driver "features"
structure which represents data about what features of the NVM access
interface the driver supports.

Implement ice_handle_nvm_access to parse the access request and perform
the necessary function.

This function verifies that the access request is valid. If so, the
function will delegate to perform the register read, register write, or
copying of the driver ice_nvm_features structure.

If the request is invalid, the function will report a suitable error
codition that can be propagated out.

Only a subset of registers is accessible, and all other registers will
be rejected with ICE_ERR_OUT_OF_RANGE.

When reading, the contents of the variable sized data buffer will be
used as storage for returning the register value. When writing, the
contents will be used as input for the value to write to the register.

Signed-off-by: Jacob Keller 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_common.h |   1 +
 drivers/net/ice/base/ice_nvm.c| 237 ++
 2 files changed, 238 insertions(+)

diff --git a/drivers/net/ice/base/ice_common.h 
b/drivers/net/ice/base/ice_common.h
index 1fd256a42..a55f7eeba 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -6,6 +6,7 @@
 #define _ICE_COMMON_H_
 
 #include "ice_type.h"
+#include "ice_nvm.h"
 #include "ice_flex_pipe.h"
 #include "ice_switch.h"
 #include "ice_fdir.h"
diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c
index 95a6c9ab6..66cfec641 100644
--- a/drivers/net/ice/base/ice_nvm.c
+++ b/drivers/net/ice/base/ice_nvm.c
@@ -411,3 +411,240 @@ enum ice_status ice_nvm_validate_checksum(struct ice_hw 
*hw)
 
return status;
 }
+
+/**
+ * ice_nvm_access_get_features - Return the NVM access features structure
+ * @cmd: NVM access command to process
+ * @data: storage for the driver NVM features
+ *
+ * Fill in the data section of the NVM access request with a copy of the NVM
+ * features structure.
+ */
+enum ice_status
+ice_nvm_access_get_features(struct ice_nvm_access_cmd *cmd,
+   union ice_nvm_access_data *data)
+{
+   /* The provided data_size must be at least as large as our NVM
+* features structure. A larger size should not be treated as an
+* error, to allow future extensions to to the features structure to
+* work on older drivers.
+*/
+   if (cmd->data_size < sizeof(struct ice_nvm_features))
+   return ICE_ERR_NO_MEMORY;
+
+   /* Initialize the data buffer to zeros */
+   ice_memset(data, 0, cmd->data_size, ICE_NONDMA_MEM);
+
+   /* Fill in the features data */
+   data->drv_features.major = ICE_NVM_ACCESS_MAJOR_VER;
+   data->drv_features.minor = ICE_NVM_ACCESS_MINOR_VER;
+   data->drv_features.size = sizeof(struct ice_nvm_features);
+   data->drv_features.features[0] = ICE_NVM_FEATURES_0_REG_ACCESS;
+
+   return ICE_SUCCESS;
+}
+
+/**
+ * ice_nvm_access_get_module - Helper function to read module value
+ * @cmd: NVM access command structure
+ *
+ * Reads the module value out of the NVM access config field.
+ */
+u32 ice_nvm_access_get_module(struct ice_nvm_access_cmd *cmd)
+{
+   return ((cmd->config & ICE_NVM_CFG_MODULE_M) >> ICE_NVM_CFG_MODULE_S);
+}
+
+/**
+ * ice_nvm_access_get_flags - Helper function to read flags value
+ * @cmd: NVM access command structure
+ *
+ * Reads the flags value out of the NVM access config field.
+ */
+u32 ice_nvm_access_get_flags(struct ice_nvm_access_cmd *cmd)
+{
+   return ((cmd->config & ICE_NVM_CFG_FLAGS_M) >> ICE_NVM_CFG_FLAGS_S);
+}
+
+/**
+ * ice_nvm_access_get_adapter - Helper function to read adapter info
+ * @cmd: NVM access command structure
+ *
+ * Read the adapter info value out of the NVM access config field.
+ */
+u32 ice_nvm_access_get_adapter(struct ice_nvm_access_cmd *cmd)
+{
+   return ((cmd->config & ICE_NVM_CFG_ADAPTER_INFO_M) >>
+   ICE_NVM_CFG_ADAPTER_INFO_S);
+}
+
+/**
+ * ice_validate_nvm_rw_reg - Check than an NVM access request is valid
+ * @cmd: NVM access command structure
+ *
+ * Validates that an NVM access structure is request to read or write a valid
+ * register offset. First validates that the module and flags are correct, and
+ * then ensures that the register offset is one of the accepted registers.
+ */
+static enum ice_status
+ice_validate_nvm_rw_reg(struct ice_nvm_access_cmd *cmd)
+{
+   u32 module, flags, offset;
+   u16 i;
+
+   module = ice_nvm_access_get_module(cmd);
+   flags = ice_nvm_access_get_flags(cmd);
+   offset = cmd->offset;
+
+   /* Make sure the module and flags indicate a read/write request */
+

[dpdk-dev] [PATCH 27/63] net/ice/base: improve switch advanced rule

[Qi Zhang]

Correct algorithm to detect free field vector indexes to be
used for recipe line result values. The code now scans all
recipes that are associated with all the field vector being
targed for a new recipe to detect which result indexes are
unused.

Change recipe chaining code to place recipe on a single line
if it will fit, rather than looking to break things apart
according to preferred combinations.

These improvements fix a condition where recipes were getting
added with conflicting result index values.

Signed-off-by: Dan Nowlin 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_bitops.h |  31 
 drivers/net/ice/base/ice_switch.c | 354 +-
 drivers/net/ice/base/ice_switch.h |   5 +
 3 files changed, 309 insertions(+), 81 deletions(-)

diff --git a/drivers/net/ice/base/ice_bitops.h 
b/drivers/net/ice/base/ice_bitops.h
index a3a67eb4b..f0aa8ce88 100644
--- a/drivers/net/ice/base/ice_bitops.h
+++ b/drivers/net/ice/base/ice_bitops.h
@@ -229,6 +229,37 @@ ice_or_bitmap(ice_bitmap_t *dst, const ice_bitmap_t *bmp1,
 }
 
 /**
+ * ice_xor_bitmap - bitwise XOR 2 bitmaps and store result in dst bitmap
+ * @dst: Destination bitmap that receive the result of the operation
+ * @bmp1: The first bitmap of XOR operation
+ * @bmp2: The second bitmap to XOR with the first
+ * @size: Size of the bitmaps in bits
+ *
+ * This function performs a bitwise XOR on two "source" bitmaps of the same 
size
+ * and stores the result to "dst" bitmap. The "dst" bitmap must be of the same
+ * size as the "source" bitmaps to avoid buffer overflows.
+ */
+static inline void
+ice_xor_bitmap(ice_bitmap_t *dst, const ice_bitmap_t *bmp1,
+  const ice_bitmap_t *bmp2, u16 size)
+{
+   ice_bitmap_t mask;
+   u16 i;
+
+   /* Handle all but last chunk*/
+   for (i = 0; i < BITS_TO_CHUNKS(size) - 1; i++)
+   dst[i] = bmp1[i] ^ bmp2[i];
+
+   /* We want to only XOR bits within the size. Furthermore, we also do
+* not want to modify destination bits which are beyond the specified
+* size. Use a bitmask to ensure that we only modify the bits that are
+* within the specified size.
+*/
+   mask = LAST_CHUNK_MASK(size);
+   dst[i] = (dst[i] & ~mask) | ((bmp1[i] ^ bmp2[i]) & mask);
+}
+
+/**
  * ice_find_next_bit - Find the index of the next set bit of a bitmap
  * @bitmap: the bitmap to scan
  * @size: the size in bits of the bitmap
diff --git a/drivers/net/ice/base/ice_switch.c 
b/drivers/net/ice/base/ice_switch.c
index f88addec6..2b0c7c7a3 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -440,11 +440,47 @@ dummy_pppoe_packet[] = {
 /* this is a recipe to profile association bitmap */
 static ice_declare_bitmap(recipe_to_profile[ICE_MAX_NUM_RECIPES],
  ICE_MAX_NUM_PROFILES);
-static ice_declare_bitmap(available_result_ids, ICE_CHAIN_FV_INDEX_START + 1);
+
+/* this is a profile to recipe association bitmap */
+static ice_declare_bitmap(profile_to_recipe[ICE_MAX_NUM_PROFILES],
+ ICE_MAX_NUM_RECIPES);
 
 static void ice_get_recp_to_prof_map(struct ice_hw *hw);
 
 /**
+ * ice_collect_result_idx - copy result index values
+ * @buf: buffer that contains the result index
+ * @recp: the recipe struct to copy data into
+ */
+static void ice_collect_result_idx(struct ice_aqc_recipe_data_elem *buf,
+  struct ice_sw_recipe *recp)
+{
+   if (buf->content.result_indx & ICE_AQ_RECIPE_ID_IS_ROOT)
+   ice_set_bit(buf->content.result_indx &
+   ~ICE_AQ_RECIPE_ID_IS_ROOT, recp->res_idxs);
+}
+
+/**
+ * ice_collect_result_idx_from_bitmap - copy result index values using bitmap
+ * @hw: pointer to hardware structure
+ * @recp: the recipe struct to copy data into
+ */
+static void
+ice_collect_result_idx_from_bitmap(struct ice_hw *hw,
+  struct ice_sw_recipe *recp)
+{
+   u16 bit = 0;
+
+   while (ICE_MAX_NUM_RECIPES >
+  (bit = ice_find_next_bit(recp->r_bitmap, ICE_MAX_NUM_RECIPES,
+   bit))) {
+   ice_collect_result_idx(hw->switch_info->recp_list[bit].root_buf,
+  recp);
+   bit++;
+   }
+}
+
+/**
  * ice_get_recp_frm_fw - update SW bookkeeping from FW recipe entries
  * @hw: pointer to hardware structure
  * @recps: struct that we need to populate
@@ -466,6 +502,7 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe 
*recps, u8 rid,
u16 num_recps = ICE_MAX_NUM_RECIPES;
struct ice_prot_lkup_ext *lkup_exts;
enum ice_status status;
+   u8 is_root;
 
/* we need a buffer big enough to accommodate all the recipes */
tmp = (struct ice_aqc_recipe_data_elem *)ice_calloc(hw,
@@ -507,14 +544,10 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct 
ice_sw_recipe *recps,

[dpdk-dev] [PATCH 25/63] net/ice/base: add support for GTP and PPPoE protocols

[Qi Zhang]

Added switch protocol segments for both GTP and PPPOE protocols.
Added RSS protocol segments for both GTP and PPPOE protocols.

Signed-off-by: Dan Nowlin 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_flow.c  | 105 ++-
 drivers/net/ice/base/ice_flow.h  |  61 ++
 drivers/net/ice/base/ice_protocol_type.h |  33 +-
 drivers/net/ice/base/ice_switch.c|  79 ++-
 4 files changed, 251 insertions(+), 27 deletions(-)

diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index 1530a72cc..0f52b3379 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -19,6 +19,8 @@
 #define ICE_FLOW_FLD_SZ_ICMP_CODE  1
 #define ICE_FLOW_FLD_SZ_ARP_OPER   2
 #define ICE_FLOW_FLD_SZ_GRE_KEYID  4
+#define ICE_FLOW_FLD_SZ_GTP_TEID   4
+#define ICE_FLOW_FLD_SZ_PPPOE_SESS_ID   2
 
 /* Protocol header fields are extracted at the word boundaries as word-sized
  * values. Specify the displacement value of some non-word-aligned fields 
needed
@@ -115,6 +117,23 @@ struct ice_flow_field_info 
ice_flds_info[ICE_FLOW_FIELD_IDX_MAX] = {
/* GRE */
/* ICE_FLOW_FIELD_IDX_GRE_KEYID */
ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_GRE, 12, ICE_FLOW_FLD_SZ_GRE_KEYID),
+   /* GTP */
+   /* ICE_FLOW_FIELD_IDX_GTPC_TEID */
+   ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_GTPC_TEID, 12,
+ ICE_FLOW_FLD_SZ_GTP_TEID),
+   /* ICE_FLOW_FIELD_IDX_GTPU_IP_TEID */
+   ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_GTPU_IP, 12,
+ ICE_FLOW_FLD_SZ_GTP_TEID),
+   /* ICE_FLOW_FIELD_IDX_GTPU_UP_TEID */
+   ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_GTPU_UP, 12,
+ ICE_FLOW_FLD_SZ_GTP_TEID),
+   /* ICE_FLOW_FIELD_IDX_GTPU_DWN_TEID */
+   ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_GTPU_DWN, 12,
+ ICE_FLOW_FLD_SZ_GTP_TEID),
+   /* PPPOE */
+   /* ICE_FLOW_FIELD_IDX_PPPOE_SESS_ID */
+   ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_PPPOE, 2,
+ ICE_FLOW_FLD_SZ_PPPOE_SESS_ID),
 };
 
 /* Bitmaps indicating relevant packet types for a particular protocol header
@@ -290,6 +309,42 @@ static const u32 ice_ptypes_mac_il[] = {
0x, 0x, 0x, 0x,
 };
 
+/* Packet types for GTPC */
+static const u32 ice_ptypes_gtpc[] = {
+   0x, 0x, 0x, 0x,
+   0x, 0x, 0x, 0x,
+   0x, 0x, 0x0180, 0x,
+   0x, 0x, 0x, 0x,
+   0x, 0x, 0x, 0x,
+   0x, 0x, 0x, 0x,
+   0x, 0x, 0x, 0x,
+   0x, 0x, 0x, 0x,
+};
+
+/* Packet types for GTPC with TEID */
+static const u32 ice_ptypes_gtpc_tid[] = {
+   0x, 0x, 0x, 0x,
+   0x, 0x, 0x, 0x,
+   0x, 0x, 0x0060, 0x,
+   0x, 0x, 0x, 0x,
+   0x, 0x, 0x, 0x,
+   0x, 0x, 0x, 0x,
+   0x, 0x, 0x, 0x,
+   0x, 0x, 0x, 0x,
+};
+
+/* Packet types for GTPU */
+static const u32 ice_ptypes_gtpu[] = {
+   0x, 0x, 0x, 0x,
+   0x, 0x, 0x, 0x,
+   0x, 0x, 0x7800, 0x,
+   0x, 0x, 0x, 0x,
+   0x, 0x, 0x, 0x,
+   0x, 0x, 0x, 0x,
+   0x, 0x, 0x, 0x,
+   0x, 0x, 0x, 0x,
+};
+
 /* Manage parameters and info. used during the creation of a flow profile */
 struct ice_flow_prof_params {
enum ice_block blk;
@@ -317,10 +372,13 @@ static bool ice_is_pow2(u64 val)
 #define ICE_FLOW_SEG_HDRS_L2_MASK  \
(ICE_FLOW_SEG_HDR_ETH | ICE_FLOW_SEG_HDR_VLAN)
 #define ICE_FLOW_SEG_HDRS_L3_MASK  \
-   (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_ARP)
+   (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6 | \
+ICE_FLOW_SEG_HDR_ARP | ICE_FLOW_SEG_HDR_PPPOE)
 #define ICE_FLOW_SEG_HDRS_L4_MASK  \
(ICE_FLOW_SEG_HDR_ICMP | ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_UDP | \
-ICE_FLOW_SEG_HDR_SCTP)
+ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_GTPC | \
+ICE_FLOW_SEG_HDR_GTPC_TEID | ICE_FLOW_SEG_HDR_GTPU_IP | \
+ICE_FLOW_SEG_HDR_GTPU_UP | ICE_FLOW_SEG_HDR_GTPU_DWN)
 
 /**
  * ice_flow_val_hdrs - validates packet segments for valid protocol headers
@@ -431,21 +489,18 @@ ice_flow_proc_seg_hdrs(struct ice_flow_prof_params 

[dpdk-dev] [PATCH 26/63] net/ice/base: add locks for flow functions

[Qi Zhang]

Wrap functions to search for flow profiles, add and remove RSS
configurations with flow profile locks. This is to ensure that if
several VFs and PFs are disabled at the same time functions that access
the flow profile lists are thread safe.

Signed-off-by: Vignesh Sridhar 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_flow.c | 29 +
 1 file changed, 17 insertions(+), 12 deletions(-)

diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index 0f52b3379..9e93a1078 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -949,8 +949,9 @@ ice_flow_find_prof_conds(struct ice_hw *hw, enum ice_block 
blk,
 enum ice_flow_dir dir, struct ice_flow_seg_info *segs,
 u8 segs_cnt, u16 vsi_handle, u32 conds)
 {
-   struct ice_flow_prof *p;
+   struct ice_flow_prof *p, *prof = NULL;
 
+   ice_acquire_lock(&hw->fl_profs_locks[blk]);
LIST_FOR_EACH_ENTRY(p, &hw->fl_profs[blk], ice_flow_prof, l_entry) {
if ((p->dir == dir || conds & ICE_FLOW_FIND_PROF_NOT_CHK_DIR) &&
segs_cnt && segs_cnt == p->segs_cnt) {
@@ -972,12 +973,15 @@ ice_flow_find_prof_conds(struct ice_hw *hw, enum 
ice_block blk,
break;
 
/* A match is found if all segments are matched */
-   if (i == segs_cnt)
-   return p;
+   if (i == segs_cnt) {
+   prof = p;
+   break;
+   }
}
}
+   ice_release_lock(&hw->fl_profs_locks[blk]);
 
-   return NULL;
+   return prof;
 }
 
 /**
@@ -994,10 +998,8 @@ ice_flow_find_prof(struct ice_hw *hw, enum ice_block blk, 
enum ice_flow_dir dir,
 {
struct ice_flow_prof *p;
 
-   ice_acquire_lock(&hw->fl_profs_locks[blk]);
p = ice_flow_find_prof_conds(hw, blk, dir, segs, segs_cnt,
 ICE_MAX_VSI, ICE_FLOW_FIND_PROF_CHK_FLDS);
-   ice_release_lock(&hw->fl_profs_locks[blk]);
 
return p ? p->id : ICE_FLOW_PROF_ID_INVAL;
 }
@@ -1497,9 +1499,12 @@ ice_flow_add_entry(struct ice_hw *hw, enum ice_block 
blk, u64 prof_id,
goto out;
}
 
-   ice_acquire_lock(&prof->entries_lock);
-   LIST_ADD(&e->l_entry, &prof->entries);
-   ice_release_lock(&prof->entries_lock);
+   if (blk != ICE_BLK_ACL) {
+   /* ACL will handle the entry management */
+   ice_acquire_lock(&prof->entries_lock);
+   LIST_ADD(&e->l_entry, &prof->entries);
+   ice_release_lock(&prof->entries_lock);
+   }
 
*entry_h = ICE_FLOW_ENTRY_HNDL(e);
 
@@ -1930,7 +1935,7 @@ ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, 
u64 hashed_flds,
 
/* Remove profile if it has no VSIs associated */
if (!ice_is_any_bit_set(prof->vsis, ICE_MAX_VSI)) {
-   status = ice_flow_rem_prof_sync(hw, blk, prof);
+   status = ice_flow_rem_prof(hw, blk, prof->id);
if (status)
goto exit;
}
@@ -1963,7 +1968,7 @@ ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, 
u64 hashed_flds,
 * be removed.
 */
if (status) {
-   ice_flow_rem_prof_sync(hw, blk, prof);
+   ice_flow_rem_prof(hw, blk, prof->id);
goto exit;
}
 
@@ -2047,7 +2052,7 @@ ice_rem_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, 
u64 hashed_flds,
ice_rem_rss_list(hw, vsi_handle, prof);
 
if (!ice_is_any_bit_set(prof->vsis, ICE_MAX_VSI))
-   status = ice_flow_rem_prof_sync(hw, blk, prof);
+   status = ice_flow_rem_prof(hw, blk, prof->id);
 
 out:
ice_free(hw, segs);
-- 
2.13.6

[dpdk-dev] [PATCH 28/63] net/ice/base: move function declaration

[Qi Zhang]

Improve code orgnization, move declaration of ice_cfg_tc_nod_bw_alloc and
ice_cfg_rl_burst_size from ice_common.h to ice_nvm.h.

Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_common.h | 8 
 drivers/net/ice/base/ice_nvm.h| 4 
 drivers/net/ice/base/ice_sched.h  | 4 
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/net/ice/base/ice_common.h 
b/drivers/net/ice/base/ice_common.h
index a55f7eeba..67adc9c59 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -50,10 +50,6 @@ enum ice_status
 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
  struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
  enum ice_adminq_opc opc, struct ice_sq_cd *cd);
-enum ice_status ice_init_nvm(struct ice_hw *hw);
-enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data);
-enum ice_status
-ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data);
 enum ice_status
 ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
struct ice_aq_desc *desc, void *buf, u16 buf_size,
@@ -201,10 +197,6 @@ enum ice_status
 ice_sched_replay_q_bw(struct ice_port_info *pi, struct ice_q_ctx *q_ctx);
 struct ice_q_ctx *
 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle);
-enum ice_status
-ice_cfg_tc_node_bw_alloc(struct ice_port_info *pi, u8 tc,
-enum ice_rl_type rl_type, u8 bw_alloc);
-enum ice_status ice_cfg_rl_burst_size(struct ice_hw *hw, u32 bytes);
 void
 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
  u64 *prev_stat, u64 *cur_stat);
diff --git a/drivers/net/ice/base/ice_nvm.h b/drivers/net/ice/base/ice_nvm.h
index da76b2674..d5b7b2d19 100644
--- a/drivers/net/ice/base/ice_nvm.h
+++ b/drivers/net/ice/base/ice_nvm.h
@@ -84,4 +84,8 @@ ice_nvm_access_get_features(struct ice_nvm_access_cmd *cmd,
 enum ice_status
 ice_handle_nvm_access(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
  union ice_nvm_access_data *data);
+enum ice_status ice_init_nvm(struct ice_hw *hw);
+enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data);
+enum ice_status
+ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data);
 #endif /* _ICE_NVM_H_ */
diff --git a/drivers/net/ice/base/ice_sched.h b/drivers/net/ice/base/ice_sched.h
index 932ae075f..d6b467477 100644
--- a/drivers/net/ice/base/ice_sched.h
+++ b/drivers/net/ice/base/ice_sched.h
@@ -185,4 +185,8 @@ ice_sched_set_agg_bw_shared_lmt(struct ice_port_info *pi, 
u32 agg_id, u32 bw);
 enum ice_status
 ice_sched_cfg_sibl_node_prio(struct ice_port_info *pi,
 struct ice_sched_node *node, u8 priority);
+enum ice_status
+ice_cfg_tc_node_bw_alloc(struct ice_port_info *pi, u8 tc,
+enum ice_rl_type rl_type, u8 bw_alloc);
+enum ice_status ice_cfg_rl_burst_size(struct ice_hw *hw, u32 bytes);
 #endif /* _ICE_SCHED_H_ */
-- 
2.13.6

[dpdk-dev] [PATCH 29/63] net/ice/base: add 16-byte Flex Rx Descriptor

[Qi Zhang]

Add 16-byte Flex RX descriptor structure definition.

Signed-off-by: Dan Nowlin 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_lan_tx_rx.h | 28 ++--
 1 file changed, 26 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h 
b/drivers/net/ice/base/ice_lan_tx_rx.h
index 2cba6bc1e..7c3927ac2 100644
--- a/drivers/net/ice/base/ice_lan_tx_rx.h
+++ b/drivers/net/ice/base/ice_lan_tx_rx.h
@@ -373,10 +373,34 @@ enum ice_rx_prog_status_desc_error_bits {
ICE_RX_PROG_STATUS_DESC_NO_FD_ENTRY_S   = 1,
 };
 
-/* Rx Flex Descriptor
- * This descriptor is used instead of the legacy version descriptor when
+/* Rx Flex Descriptors
+ * These descriptors are used instead of the legacy version descriptors when
  * ice_rlan_ctx.adv_desc is set
  */
+union ice_16b_rx_flex_desc {
+   struct {
+   __le64 pkt_addr; /* Packet buffer address */
+   __le64 hdr_addr; /* Header buffer address */
+/* bit 0 of hdr_addr is DD bit */
+   } read;
+   struct {
+   /* Qword 0 */
+   u8 rxdid; /* descriptor builder profile ID */
+   u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */
+   __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
+   __le16 pkt_len; /* [15:14] are reserved */
+   __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */
+   /* sph=[11:11] */
+   /* ff1/ext=[15:12] */
+
+   /* Qword 1 */
+   __le16 status_error0;
+   __le16 l2tag1;
+   __le16 flex_meta0;
+   __le16 flex_meta1;
+   } wb; /* writeback */
+};
+
 union ice_32b_rx_flex_desc {
struct {
__le64 pkt_addr; /* Packet buffer address */
-- 
2.13.6

[dpdk-dev] [PATCH 32/63] net/ice/base: add more opcode and macros

[Qi Zhang]

Add more opcode and macros according to hardware spec.

1. Add opcode for the NVM Update EMPR command.
2. Add opcode for NVM save factory settings
3. Add opcode for NVM Write/Write Activate calls
4. Add loopback reporting to get link response macros
5. Add link event defines macros

Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_adminq_cmd.h | 28 +++-
 1 file changed, 23 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ice/base/ice_adminq_cmd.h 
b/drivers/net/ice/base/ice_adminq_cmd.h
index cc42180ea..b9e3bd5fa 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -1575,7 +1575,12 @@ struct ice_aqc_get_link_status_data {
 #define ICE_AQ_LINK_TX_ACTIVE  0
 #define ICE_AQ_LINK_TX_DRAINED 1
 #define ICE_AQ_LINK_TX_FLUSHED 3
-   u8 reserved2;
+   u8 lb_status;
+#define ICE_AQ_LINK_LB_PHY_LCL BIT(0)
+#define ICE_AQ_LINK_LB_PHY_RMT BIT(1)
+#define ICE_AQ_LINK_LB_MAC_LCL BIT(2)
+#define ICE_AQ_LINK_LB_PHY_IDX_S   3
+#define ICE_AQ_LINK_LB_PHY_IDX_M   (0x7 << ICE_AQ_LB_PHY_IDX_S)
__le16 max_frame_size;
u8 cfg;
 #define ICE_AQ_LINK_25G_KR_FEC_EN  BIT(0)
@@ -1631,6 +1636,8 @@ struct ice_aqc_set_event_mask {
 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7)
 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8)
 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDEDBIT(9)
+#define ICE_AQ_LINK_EVENT_TOPO_CONFLICTBIT(10)
+#define ICE_AQ_LINK_EVENT_MEDIA_CONFLICT   BIT(11)
u8  reserved1[6];
 };
 
@@ -1690,20 +1697,26 @@ struct ice_aqc_sff_eeprom {
 
 /* NVM Read command (indirect 0x0701)
  * NVM Erase commands (direct 0x0702)
- * NVM Update commands (indirect 0x0703)
+ * NVM Write commands (indirect 0x0703)
+ * NVM Write Activate commands (direct 0x0707)
+ * NVM Shadow RAM Dump commands (direct 0x0707)
  */
 struct ice_aqc_nvm {
__le16 offset_low;
u8 offset_high;
u8 cmd_flags;
 #define ICE_AQC_NVM_LAST_CMD   BIT(0)
-#define ICE_AQC_NVM_PCIR_REQ   BIT(0)  /* Used by NVM Update reply */
-#define ICE_AQC_NVM_PRESERVATION_S 1
+#define ICE_AQC_NVM_PCIR_REQ   BIT(0)  /* Used by NVM Write reply */
+#define ICE_AQC_NVM_PRESERVATION_S 1 /* Used by NVM Write Activate only */
 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S)
 #define ICE_AQC_NVM_NO_PRESERVATION(0 << ICE_AQC_NVM_PRESERVATION_S)
 #define ICE_AQC_NVM_PRESERVE_ALL   BIT(1)
 #define ICE_AQC_NVM_FACTORY_DEFAULT(2 << ICE_AQC_NVM_PRESERVATION_S)
 #define ICE_AQC_NVM_PRESERVE_SELECTED  (3 << ICE_AQC_NVM_PRESERVATION_S)
+#define ICE_AQC_NVM_ACTIV_SEL_NVM  BIT(3) /* Write Activate/SR Dump only */
+#define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4)
+#define ICE_AQC_NVM_ACTIV_SEL_NETLIST  BIT(5)
+#define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3)
 #define ICE_AQC_NVM_FLASH_ONLY BIT(7)
__le16 module_typeid;
__le16 length;
@@ -2292,6 +2305,7 @@ struct ice_aq_desc {
struct ice_aqc_set_mac_cfg set_mac_cfg;
struct ice_aqc_set_event_mask set_event_mask;
struct ice_aqc_get_link_status get_link_status;
+   struct ice_aqc_event_lan_overflow lan_overflow;
} params;
 };
 
@@ -2465,10 +2479,14 @@ enum ice_adminq_opc {
/* NVM commands */
ice_aqc_opc_nvm_read= 0x0701,
ice_aqc_opc_nvm_erase   = 0x0702,
-   ice_aqc_opc_nvm_update  = 0x0703,
+   ice_aqc_opc_nvm_write   = 0x0703,
ice_aqc_opc_nvm_cfg_read= 0x0704,
ice_aqc_opc_nvm_cfg_write   = 0x0705,
ice_aqc_opc_nvm_checksum= 0x0706,
+   ice_aqc_opc_nvm_write_activate  = 0x0707,
+   ice_aqc_opc_nvm_sr_dump = 0x0707,
+   ice_aqc_opc_nvm_save_factory_settings   = 0x0708,
+   ice_aqc_opc_nvm_update_empr = 0x0709,
 
/* LLDP commands */
ice_aqc_opc_lldp_get_mib= 0x0A00,
-- 
2.13.6

[dpdk-dev] [PATCH 33/63] net/ice/base: set status when global cfg lock is unavailable

[Qi Zhang]

To download the DDP file to the device, a PF first has to grab the
global configuration lock. When a PF can't grab this lock, set
hw->pkg_dwnld_status to ICE_AQ_RC_EEXIST.

Signed-off-by: Anirudh Venkataramanan 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_flex_pipe.c | 15 ++-
 drivers/net/ice/base/ice_type.h  |  2 ++
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ice/base/ice_flex_pipe.c 
b/drivers/net/ice/base/ice_flex_pipe.c
index 7daaf10b0..f8dd1c4d1 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -961,9 +961,19 @@ ice_dwnld_cfg_bufs(struct ice_hw *hw, struct ice_buf 
*bufs, u32 count)
if (LE32_TO_CPU(bh->section_entry[0].type) & ICE_METADATA_BUF)
return ICE_SUCCESS;
 
+   /* reset pkg_dwnld_status in case this function is called in the
+* reset/rebuild flow
+*/
+   hw->pkg_dwnld_status = ICE_AQ_RC_OK;
+
status = ice_acquire_global_cfg_lock(hw, ICE_RES_WRITE);
-   if (status)
+   if (status) {
+   if (status == ICE_ERR_AQ_NO_WORK)
+   hw->pkg_dwnld_status = ICE_AQ_RC_EEXIST;
+   else
+   hw->pkg_dwnld_status = hw->adminq.sq_last_status;
return status;
+   }
 
for (i = 0; i < count; i++) {
bool last = ((i + 1) == count);
@@ -986,6 +996,9 @@ ice_dwnld_cfg_bufs(struct ice_hw *hw, struct ice_buf *bufs, 
u32 count)
 
status = ice_aq_download_pkg(hw, bh, ICE_PKG_BUF_SIZE, last,
 &offset, &info, NULL);
+
+   /* Save AQ status from download package */
+   hw->pkg_dwnld_status = hw->adminq.sq_last_status;
if (status) {
ice_debug(hw, ICE_DBG_PKG,
  "Pkg download failed: err %d off %d inf %d\n",
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index dc041760d..541e29851 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -775,6 +775,8 @@ struct ice_hw {
u8 active_pkg_name[ICE_PKG_NAME_SIZE];
u8 active_pkg_in_nvm;
 
+   enum ice_aq_err pkg_dwnld_status;
+
/* Driver's package ver - (from the Metadata seg) */
struct ice_pkg_ver pkg_ver;
u8 pkg_name[ICE_PKG_NAME_SIZE];
-- 
2.13.6

[dpdk-dev] [PATCH 30/63] net/ice/base: add 32-byte Flex Rx Desc for Comms package

[Qi Zhang]

Add 32-byte Flex RX Descriptor structure definition to match the
Comms package's design.

Signed-off-by: Junfeng Guo 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_lan_tx_rx.h | 40 
 1 file changed, 40 insertions(+)

diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h 
b/drivers/net/ice/base/ice_lan_tx_rx.h
index 7c3927ac2..e1c2f0d01 100644
--- a/drivers/net/ice/base/ice_lan_tx_rx.h
+++ b/drivers/net/ice/base/ice_lan_tx_rx.h
@@ -619,6 +619,46 @@ struct ice_32b_rx_flex_desc_nic_2 {
} flex_ts;
 };
 
+/* Rx Flex Descriptor for Comms Package Profile
+ * RxDID Profile ID 16-21
+ * Flex-field 0: RSS hash lower 16-bits
+ * Flex-field 1: RSS hash upper 16-bits
+ * Flex-field 2: Flow ID lower 16-bits
+ * Flex-field 3: Flow ID upper 16-bits
+ * Flex-field 4: AUX0
+ * Flex-field 5: AUX1
+ */
+struct ice_32b_rx_flex_desc_comms {
+   /* Qword 0 */
+   u8 rxdid;
+   u8 mir_id_umb_cast;
+   __le16 ptype_flexi_flags0;
+   __le16 pkt_len;
+   __le16 hdr_len_sph_flex_flags1;
+
+   /* Qword 1 */
+   __le16 status_error0;
+   __le16 l2tag1;
+   __le32 rss_hash;
+
+   /* Qword 2 */
+   __le16 status_error1;
+   u8 flexi_flags2;
+   u8 ts_low;
+   __le16 l2tag2_1st;
+   __le16 l2tag2_2nd;
+
+   /* Qword 3 */
+   __le32 flow_id;
+   union {
+   struct {
+   __le16 aux0;
+   __le16 aux1;
+   } flex;
+   __le32 ts_high;
+   } flex_ts;
+};
+
 /* Receive Flex Descriptor profile IDs: There are a total
  * of 64 profiles where profile IDs 0/1 are for legacy; and
  * profiles 2-63 are flex profiles that can be programmed
-- 
2.13.6

[dpdk-dev] [PATCH 31/63] net/ice/base: update flag bits to current specification

[Qi Zhang]

Currently the VLAN ice_flg64_bits are off by 1. Fix this by
setting the ICE_FLG_EVLAN_x8100 flag to 14, which also updates
ICE_FLG_EVLAN_x9100 to 15 and ICE_FLG_VLAN_x8100 to 16.

Signed-off-by: Brett Creeley 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_lan_tx_rx.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h 
b/drivers/net/ice/base/ice_lan_tx_rx.h
index e1c2f0d01..e77d4bf50 100644
--- a/drivers/net/ice/base/ice_lan_tx_rx.h
+++ b/drivers/net/ice/base/ice_lan_tx_rx.h
@@ -737,7 +737,7 @@ enum ice_flg64_bits {
ICE_FLG_PKT_DSI = 0,
/* If there is a 1 in this bit position then that means Rx packet */
ICE_FLG_PKT_DIR = 4,
-   ICE_FLG_EVLAN_x8100 = 15,
+   ICE_FLG_EVLAN_x8100 = 14,
ICE_FLG_EVLAN_x9100,
ICE_FLG_VLAN_x8100,
ICE_FLG_TNL_MAC = 22,
-- 
2.13.6

[dpdk-dev] [PATCH 36/63] net/ice/base: add support for not locking sideband queue

[Qi Zhang]

For certain PTP clock adjustments, there is a use case for locking the
sideband queue at a higher level and performing an atomic series of
operations while the sideband queue is locked.  To accommodate this use
case, split ice_sw_send_cmd() into a version that takes the lock and a
version that does not.

Signed-off-by: Ben Shelton 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_controlq.c | 40 +++--
 1 file changed, 34 insertions(+), 6 deletions(-)

diff --git a/drivers/net/ice/base/ice_controlq.c 
b/drivers/net/ice/base/ice_controlq.c
index 8070bb9a7..70a50bff4 100644
--- a/drivers/net/ice/base/ice_controlq.c
+++ b/drivers/net/ice/base/ice_controlq.c
@@ -859,7 +859,7 @@ static bool ice_sq_done(struct ice_hw *hw, struct 
ice_ctl_q_info *cq)
 }
 
 /**
- * ice_sq_send_cmd - send command to Control Queue (ATQ)
+ * ice_sq_send_cmd_nolock - send command to Control Queue (ATQ)
  * @hw: pointer to the HW struct
  * @cq: pointer to the specific Control queue
  * @desc: prefilled descriptor describing the command (non DMA mem)
@@ -870,10 +870,10 @@ static bool ice_sq_done(struct ice_hw *hw, struct 
ice_ctl_q_info *cq)
  * This is the main send command routine for the ATQ. It runs the queue,
  * cleans the queue, etc.
  */
-enum ice_status
-ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
-   struct ice_aq_desc *desc, void *buf, u16 buf_size,
-   struct ice_sq_cd *cd)
+static enum ice_status
+ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,
+  struct ice_aq_desc *desc, void *buf, u16 buf_size,
+  struct ice_sq_cd *cd)
 {
struct ice_dma_mem *dma_buf = NULL;
struct ice_aq_desc *desc_on_ring;
@@ -887,7 +887,6 @@ ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info 
*cq,
/* if reset is in progress return a soft error */
if (hw->reset_ongoing)
return ICE_ERR_RESET_ONGOING;
-   ice_acquire_lock(&cq->sq_lock);
 
cq->sq_last_status = ICE_AQ_RC_OK;
 
@@ -1040,7 +1039,36 @@ ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info 
*cq,
}
 
 sq_send_command_error:
+   return status;
+}
+
+/**
+ * ice_sq_send_cmd - send command to Control Queue (ATQ)
+ * @hw: pointer to the HW struct
+ * @cq: pointer to the specific Control queue
+ * @desc: prefilled descriptor describing the command (non DMA mem)
+ * @buf: buffer to use for indirect commands (or NULL for direct commands)
+ * @buf_size: size of buffer for indirect commands (or 0 for direct commands)
+ * @cd: pointer to command details structure
+ *
+ * This is the main send command routine for the ATQ. It runs the queue,
+ * cleans the queue, etc.
+ */
+enum ice_status
+ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
+   struct ice_aq_desc *desc, void *buf, u16 buf_size,
+   struct ice_sq_cd *cd)
+{
+   enum ice_status status = ICE_SUCCESS;
+
+   /* if reset is in progress return a soft error */
+   if (hw->reset_ongoing)
+   return ICE_ERR_RESET_ONGOING;
+
+   ice_acquire_lock(&cq->sq_lock);
+   status = ice_sq_send_cmd_nolock(hw, cq, desc, buf, buf_size, cd);
ice_release_lock(&cq->sq_lock);
+
return status;
 }
 
-- 
2.13.6

[dpdk-dev] [PATCH 37/63] net/ice/base: associate recipes by profile type

[Qi Zhang]

Change recipe to profile association logic to determine the profile type
to determine if a profile is compatible with the rule being added.

Signed-off-by: Dan Nowlin 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_flex_pipe.c | 87 ++--
 drivers/net/ice/base/ice_flex_pipe.h |  5 +-
 drivers/net/ice/base/ice_flex_type.h |  8 +++
 drivers/net/ice/base/ice_protocol_type.h |  5 +-
 drivers/net/ice/base/ice_switch.c| 54 ++--
 5 files changed, 151 insertions(+), 8 deletions(-)

diff --git a/drivers/net/ice/base/ice_flex_pipe.c 
b/drivers/net/ice/base/ice_flex_pipe.c
index f8dd1c4d1..3beb4d961 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -1506,10 +1506,83 @@ ice_sw_fv_handler(u32 sect_type, void *section, u32 
index, u32 *offset)
 }
 
 /**
+ * ice_get_sw_prof_type - determine switch profile type
+ * @hw: pointer to the HW structure
+ * @fv: pointer to the switch field vector
+ */
+static enum ice_prof_type
+ice_get_sw_prof_type(struct ice_hw *hw, struct ice_fv *fv)
+{
+   u16 i;
+
+   for (i = 0; i < hw->blk[ICE_BLK_SW].es.fvw; i++) {
+   /* UDP tunnel will have UDP_OF protocol ID and VNI offset */
+   if (fv->ew[i].prot_id == (u8)ICE_PROT_UDP_OF &&
+   fv->ew[i].off == ICE_VNI_OFFSET)
+   return ICE_PROF_TUN_UDP;
+
+   /* GRE tunnel will have GRE protocol */
+   if (fv->ew[i].prot_id == (u8)ICE_PROT_GRE_OF)
+   return ICE_PROF_TUN_GRE;
+
+   /* PPPOE tunnel will have PPPOE protocol */
+   if (fv->ew[i].prot_id == (u8)ICE_PROT_PPPOE)
+   return ICE_PROF_TUN_PPPOE;
+   }
+
+   return ICE_PROF_NON_TUN;
+}
+
+/**
+ * ice_get_sw_fv_bitmap - Get switch field vector bitmap based on profile type
+ * @hw: pointer to hardware structure
+ * @type: type of profiles requested
+ * @bm: pointer to memory for returning the bitmap of field vectors
+ */
+void
+ice_get_sw_fv_bitmap(struct ice_hw *hw, enum ice_prof_type type,
+ice_bitmap_t *bm)
+{
+   struct ice_pkg_enum state;
+   struct ice_seg *ice_seg;
+   struct ice_fv *fv;
+
+   if (type == ICE_PROF_ALL) {
+   u16 i;
+
+   for (i = 0; i < ICE_MAX_NUM_PROFILES; i++)
+   ice_set_bit(i, bm);
+   return;
+   }
+
+   ice_zero_bitmap(bm, ICE_MAX_NUM_PROFILES);
+
+   ice_seg = hw->seg;
+   do {
+   enum ice_prof_type prof_type;
+   u32 offset;
+
+   fv = (struct ice_fv *)
+   ice_pkg_enum_entry(ice_seg, &state, ICE_SID_FLD_VEC_SW,
+  &offset, ice_sw_fv_handler);
+   ice_seg = NULL;
+
+   if (fv) {
+   /* Determine field vector type */
+   prof_type = ice_get_sw_prof_type(hw, fv);
+
+   if (type & prof_type)
+   ice_set_bit((u16)offset, bm);
+   }
+   } while (fv);
+}
+
+/**
  * ice_get_sw_fv_list
  * @hw: pointer to the HW structure
  * @prot_ids: field vector to search for with a given protocol ID
  * @ids_cnt: lookup/protocol count
+ * @bm: bitmap of field vectors to consider
  * @fv_list: Head of a list
  *
  * Finds all the field vector entries from switch block that contain
@@ -1521,7 +1594,7 @@ ice_sw_fv_handler(u32 sect_type, void *section, u32 
index, u32 *offset)
  */
 enum ice_status
 ice_get_sw_fv_list(struct ice_hw *hw, u16 *prot_ids, u8 ids_cnt,
-  struct LIST_HEAD_TYPE *fv_list)
+  ice_bitmap_t *bm, struct LIST_HEAD_TYPE *fv_list)
 {
struct ice_sw_fv_list_entry *fvl;
struct ice_sw_fv_list_entry *tmp;
@@ -1540,8 +1613,17 @@ ice_get_sw_fv_list(struct ice_hw *hw, u16 *prot_ids, u8 
ids_cnt,
fv = (struct ice_fv *)
ice_pkg_enum_entry(ice_seg, &state, ICE_SID_FLD_VEC_SW,
   &offset, ice_sw_fv_handler);
+   if (!fv)
+   break;
+   ice_seg = NULL;
 
-   for (i = 0; i < ids_cnt && fv; i++) {
+   /* If field vector is not in the bitmap list, then skip this
+* profile.
+*/
+   if (!ice_is_bit_set(bm, (u16)offset))
+   continue;
+
+   for (i = 0; i < ids_cnt; i++) {
int j;
 
/* This code assumes that if a switch field vector line
@@ -1565,7 +1647,6 @@ ice_get_sw_fv_list(struct ice_hw *hw, u16 *prot_ids, u8 
ids_cnt,
break;
}
}
-   ice_seg = NULL;
} while (fv);
if (LIST_EMPTY(fv_list))
return ICE_ERR_CFG;
diff -

[dpdk-dev] [PATCH 34/63] net/ice/base: initialize driver NVM data earlier

[Qi Zhang]

The driver detects and warns about FW rollback mode before getting the NVM
version (through ice_init_nvm) which results in "0.00 0x0 0.0.0" being
printed. Fix this by calling ice_init_nvm earlier.

This could have been fixed by moving ice_print_rollback_msg as well, but
it made more sense to move ice_init_nvm closer to the flow that gets the
FW version information (i.e. control queue init flow).

Signed-off-by: Anirudh Venkataramanan 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_common.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ice/base/ice_common.c 
b/drivers/net/ice/base/ice_common.c
index 36434ee42..e19ce733c 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -759,10 +759,13 @@ enum ice_status ice_init_hw(struct ice_hw *hw)
if (status)
goto err_unroll_cqinit;
 
+   status = ice_init_nvm(hw);
+   if (status)
+   goto err_unroll_cqinit;
+
if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK)
ice_print_rollback_msg(hw);
 
-
status = ice_clear_pf_cfg(hw);
if (status)
goto err_unroll_cqinit;
@@ -773,9 +776,6 @@ enum ice_status ice_init_hw(struct ice_hw *hw)
 
ice_clear_pxe_mode(hw);
 
-   status = ice_init_nvm(hw);
-   if (status)
-   goto err_unroll_cqinit;
 
status = ice_get_caps(hw);
if (status)
-- 
2.13.6

[dpdk-dev] [PATCH 35/63] net/ice/base: add function to configure Tx AQ command

[Qi Zhang]

This function is needed by the driver to move PSM leaf nodes to a new
parent.

Additionally, add struct ice_aqc_move_txqs to struct ice_aq_desc so
driver code can access it.

Signed-off-by: Ben Shelton 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_adminq_cmd.h |  1 +
 drivers/net/ice/base/ice_common.c | 71 +++
 drivers/net/ice/base/ice_common.h |  6 +++
 3 files changed, 78 insertions(+)

diff --git a/drivers/net/ice/base/ice_adminq_cmd.h 
b/drivers/net/ice/base/ice_adminq_cmd.h
index b9e3bd5fa..9a063592f 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -2292,6 +2292,7 @@ struct ice_aq_desc {
struct ice_aqc_clear_fd_table clear_fd_table;
struct ice_aqc_add_txqs add_txqs;
struct ice_aqc_dis_txqs dis_txqs;
+   struct ice_aqc_move_txqs move_txqs;
struct ice_aqc_txqs_cleanup txqs_cleanup;
struct ice_aqc_add_get_update_free_vsi vsi_cmd;
struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;
diff --git a/drivers/net/ice/base/ice_common.c 
b/drivers/net/ice/base/ice_common.c
index e19ce733c..c2d4f1f05 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -3415,6 +3415,77 @@ ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
return status;
 }
 
+/**
+ * ice_aq_move_recfg_lan_txq
+ * @hw: pointer to the hardware structure
+ * @num_qs: number of queues to move/reconfigure
+ * @is_move: true if this operation involves node movement
+ * @is_tc_change: true if this operation involves a TC change
+ * @subseq_call: true if this operation is a subsequent call
+ * @flush_pipe: on timeout, true to flush pipe, false to return EAGAIN
+ * @timeout: timeout in units of 100 usec (valid values 0-50)
+ * @blocked_cgds: out param, bitmap of CGDs that timed out if returning EAGAIN
+ * @buf: struct containing src/dest TEID and per-queue info
+ * @buf_size: size of buffer for indirect command
+ * @txqs_moved: out param, number of queues successfully moved
+ * @cd: pointer to command details structure or NULL
+ *
+ * Move / Reconfigure Tx LAN queues (0x0C32)
+ */
+enum ice_status
+ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move,
+ bool is_tc_change, bool subseq_call, bool flush_pipe,
+ u8 timeout, u32 *blocked_cgds,
+ struct ice_aqc_move_txqs_data *buf, u16 buf_size,
+ u8 *txqs_moved, struct ice_sq_cd *cd)
+{
+   struct ice_aqc_move_txqs *cmd;
+   struct ice_aq_desc desc;
+   enum ice_status status;
+
+   cmd = &desc.params.move_txqs;
+   ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_move_recfg_txqs);
+
+#define ICE_LAN_TXQ_MOVE_TIMEOUT_MAX 50
+   if (timeout > ICE_LAN_TXQ_MOVE_TIMEOUT_MAX)
+   return ICE_ERR_PARAM;
+
+   if (is_tc_change && !flush_pipe && !blocked_cgds)
+   return ICE_ERR_PARAM;
+
+   if (!is_move && !is_tc_change)
+   return ICE_ERR_PARAM;
+
+   desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
+
+   if (is_move)
+   cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_MOVE;
+
+   if (is_tc_change)
+   cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_TC_CHANGE;
+
+   if (subseq_call)
+   cmd->cmd_type |= ICE_AQC_Q_CMD_SUBSEQ_CALL;
+
+   if (flush_pipe)
+   cmd->cmd_type |= ICE_AQC_Q_CMD_FLUSH_PIPE;
+
+   cmd->num_qs = num_qs;
+   cmd->timeout = ((timeout << ICE_AQC_Q_CMD_TIMEOUT_S) &
+   ICE_AQC_Q_CMD_TIMEOUT_M);
+
+   status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
+
+   if (!status && txqs_moved)
+   *txqs_moved = cmd->num_qs;
+
+   if (hw->adminq.sq_last_status == ICE_AQ_RC_EAGAIN &&
+   is_tc_change && !flush_pipe)
+   *blocked_cgds = LE32_TO_CPU(cmd->blocked_cgds);
+
+   return status;
+}
+
 
 /* End of FW Admin Queue command wrappers */
 
diff --git a/drivers/net/ice/base/ice_common.h 
b/drivers/net/ice/base/ice_common.h
index 67adc9c59..c42c58670 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -106,6 +106,12 @@ enum ice_status
 ice_aq_add_lan_txq(struct ice_hw *hw, u8 count,
   struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
   struct ice_sq_cd *cd);
+enum ice_status
+ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move,
+ bool is_tc_change, bool subseq_call, bool flush_pipe,
+ u8 timeout, u32 *blocked_cgds,
+ struct ice_aqc_move_txqs_data *buf, u16 buf_size,
+ u8 *txqs_moved, struct ice_sq_cd *cd);
 
 bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq);
 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloa

[dpdk-dev] [PATCH 40/63] net/ice/base: improve switch chained recipe

[Qi Zhang]

When updating switch database with chained recipes from
firmware, where a null pointer derefence was occurring due to looking
into a sub-recipe entry which is not filled in.

Signed-off-by: Dan Nowlin 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_protocol_type.h |   2 +
 drivers/net/ice/base/ice_switch.c| 164 ---
 2 files changed, 108 insertions(+), 58 deletions(-)

diff --git a/drivers/net/ice/base/ice_protocol_type.h 
b/drivers/net/ice/base/ice_protocol_type.h
index ee40bdc30..91f56f3fa 100644
--- a/drivers/net/ice/base/ice_protocol_type.h
+++ b/drivers/net/ice/base/ice_protocol_type.h
@@ -135,6 +135,8 @@ enum ice_prot_id {
 #define ICE_GRE_OF_HW  64 /* NVGRE */
 #define ICE_META_DATA_ID_HW 255 /* this is used for tunnel type */
 
+#define ICE_MDID_SIZE 2
+#define ICE_TUN_FLAG_MDID 21
 #define ICE_TUN_FLAG_MASK 0xFF
 #define ICE_TUN_FLAG_FV_IND 2
 
diff --git a/drivers/net/ice/base/ice_switch.c 
b/drivers/net/ice/base/ice_switch.c
index 65ec1bb93..b4f50e0e5 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -455,29 +455,24 @@ static void ice_get_recp_to_prof_map(struct ice_hw *hw);
 static void ice_collect_result_idx(struct ice_aqc_recipe_data_elem *buf,
   struct ice_sw_recipe *recp)
 {
-   if (buf->content.result_indx & ICE_AQ_RECIPE_ID_IS_ROOT)
+   if (buf->content.result_indx & ICE_AQ_RECIPE_RESULT_EN)
ice_set_bit(buf->content.result_indx &
-   ~ICE_AQ_RECIPE_ID_IS_ROOT, recp->res_idxs);
+   ~ICE_AQ_RECIPE_RESULT_EN, recp->res_idxs);
 }
 
 /**
- * ice_collect_result_idx_from_bitmap - copy result index values using bitmap
- * @hw: pointer to hardware structure
- * @recp: the recipe struct to copy data into
+ * ice_init_possible_res_bm - initialize possible result bitmap
+ * @pos_result_bm: pointer to the bitmap to initialize
  */
-static void
-ice_collect_result_idx_from_bitmap(struct ice_hw *hw,
-  struct ice_sw_recipe *recp)
+static void ice_init_possible_res_bm(ice_bitmap_t *pos_result_bm)
 {
-   u16 bit = 0;
+   u16 bit;
 
-   while (ICE_MAX_NUM_RECIPES >
-  (bit = ice_find_next_bit(recp->r_bitmap, ICE_MAX_NUM_RECIPES,
-   bit))) {
-   ice_collect_result_idx(hw->switch_info->recp_list[bit].root_buf,
-  recp);
-   bit++;
-   }
+   ice_zero_bitmap(pos_result_bm, ICE_MAX_FV_WORDS);
+
+   for (bit = 0; bit < ICE_MAX_FV_WORDS; bit++)
+   if (ICE_POSSIBLE_RES_IDX & BIT_ULL(bit))
+   ice_set_bit(bit, pos_result_bm);
 }
 
 /**
@@ -495,14 +490,16 @@ static enum ice_status
 ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,
bool *refresh_required)
 {
-   u16 i, sub_recps, fv_word_idx = 0, result_idx = 0;
-   ice_declare_bitmap(r_bitmap, ICE_MAX_NUM_PROFILES);
-   u16 result_idxs[ICE_MAX_CHAIN_RECIPE] = { 0 };
+   ice_declare_bitmap(possible_idx, ICE_MAX_FV_WORDS);
+   ice_declare_bitmap(result_bm, ICE_MAX_FV_WORDS);
struct ice_aqc_recipe_data_elem *tmp;
u16 num_recps = ICE_MAX_NUM_RECIPES;
struct ice_prot_lkup_ext *lkup_exts;
+   u16 i, sub_recps, fv_word_idx = 0;
enum ice_status status;
-   u8 is_root;
+
+   ice_zero_bitmap(result_bm, ICE_MAX_FV_WORDS);
+   ice_init_possible_res_bm(possible_idx);
 
/* we need a buffer big enough to accommodate all the recipes */
tmp = (struct ice_aqc_recipe_data_elem *)ice_calloc(hw,
@@ -528,14 +525,18 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct 
ice_sw_recipe *recps, u8 rid,
ice_get_recp_to_prof_map(hw);
*refresh_required = false;
}
-   lkup_exts = &recps[rid].lkup_exts;
-   /* start populating all the entries for recps[rid] based on lkups from
-* firmware
+
+   /* Start populating all the entries for recps[rid] based on lkups from
+* firmware. Note that we are only creating the root recipe in our
+* database.
 */
+   lkup_exts = &recps[rid].lkup_exts;
+
for (sub_recps = 0; sub_recps < num_recps; sub_recps++) {
struct ice_aqc_recipe_data_elem root_bufs = tmp[sub_recps];
struct ice_recp_grp_entry *rg_entry;
-   u8 prof_id, prot = 0;
+   u8 prof_id, idx, prot = 0;
+   bool is_root;
u16 off = 0;
 
rg_entry = (struct ice_recp_grp_entry *)
@@ -544,15 +545,18 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct 
ice_sw_recipe *recps, u8 rid,
status = ICE_ERR_NO_MEMORY;
goto err_unroll;
}
-   /* When copying, clear the result index enable bit */
-   result_idx

[dpdk-dev] [PATCH 39/63] net/ice/base: update UDP tunnel switch training packets

[Qi Zhang]

Change UDP tunnel training packets for the switch to work for both
Geneve and VXLAN cases.

Signed-off-by: Dan Nowlin 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_switch.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ice/base/ice_switch.c 
b/drivers/net/ice/base/ice_switch.c
index bc7caf1a8..65ec1bb93 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -179,7 +179,7 @@ u8 dummy_udp_tun_tcp_packet[] = {
0x00, 0x00, 0x12, 0xb5, /* ICE_UDP_OF 34 */
0x00, 0x46, 0x00, 0x00,
 
-   0x04, 0x00, 0x00, 0x03, /* ICE_VXLAN 42 */
+   0x00, 0x00, 0x65, 0x58, /* ICE_VXLAN 42 */
0x00, 0x00, 0x00, 0x00,
 
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_IL 50 */
@@ -230,7 +230,7 @@ u8 dummy_udp_tun_udp_packet[] = {
0x00, 0x00, 0x12, 0xb5, /* ICE_UDP_OF 34 */
0x00, 0x3a, 0x00, 0x00,
 
-   0x0c, 0x00, 0x00, 0x03, /* ICE_VXLAN 42 */
+   0x00, 0x00, 0x65, 0x58, /* ICE_VXLAN 42 */
0x00, 0x00, 0x00, 0x00,
 
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_IL 50 */
-- 
2.13.6

[dpdk-dev] [PATCH 38/63] net/ice/base: return switch error on invalid match criteria

[Qi Zhang]

Fixing ice_add_adv_rule to return an error when an invalid match
criteria is requested by the caller. This happens when the protocol
and offset pair is not supported by the package.

This change required a fix for the offset in the VXLAN GPE header,
and also found an issue with NVGRE where the package does not seem
to extract the correct offsets. Disabling the TDD test for NVGRE
until the time the shared code and package can align correctly.

Signed-off-by: Dan Nowlin 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_switch.c | 21 +
 1 file changed, 17 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ice/base/ice_switch.c 
b/drivers/net/ice/base/ice_switch.c
index 2a7ffc7aa..bc7caf1a8 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -4651,7 +4651,7 @@ static const struct ice_prot_ext_tbl_entry ice_prot_ext[] 
= {
{ ICE_SCTP_IL,  { 0, 2 } },
{ ICE_VXLAN,{ 8, 10, 12, 14 } },
{ ICE_GENEVE,   { 8, 10, 12, 14 } },
-   { ICE_VXLAN_GPE,{ 0, 2, 4 } },
+   { ICE_VXLAN_GPE,{ 8, 10, 12, 14 } },
{ ICE_NVGRE,{ 0, 2, 4, 6 } },
{ ICE_GTP,  { 8, 10, 12, 14, 16, 18, 20 } },
{ ICE_PPPOE,{ 0, 2, 4, 6 } },
@@ -4950,7 +4950,7 @@ ice_create_first_fit_recp_def(struct ice_hw *hw,
  * Helper function to fill in the field vector indices for protocol-offset
  * pairs. These indexes are then ultimately programmed into a recipe.
  */
-static void
+static enum ice_status
 ice_fill_fv_word_index(struct ice_hw *hw, struct LIST_HEAD_TYPE *fv_list,
   struct LIST_HEAD_TYPE *rg_list)
 {
@@ -4959,7 +4959,7 @@ ice_fill_fv_word_index(struct ice_hw *hw, struct 
LIST_HEAD_TYPE *fv_list,
struct ice_fv_word *fv_ext;
 
if (LIST_EMPTY(fv_list))
-   return;
+   return ICE_SUCCESS;
 
fv = LIST_FIRST_ENTRY(fv_list, struct ice_sw_fv_list_entry, list_entry);
fv_ext = fv->fv_ptr->ew;
@@ -4969,6 +4969,7 @@ ice_fill_fv_word_index(struct ice_hw *hw, struct 
LIST_HEAD_TYPE *fv_list,
 
for (i = 0; i < rg->r_group.n_val_pairs; i++) {
struct ice_fv_word *pr;
+   bool found = false;
u16 mask;
u8 j;
 
@@ -4978,6 +4979,8 @@ ice_fill_fv_word_index(struct ice_hw *hw, struct 
LIST_HEAD_TYPE *fv_list,
for (j = 0; j < hw->blk[ICE_BLK_SW].es.fvw; j++)
if (fv_ext[j].prot_id == pr->prot_id &&
fv_ext[j].off == pr->off) {
+   found = true;
+
/* Store index of field vector */
rg->fv_idx[i] = j;
/* Mask is given by caller as big
@@ -4987,8 +4990,16 @@ ice_fill_fv_word_index(struct ice_hw *hw, struct 
LIST_HEAD_TYPE *fv_list,
rg->fv_mask[i] = mask << 8 | mask >> 8;
break;
}
+
+   /* Protocol/offset could not be found, caller gave an
+* invalid pair
+*/
+   if (!found)
+   return ICE_ERR_PARAM;
}
}
+
+   return ICE_SUCCESS;
 }
 
 /**
@@ -5627,7 +5638,9 @@ ice_add_adv_recipe(struct ice_hw *hw, struct 
ice_adv_lkup_elem *lkups,
/* Find offsets from the field vector. Pick the first one for all the
 * recipes.
 */
-   ice_fill_fv_word_index(hw, &rm->fv_list, &rm->rg_list);
+   status = ice_fill_fv_word_index(hw, &rm->fv_list, &rm->rg_list);
+   if (status)
+   goto err_unroll;
 
/* get bitmap of all profiles the recipe will be associated with */
ice_zero_bitmap(profiles, ICE_MAX_NUM_PROFILES);
-- 
2.13.6

[dpdk-dev] [PATCH 42/63] net/ice/base: add routine for tunnel port query

[Qi Zhang]

Add ice_get_open_tunnel_port routine, which can be used to find
an open tunnel port for creating switch and flow director training
packets.

Signed-off-by: Dan Nowlin 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_flex_pipe.c | 22 ++
 drivers/net/ice/base/ice_flex_pipe.h |  3 +++
 2 files changed, 25 insertions(+)

diff --git a/drivers/net/ice/base/ice_flex_pipe.c 
b/drivers/net/ice/base/ice_flex_pipe.c
index 3beb4d961..8161ccaec 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -1874,6 +1874,28 @@ ice_find_free_tunnel_entry(struct ice_hw *hw, enum 
ice_tunnel_type type,
 }
 
 /**
+ * ice_get_tunnel_port - retrieve an open tunnel port
+ * @hw: pointer to the HW structure
+ * @type: tunnel type (TNL_ALL will return any open port)
+ * @port: returns open port
+ */
+bool
+ice_get_open_tunnel_port(struct ice_hw *hw, enum ice_tunnel_type type,
+u16 *port)
+{
+   u16 i;
+
+   for (i = 0; i < hw->tnl.count && i < ICE_TUNNEL_MAX_ENTRIES; i++)
+   if (hw->tnl.tbl[i].valid && hw->tnl.tbl[i].in_use &&
+   (type == TNL_ALL || hw->tnl.tbl[i].type == type)) {
+   *port = hw->tnl.tbl[i].port;
+   return true;
+   }
+
+   return false;
+}
+
+/**
  * ice_create_tunnel
  * @hw: pointer to the HW structure
  * @type: type of tunnel
diff --git a/drivers/net/ice/base/ice_flex_pipe.h 
b/drivers/net/ice/base/ice_flex_pipe.h
index 17285efe0..ab1663574 100644
--- a/drivers/net/ice/base/ice_flex_pipe.h
+++ b/drivers/net/ice/base/ice_flex_pipe.h
@@ -36,6 +36,9 @@ ice_get_sw_fv_bitmap(struct ice_hw *hw, enum ice_prof_type 
type,
 enum ice_status
 ice_get_sw_fv_list(struct ice_hw *hw, u16 *prot_ids, u8 ids_cnt,
   ice_bitmap_t *bm, struct LIST_HEAD_TYPE *fv_list);
+bool
+ice_get_open_tunnel_port(struct ice_hw *hw, enum ice_tunnel_type type,
+u16 *port);
 enum ice_status
 ice_create_tunnel(struct ice_hw *hw, enum ice_tunnel_type type, u16 port);
 enum ice_status ice_destroy_tunnel(struct ice_hw *hw, u16 port, bool all);
-- 
2.13.6

[dpdk-dev] [PATCH 41/63] net/ice/base: move and add some help function and macros

[Qi Zhang]

ice_ilog2 computes the integer log base 2 of the value (0 is undefined)
ice_is_pow2 returns true if the value is a power of 2 (0 is not a power
of 2).  Move the functions to ice_type.h and wrap them so that components
can strip or conditionally-compile out these implementations in lieu of
their own via osdep/other.
The patch also add help macro ROUND_UP and IS_ETHER_ADDR_EQUAL.

Signed-off-by: Bruce Allan 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_flow.c   |  9 -
 drivers/net/ice/base/ice_switch.c | 15 ---
 drivers/net/ice/base/ice_type.h   | 39 +++
 3 files changed, 39 insertions(+), 24 deletions(-)

diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index 9e93a1078..477cf5dfe 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -360,15 +360,6 @@ struct ice_flow_prof_params {
ice_declare_bitmap(ptypes, ICE_FLOW_PTYPE_MAX);
 };
 
-/**
- * ice_is_pow2 - check if integer value is a power of 2
- * @val: unsigned integer to be validated
- */
-static bool ice_is_pow2(u64 val)
-{
-   return (val && !(val & (val - 1)));
-}
-
 #define ICE_FLOW_SEG_HDRS_L2_MASK  \
(ICE_FLOW_SEG_HDR_ETH | ICE_FLOW_SEG_HDR_VLAN)
 #define ICE_FLOW_SEG_HDRS_L3_MASK  \
diff --git a/drivers/net/ice/base/ice_switch.c 
b/drivers/net/ice/base/ice_switch.c
index b4f50e0e5..ef3a919ec 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -1849,21 +1849,6 @@ static void ice_fill_sw_info(struct ice_hw *hw, struct 
ice_fltr_info *fi)
 }
 
 /**
- * ice_ilog2 - Calculates integer log base 2 of a number
- * @n: number on which to perform operation
- */
-static int ice_ilog2(u64 n)
-{
-   int i;
-
-   for (i = 63; i >= 0; i--)
-   if (((u64)1 << i) & n)
-   return i;
-
-   return -1;
-}
-
-/**
  * ice_fill_sw_rule - Helper function to fill switch rule structure
  * @hw: pointer to the hardware structure
  * @f_info: entry containing packet forwarding information
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 541e29851..403fb7668 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -22,6 +22,16 @@
 #define ICE_BYTES_PER_DWORD4
 #define ICE_MAX_TRAFFIC_CLASS  8
 
+/**
+ * ROUND_UP - round up to next arbitrary multiple (not a power of 2)
+ * @a: value to round up
+ * @b: arbitrary multiple
+ *
+ * Round up to the next multiple of the arbitrary b.
+ * Note, when b is a power of 2 use ICE_ALIGN() instead.
+ */
+#define ROUND_UP(a, b) ((b) * DIVIDE_AND_ROUND_UP((a), (b)))
+
 #define MIN_T(_t, _a, _b)  min((_t)(_a), (_t)(_b))
 
 #define IS_ASCII(_ch)  ((_ch) < 0x80)
@@ -36,6 +46,30 @@
 #include "ice_flex_type.h"
 #include "ice_protocol_type.h"
 
+/**
+ * ice_is_pow2 - check if integer value is a power of 2
+ * @val: unsigned integer to be validated
+ */
+static inline bool ice_is_pow2(u64 val)
+{
+   return (val && !(val & (val - 1)));
+}
+
+/**
+ * ice_ilog2 - Calculates integer log base 2 of a number
+ * @n: number on which to perform operation
+ */
+static inline int ice_ilog2(u64 n)
+{
+   int i;
+
+   for (i = 63; i >= 0; i--)
+   if (((u64)1 << i) & n)
+   return i;
+
+   return -1;
+}
+
 static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc)
 {
return ice_is_bit_set(&bitmap, tc);
@@ -104,6 +138,11 @@ static inline u32 ice_round_to_num(u32 N, u32 R)
 
 
 
+#define IS_ETHER_ADDR_EQUAL(addr1, addr2) \
+   (((bool)u16 *)(addr1))[0] == ((u16 *)(addr2))[0]))) && \
+((bool)u16 *)(addr1))[1] == ((u16 *)(addr2))[1]))) && \
+((bool)u16 *)(addr1))[2] == ((u16 *)(addr2))[2]
+
 enum ice_aq_res_ids {
ICE_NVM_RES_ID = 1,
ICE_SPD_RES_ID,
-- 
2.13.6

[dpdk-dev] [PATCH 46/63] net/ice/base: add RSS support for PPPoE and GTPU

[Qi Zhang]

Added RSS support for PPPoE with inner TCP and UDP.
Added RSS support for GTPU with IPv4 and IPv6.

Signed-off-by: Zhirun Yan 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_flow.c | 38 --
 drivers/net/ice/base/ice_flow.h | 17 +++--
 2 files changed, 43 insertions(+), 12 deletions(-)

diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index a49196c1c..f71ac50d6 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -167,7 +167,7 @@ static const u32 ice_ptypes_macvlan_il[] = {
 static const u32 ice_ptypes_ipv4_ofos[] = {
0xFDC0, 0xBFBF7F7E, 0x00EFDFDF, 0x,
0x, 0x, 0x, 0x,
-   0x0003000F, 0x, 0x, 0x,
+   0x0003000F, 0x000FC000, 0x, 0x,
0x, 0x, 0x, 0x,
0x, 0x, 0x, 0x,
0x, 0x, 0x, 0x,
@@ -179,7 +179,7 @@ static const u32 ice_ptypes_ipv4_ofos[] = {
 static const u32 ice_ptypes_ipv4_il[] = {
0xE000, 0xB807700E, 0x8001DC03, 0xE01DC03B,
0x0007700E, 0x, 0x, 0x,
-   0x, 0x, 0x, 0x,
+   0x, 0x, 0x000FF800, 0x,
0x, 0x, 0x, 0x,
0x, 0x, 0x, 0x,
0x, 0x, 0x, 0x,
@@ -191,7 +191,7 @@ static const u32 ice_ptypes_ipv4_il[] = {
 static const u32 ice_ptypes_ipv6_ofos[] = {
0x, 0x, 0xF700, 0xFEFDFDFB,
0x03BF7F7E, 0x, 0x, 0x,
-   0x00080F00, 0x, 0x, 0x,
+   0x00080F00, 0x03F0, 0x, 0x,
0x, 0x, 0x, 0x,
0x, 0x, 0x, 0x,
0x, 0x, 0x, 0x,
@@ -203,7 +203,7 @@ static const u32 ice_ptypes_ipv6_ofos[] = {
 static const u32 ice_ptypes_ipv6_il[] = {
0x, 0x03B80770, 0x00EE01DC, 0x0EE0,
0x03B80770, 0x, 0x, 0x,
-   0x, 0x, 0x, 0x,
+   0x, 0x, 0x7FE0, 0x,
0x, 0x, 0x, 0x,
0x, 0x, 0x, 0x,
0x, 0x, 0x, 0x,
@@ -229,7 +229,7 @@ static const u32 ice_ptypes_arp_of[] = {
 static const u32 ice_ptypes_udp_il[] = {
0x8100, 0x20204040, 0x04081010, 0x80810102,
0x00204040, 0x, 0x, 0x,
-   0x, 0x, 0x, 0x,
+   0x, 0x0041, 0x10842000, 0x,
0x, 0x, 0x, 0x,
0x, 0x, 0x, 0x,
0x, 0x, 0x, 0x,
@@ -241,7 +241,7 @@ static const u32 ice_ptypes_udp_il[] = {
 static const u32 ice_ptypes_tcp_il[] = {
0x0400, 0x80810102, 0x10204040, 0x42040408,
0x00810102, 0x, 0x, 0x,
-   0x, 0x, 0x, 0x,
+   0x, 0x0082, 0x21084000, 0x,
0x, 0x, 0x, 0x,
0x, 0x, 0x, 0x,
0x, 0x, 0x, 0x,
@@ -277,7 +277,7 @@ static const u32 ice_ptypes_icmp_of[] = {
 static const u32 ice_ptypes_icmp_il[] = {
0x, 0x02040408, 0x40810102, 0x08101020,
0x02040408, 0x, 0x, 0x,
-   0x, 0x, 0x, 0x,
+   0x, 0x, 0x42108000, 0x,
0x, 0x, 0x, 0x,
0x, 0x, 0x, 0x,
0x, 0x, 0x, 0x,
@@ -345,6 +345,18 @@ static const u32 ice_ptypes_gtpu[] = {
0x, 0x, 0x, 0x,
 };
 
+/* Packet types for pppoe */
+static const u32 ice_ptypes_pppoe[] = {
+   0x, 0x, 0x, 0x,
+   0x, 0x, 0x, 0x,
+   0x, 0x03FFF000, 0x, 0x,
+   0x, 0x, 0x, 0x,
+   0x, 0x, 0x, 0x,
+   0x, 0x, 0x, 0x,
+   0x, 0x, 0x, 0x,
+   0x, 0x, 0x, 0x,
+};
+
 /* Manage parameters and info. used during the creation of a flow profile */
 struct ice_flow_prof_params {
enum ice_block blk;
@@ -368,8 +380,7 @@ struct ice_flow_prof_params {
 #define ICE_FLOW_SEG_HDRS_L4_MASK  \
(ICE_FLOW_SEG_HDR_ICMP | ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_H

[dpdk-dev] [PATCH 43/63] net/ice/base: ptype group consolidation

[Qi Zhang]

This patch is an optimization to decrease the number of TCAM entries
used in the profile blocks, especially for RSS. To be most effective
this will also require a package change in order to decrease the number
of PTYPE groups necessary to program RSS, FD and ACL rules.

Signed-off-by: Dan Nowlin 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_flex_pipe.c | 214 ++-
 drivers/net/ice/base/ice_flex_pipe.h |   2 +-
 drivers/net/ice/base/ice_flex_type.h |   8 +-
 3 files changed, 89 insertions(+), 135 deletions(-)

diff --git a/drivers/net/ice/base/ice_flex_pipe.c 
b/drivers/net/ice/base/ice_flex_pipe.c
index 8161ccaec..6ae71e698 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -2121,29 +2121,6 @@ void ice_ptg_alloc_val(struct ice_hw *hw, enum ice_block 
blk, u8 ptg)
hw->blk[blk].xlt1.ptg_tbl[ptg].in_use = true;
 }
 
-/**
- * ice_ptg_alloc - Find a free entry and allocates a new packet type group ID
- * @hw: pointer to the hardware structure
- * @blk: HW block
- *
- * This function allocates and returns a new packet type group ID. Note
- * that 0 is the default packet type group, so successfully created PTGs will
- * have a non-zero ID value; which means a 0 return value indicates an error.
- */
-static u8 ice_ptg_alloc(struct ice_hw *hw, enum ice_block blk)
-{
-   u16 i;
-
-   /* Skip the default PTG of 0 */
-   for (i = 1; i < ICE_MAX_PTGS; i++)
-   if (!hw->blk[blk].xlt1.ptg_tbl[i].in_use) {
-   /* found a free PTG ID */
-   ice_ptg_alloc_val(hw, blk, i);
-   return (u8)i;
-   }
-
-   return 0;
-}
 
 /**
  * ice_ptg_remove_ptype - Removes ptype from a particular packet type group
@@ -3884,43 +3861,6 @@ ice_vsig_get_ref(struct ice_hw *hw, enum ice_block blk, 
u16 vsig, u16 *refs)
 }
 
 /**
- * ice_get_ptg - get or allocate a ptg for a ptype
- * @hw: pointer to the hardware structure
- * @blk: HW block
- * @ptype: the ptype to retrieve the PTG for
- * @ptg: receives the PTG of the ptype
- * @add: receive boolean indicating whether PTG was added or not
- */
-static enum ice_status
-ice_get_ptg(struct ice_hw *hw, enum ice_block blk, u16 ptype, u8 *ptg,
-   bool *add)
-{
-   enum ice_status status;
-
-   *ptg = ICE_DEFAULT_PTG;
-   *add = false;
-
-   status = ice_ptg_find_ptype(hw, blk, ptype, ptg);
-   if (status)
-   return status;
-
-   if (*ptg == ICE_DEFAULT_PTG) {
-   /* need to allocate a PTG, and add ptype to it */
-   *ptg = ice_ptg_alloc(hw, blk);
-   if (*ptg == ICE_DEFAULT_PTG)
-   return ICE_ERR_HW_TABLE;
-
-   status = ice_ptg_add_mv_ptype(hw, blk, ptype, *ptg);
-   if (status)
-   return ICE_ERR_HW_TABLE;
-
-   *add = true;
-   }
-
-   return ICE_SUCCESS;
-};
-
-/**
  * ice_has_prof_vsig - check to see if VSIG has a specific profile
  * @hw: pointer to the hardware structure
  * @blk: HW block
@@ -4420,11 +4360,14 @@ ice_add_prof_with_mask(struct ice_hw *hw, enum 
ice_block blk, u64 id,
   u8 ptypes[], struct ice_fv_word *es, u16 *masks)
 {
u32 bytes = DIVIDE_AND_ROUND_UP(ICE_FLOW_PTYPE_MAX, BITS_PER_BYTE);
+   ice_declare_bitmap(ptgs_used, ICE_XLT1_CNT);
struct ice_prof_map *prof;
enum ice_status status;
u32 byte = 0;
u8 prof_id;
 
+   ice_zero_bitmap(ptgs_used, ICE_XLT1_CNT);
+
ice_acquire_lock(&hw->blk[blk].es.prof_map_lock);
 
/* search for existing profile */
@@ -4464,11 +4407,11 @@ ice_add_prof_with_mask(struct ice_hw *hw, enum 
ice_block blk, u64 id,
 
prof->profile_cookie = id;
prof->prof_id = prof_id;
-   prof->ptype_count = 0;
+   prof->ptg_cnt = 0;
prof->context = 0;
 
/* build list of ptgs */
-   while (bytes && prof->ptype_count < ICE_MAX_PTYPE_PER_PROFILE) {
+   while (bytes && prof->ptg_cnt < ICE_MAX_PTG_PER_PROFILE) {
u32 bit;
 
if (!ptypes[byte]) {
@@ -4480,16 +4423,27 @@ ice_add_prof_with_mask(struct ice_hw *hw, enum 
ice_block blk, u64 id,
for (bit = 0; bit < 8; bit++) {
if (ptypes[byte] & BIT(bit)) {
u16 ptype;
+   u8 ptg;
u8 m;
 
ptype = byte * BITS_PER_BYTE + bit;
-   if (ptype < ICE_FLOW_PTYPE_MAX) {
-   prof->ptype[prof->ptype_count] = ptype;
 
-   if (++prof->ptype_count >=
-   ICE_MAX_PTYPE_PER_PROFILE)
-   break;
-   }
+   

[dpdk-dev] [PATCH 48/63] net/ice/base: fix flag settings in AQ call

[Qi Zhang]

Removed setting Read flag in the Get Allocated Resource Descriptors AQ
command (0x020A). The read flag is not required for this command and
causes the FW to return an error.

Fixes: d781ccbdd15d ("net/ice/base: add functions to get allocated resources")
Cc: sta...@dpdk.org

Signed-off-by: Dan Nowlin 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_switch.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/net/ice/base/ice_switch.c 
b/drivers/net/ice/base/ice_switch.c
index a4966d0a1..9e85da530 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -2978,8 +2978,6 @@ ice_aq_get_res_descs(struct ice_hw *hw, u16 num_entries,
ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
cmd->ops.cmd.first_desc = CPU_TO_LE16(*desc_id);
 
-   desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
-
status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
if (!status)
*desc_id = LE16_TO_CPU(cmd->ops.resp.next_desc);
-- 
2.13.6

[dpdk-dev] [PATCH 47/63] net/ice/base: remove unnecessary conditional check

[Qi Zhang]

There is no reason to do this conditional check before the assignment so
simply remove it.

Signed-off-by: Bruce Allan 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_switch.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/net/ice/base/ice_switch.c 
b/drivers/net/ice/base/ice_switch.c
index ef3a919ec..a4966d0a1 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -1145,8 +1145,7 @@ ice_add_vsi(struct ice_hw *hw, u16 vsi_handle, struct 
ice_vsi_ctx *vsi_ctx,
ice_save_vsi_ctx(hw, vsi_handle, tmp_vsi_ctx);
} else {
/* update with new HW VSI num */
-   if (tmp_vsi_ctx->vsi_num != vsi_ctx->vsi_num)
-   tmp_vsi_ctx->vsi_num = vsi_ctx->vsi_num;
+   tmp_vsi_ctx->vsi_num = vsi_ctx->vsi_num;
}
 
return ICE_SUCCESS;
-- 
2.13.6

[dpdk-dev] [PATCH 45/63] net/ice/base: packet encapsulation for RSS

[Qi Zhang]

RSS configurations calls currently support only non-tunneled packets,
which uses outer-first IPs. Adding another call to configure RSS for
tunneled packets which will enable hashing on inner-last IP. RSS hash
will only be done on the innermost IP.
- Update RSS configuration calls to take packet segment count as input
  argument
- Update flow profile ID to include identifier for encapsulated packet
  [0:31] : Packet match fields
  [32:62]: Protocol header header
  [63]: Encapsulation flag, 0 if non-tunneled, 1 if tunneled

Signed-off-by: Vignesh Sridhar 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_flow.c | 132 
 1 file changed, 80 insertions(+), 52 deletions(-)

diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index 9a35a11d5..a49196c1c 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -379,16 +379,9 @@ struct ice_flow_prof_params {
 static enum ice_status
 ice_flow_val_hdrs(struct ice_flow_seg_info *segs, u8 segs_cnt)
 {
-   const u32 masks = (ICE_FLOW_SEG_HDRS_L2_MASK |
-  ICE_FLOW_SEG_HDRS_L3_MASK |
-  ICE_FLOW_SEG_HDRS_L4_MASK);
u8 i;
 
for (i = 0; i < segs_cnt; i++) {
-   /* No header specified */
-   if (!(segs[i].hdrs & masks) || (segs[i].hdrs & ~masks))
-   return ICE_ERR_PARAM;
-
/* Multiple L3 headers */
if (segs[i].hdrs & ICE_FLOW_SEG_HDRS_L3_MASK &&
!ice_is_pow2(segs[i].hdrs & ICE_FLOW_SEG_HDRS_L3_MASK))
@@ -1866,11 +1859,22 @@ ice_add_rss_list(struct ice_hw *hw, u16 vsi_handle, 
struct ice_flow_prof *prof)
 #define ICE_FLOW_PROF_HASH_S   0
 #define ICE_FLOW_PROF_HASH_M   (0xULL << ICE_FLOW_PROF_HASH_S)
 #define ICE_FLOW_PROF_HDR_S32
-#define ICE_FLOW_PROF_HDR_M(0xULL << ICE_FLOW_PROF_HDR_S)
+#define ICE_FLOW_PROF_HDR_M(0x3FFFULL << ICE_FLOW_PROF_HDR_S)
+#define ICE_FLOW_PROF_ENCAP_S  63
+#define ICE_FLOW_PROF_ENCAP_M  (BIT_ULL(ICE_FLOW_PROF_ENCAP_S))
+
+#define ICE_RSS_OUTER_HEADERS  1
+#define ICE_RSS_INNER_HEADERS  2
 
-#define ICE_FLOW_GEN_PROFID(hash, hdr) \
+/* Flow profile ID format:
+ * [0:31] - Packet match fields
+ * [32:62] - Protocol header
+ * [63] - Encapsulation flag, 0 if non-tunneled, 1 if tunneled
+ */
+#define ICE_FLOW_GEN_PROFID(hash, hdr, segs_cnt) \
(u64)(((u64)(hash) & ICE_FLOW_PROF_HASH_M) | \
- (((u64)(hdr) << ICE_FLOW_PROF_HDR_S) & ICE_FLOW_PROF_HDR_M))
+ (((u64)(hdr) << ICE_FLOW_PROF_HDR_S) & ICE_FLOW_PROF_HDR_M) | \
+ ((u8)((segs_cnt) - 1) ? ICE_FLOW_PROF_ENCAP_M : 0))
 
 /**
  * ice_add_rss_cfg_sync - add an RSS configuration
@@ -1878,24 +1882,30 @@ ice_add_rss_list(struct ice_hw *hw, u16 vsi_handle, 
struct ice_flow_prof *prof)
  * @vsi_handle: software VSI handle
  * @hashed_flds: hash bit fields (ICE_FLOW_HASH_*) to configure
  * @addl_hdrs: protocol header fields
+ * @segs_cnt: packet segment count
  *
  * Assumption: lock has already been acquired for RSS list
  */
 static enum ice_status
 ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
-u32 addl_hdrs)
+u32 addl_hdrs, u8 segs_cnt)
 {
const enum ice_block blk = ICE_BLK_RSS;
struct ice_flow_prof *prof = NULL;
struct ice_flow_seg_info *segs;
enum ice_status status = ICE_SUCCESS;
 
-   segs = (struct ice_flow_seg_info *)ice_malloc(hw, sizeof(*segs));
+   if (!segs_cnt || segs_cnt > ICE_FLOW_SEG_MAX)
+   return ICE_ERR_PARAM;
+
+   segs = (struct ice_flow_seg_info *)ice_calloc(hw, segs_cnt,
+ sizeof(*segs));
if (!segs)
return ICE_ERR_NO_MEMORY;
 
/* Construct the packet segment info from the hashed fields */
-   status = ice_flow_set_rss_seg_info(segs, hashed_flds, addl_hdrs);
+   status = ice_flow_set_rss_seg_info(&segs[segs_cnt - 1], hashed_flds,
+  addl_hdrs);
if (status)
goto exit;
 
@@ -1903,7 +1913,7 @@ ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, 
u64 hashed_flds,
 * and has the input VSI associated to it. If found, no further
 * operations required and exit.
 */
-   prof = ice_flow_find_prof_conds(hw, blk, ICE_FLOW_RX, segs, 1,
+   prof = ice_flow_find_prof_conds(hw, blk, ICE_FLOW_RX, segs, segs_cnt,
vsi_handle,
ICE_FLOW_FIND_PROF_CHK_FLDS |
ICE_FLOW_FIND_PROF_CHK_VSI);
@@ -1915,7 +1925,7 @@ ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, 
u64 hashed_flds,
 * this profile. The VSI will be added to a new profile created with
 * the protocol header and new hash field con

[dpdk-dev] [PATCH 49/63] net/ice/base: refactor removal of VLAN promiscuous rules

[Qi Zhang]

Currently ice_clear_vsi_promisc() detects if the VLAN ID sent is not 0
and sets the recipe_id to ICE_SW_LKUP_PROMISC_VLAN in that case and
ICE_SW_LKUP_PROMISC if the VLAN_ID is 0. However this doesn't allow VLAN
0 promiscuous rules to be removed, but they can be added. Fix this by
checking if the promisc_mask contains ICE_PROMISC_VLAN_RX or
ICE_PROMISC_VLAN_TX. This change was made to match what is being done
for ice_set_vsi_promisc().

Signed-off-by: Brett Creeley 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_switch.c | 13 +
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ice/base/ice_switch.c 
b/drivers/net/ice/base/ice_switch.c
index 9e85da530..1f077d562 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -3977,7 +3977,7 @@ ice_clear_vsi_promisc(struct ice_hw *hw, u16 vsi_handle, 
u8 promisc_mask,
if (!ice_is_vsi_valid(hw, vsi_handle))
return ICE_ERR_PARAM;
 
-   if (vid)
+   if (promisc_mask & (ICE_PROMISC_VLAN_RX | ICE_PROMISC_VLAN_TX))
recipe_id = ICE_SW_LKUP_PROMISC_VLAN;
else
recipe_id = ICE_SW_LKUP_PROMISC;
@@ -3990,13 +3990,18 @@ ice_clear_vsi_promisc(struct ice_hw *hw, u16 
vsi_handle, u8 promisc_mask,
ice_acquire_lock(rule_lock);
LIST_FOR_EACH_ENTRY(itr, rule_head,
ice_fltr_mgmt_list_entry, list_entry) {
+   struct ice_fltr_info *fltr_info;
u8 fltr_promisc_mask = 0;
 
if (!ice_vsi_uses_fltr(itr, vsi_handle))
continue;
+   fltr_info = &itr->fltr_info;
+
+   if (recipe_id == ICE_SW_LKUP_PROMISC_VLAN &&
+   vid != fltr_info->l_data.mac_vlan.vlan_id)
+   continue;
 
-   fltr_promisc_mask |=
-   ice_determine_promisc_mask(&itr->fltr_info);
+   fltr_promisc_mask |= ice_determine_promisc_mask(fltr_info);
 
/* Skip if filter is not completely specified by given mask */
if (fltr_promisc_mask & ~promisc_mask)
@@ -4004,7 +4009,7 @@ ice_clear_vsi_promisc(struct ice_hw *hw, u16 vsi_handle, 
u8 promisc_mask,
 
status = ice_add_entry_to_vsi_fltr_list(hw, vsi_handle,
&remove_list_head,
-   &itr->fltr_info);
+   fltr_info);
if (status) {
ice_release_lock(rule_lock);
goto free_fltr_list;
-- 
2.13.6

[dpdk-dev] [PATCH 44/63] net/ice/base: fix for RSS hash on inner UDP port

[Qi Zhang]

Before this patch, only outer IP with inner UDP port can appear in
RSS hash, because the extraction sequence uses outer IP protocol
ID with Inner UDP protocol ID. ICE_PROT_UDP_OF always extracts the
TUNNELED UDP port values (i.e., 4789 for VXLAN). ICE_PROT_UDP_IL_OR_S
will extract NON-TUNNELED UDP port or inner UDP port.

Fixes: aa1cd410fa64 ("net/ice/base: add flow module")
Cc: sta...@dpdk.org

Signed-off-by: Zhirun Yan 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_flow.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index 477cf5dfe..9a35a11d5 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -670,7 +670,7 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct 
ice_flow_prof_params *params,
break;
case ICE_FLOW_FIELD_IDX_UDP_SRC_PORT:
case ICE_FLOW_FIELD_IDX_UDP_DST_PORT:
-   prot_id = seg == 0 ? ICE_PROT_UDP_IL_OR_S : ICE_PROT_UDP_OF;
+   prot_id = ICE_PROT_UDP_IL_OR_S;
break;
case ICE_FLOW_FIELD_IDX_SCTP_SRC_PORT:
case ICE_FLOW_FIELD_IDX_SCTP_DST_PORT:
-- 
2.13.6

[dpdk-dev] [PATCH 51/63] net/ice/base: update switch training packets with open ports

[Qi Zhang]

This patch updates UDP tunneled training packets with an appropriate
UDP dest port. For the correct profile to be chosen, an open tunnel
port must be included in the training packet.

Added GENEVE tunnel labels in the test package in order to test GENEVE
tunnel rule creation.

Signed-off-by: Dan Nowlin 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_switch.c | 57 +++
 1 file changed, 57 insertions(+)

diff --git a/drivers/net/ice/base/ice_switch.c 
b/drivers/net/ice/base/ice_switch.c
index ef12df5db..c39a77a0f 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -5826,6 +5826,55 @@ ice_fill_adv_dummy_packet(struct ice_adv_lkup_elem 
*lkups, u16 lkups_cnt,
 }
 
 /**
+ * ice_fill_adv_packet_tun - fill dummy packet with udp tunnel port
+ * @hw: pointer to the hardware structure
+ * @tun_type: tunnel type
+ * @pkt: dummy packet to fill in
+ * @offsets: offset info for the dummy packet
+ */
+static enum ice_status
+ice_fill_adv_packet_tun(struct ice_hw *hw, enum ice_sw_tunnel_type tun_type,
+   u8 *pkt, const struct ice_dummy_pkt_offsets *offsets)
+{
+   u16 open_port, i;
+
+   switch (tun_type) {
+   case ICE_SW_TUN_AND_NON_TUN:
+   case ICE_SW_TUN_VXLAN_GPE:
+   case ICE_SW_TUN_VXLAN:
+   case ICE_SW_TUN_UDP:
+   if (!ice_get_open_tunnel_port(hw, TNL_VXLAN, &open_port))
+   return ICE_ERR_CFG;
+   break;
+
+   case ICE_SW_TUN_GENEVE:
+   if (!ice_get_open_tunnel_port(hw, TNL_GENEVE, &open_port))
+   return ICE_ERR_CFG;
+   break;
+
+   default:
+   /* Nothing needs to be done for this tunnel type */
+   return ICE_SUCCESS;
+   }
+
+   /* Find the outer UDP protocol header and insert the port number */
+   for (i = 0; offsets[i].type != ICE_PROTOCOL_LAST; i++) {
+   if (offsets[i].type == ICE_UDP_OF) {
+   struct ice_l4_hdr *hdr;
+   u16 offset;
+
+   offset = offsets[i].offset;
+   hdr = (struct ice_l4_hdr *)&pkt[offset];
+   hdr->dst_port = open_port << 8 | open_port >> 8;
+
+   return ICE_SUCCESS;
+   }
+   }
+
+   return ICE_ERR_CFG;
+}
+
+/**
  * ice_find_adv_rule_entry - Search a rule entry
  * @hw: pointer to the hardware structure
  * @lkups: lookup elements or match criteria for the advanced recipe, one
@@ -6129,6 +6178,14 @@ ice_add_adv_rule(struct ice_hw *hw, struct 
ice_adv_lkup_elem *lkups,
ice_fill_adv_dummy_packet(lkups, lkups_cnt, s_rule, pkt, pkt_len,
  pkt_offsets);
 
+   if (rinfo->tun_type != ICE_NON_TUN) {
+   status = ice_fill_adv_packet_tun(hw, rinfo->tun_type,
+s_rule->pdata.lkup_tx_rx.hdr,
+pkt_offsets);
+   if (status)
+   goto err_ice_add_adv_rule;
+   }
+
status = ice_aq_sw_rules(hw, (struct ice_aqc_sw_rules *)s_rule,
 rule_buf_sz, 1, ice_aqc_opc_add_sw_rules,
 NULL);
-- 
2.13.6

[dpdk-dev] [PATCH 50/63] net/ice/base: maximize switch recipe words per line

[Qi Zhang]

Remove grouping rules to maximize the number of words placed into
a recipe line. This will allow more recipes to be added by reducing
the number of result indices required.

Signed-off-by: Dan Nowlin 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_switch.c | 128 --
 1 file changed, 128 deletions(-)

diff --git a/drivers/net/ice/base/ice_switch.c 
b/drivers/net/ice/base/ice_switch.c
index 1f077d562..ef12df5db 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -4655,17 +4655,6 @@ static const struct ice_prot_ext_tbl_entry 
ice_prot_ext[] = {
  * following combinations, then the recipe needs to be chained as per the
  * following policy.
  */
-static const struct ice_pref_recipe_group ice_recipe_pack[] = {
-   {3, { { ICE_MAC_OFOS_HW, 0, 0 }, { ICE_MAC_OFOS_HW, 2, 0 },
- { ICE_MAC_OFOS_HW, 4, 0 } }, { 0x, 0x, 0x, 0x } },
-   {4, { { ICE_MAC_IL_HW, 0, 0 }, { ICE_MAC_IL_HW, 2, 0 },
- { ICE_MAC_IL_HW, 4, 0 }, { ICE_META_DATA_ID_HW, 44, 0 } },
-   { 0x, 0x, 0x, 0x } },
-   {2, { { ICE_IPV4_IL_HW, 0, 0 }, { ICE_IPV4_IL_HW, 2, 0 } },
-   { 0x, 0x, 0x, 0x } },
-   {2, { { ICE_IPV4_IL_HW, 12, 0 }, { ICE_IPV4_IL_HW, 14, 0 } },
-   { 0x, 0x, 0x, 0x } },
-};
 
 static const struct ice_protocol_entry ice_prot_id_tbl[] = {
{ ICE_MAC_OFOS, ICE_MAC_OFOS_HW },
@@ -4812,75 +4801,7 @@ ice_fill_valid_words(struct ice_adv_lkup_elem *rule,
return ret_val;
 }
 
-/**
- * ice_find_prot_off_ind - check for specific ID and offset in rule
- * @lkup_exts: an array of protocol header extractions
- * @prot_type: protocol type to check
- * @off: expected offset of the extraction
- *
- * Check if the prot_ext has given protocol ID and offset
- */
-static u8
-ice_find_prot_off_ind(struct ice_prot_lkup_ext *lkup_exts, u8 prot_type,
- u16 off)
-{
-   u8 j;
-
-   for (j = 0; j < lkup_exts->n_val_words; j++)
-   if (lkup_exts->fv_words[j].off == off &&
-   lkup_exts->fv_words[j].prot_id == prot_type)
-   return j;
-
-   return ICE_MAX_CHAIN_WORDS;
-}
-
-/**
- * ice_is_recipe_subset - check if recipe group policy is a subset of lookup
- * @lkup_exts: an array of protocol header extractions
- * @r_policy: preferred recipe grouping policy
- *
- * Helper function to check if given recipe group is subset we need to check if
- * all the words described by the given recipe group exist in the advanced rule
- * look up information
- */
-static bool
-ice_is_recipe_subset(struct ice_prot_lkup_ext *lkup_exts,
-const struct ice_pref_recipe_group *r_policy)
-{
-   u8 ind[ICE_NUM_WORDS_RECIPE];
-   u8 count = 0;
-   u8 i;
-
-   /* check if everything in the r_policy is part of the entire rule */
-   for (i = 0; i < r_policy->n_val_pairs; i++) {
-   u8 j;
-
-   j = ice_find_prot_off_ind(lkup_exts, r_policy->pairs[i].prot_id,
- r_policy->pairs[i].off);
-   if (j >= ICE_MAX_CHAIN_WORDS)
-   return false;
-
-   /* store the indexes temporarily found by the find function
-* this will be used to mark the words as 'done'
-*/
-   ind[count++] = j;
-   }
-
-   /* If the entire policy recipe was a true match, then mark the fields
-* that are covered by the recipe as 'done' meaning that these words
-* will be clumped together in one recipe.
-* "Done" here means in our searching if certain recipe group
-* matches or is subset of the given rule, then we mark all
-* the corresponding offsets as found. So the remaining recipes should
-* be created with whatever words that were left.
-*/
-   for (i = 0; i < count; i++) {
-   u8 in = ind[i];
 
-   ice_set_bit(in, lkup_exts->done);
-   }
-   return true;
-}
 
 /**
  * ice_create_first_fit_recp_def - Create a recipe grouping
@@ -5389,51 +5310,11 @@ static enum ice_status
 ice_create_recipe_group(struct ice_hw *hw, struct ice_sw_recipe *rm,
struct ice_prot_lkup_ext *lkup_exts)
 {
-   struct ice_recp_grp_entry *entry;
-   struct ice_recp_grp_entry *tmp;
enum ice_status status;
u8 recp_count = 0;
-   u16 groups, i;
 
rm->n_grp_count = 0;
 
-
-   if (lkup_exts->n_val_words > ICE_NUM_WORDS_RECIPE) {
-   /* Each switch recipe can match up to 5 words or metadata. One
-* word in each recipe is used to match the switch ID. Four
-* words are left for matching other values. If the new advanced
-* recipe requires more than 4 words, it needs to be split into
-* 

[dpdk-dev] [PATCH 52/63] net/ice/base: remove unnecessary dummy packet finding

[Qi Zhang]

We don't need to find a dummy packet when removing a rule so remove
the call to get the dummy packet. This also obviates some variables
so remove them also.

Also reduce the scope of rule_buf_sz.

Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_switch.c | 10 +++---
 1 file changed, 3 insertions(+), 7 deletions(-)

diff --git a/drivers/net/ice/base/ice_switch.c 
b/drivers/net/ice/base/ice_switch.c
index c39a77a0f..063a26ec5 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -6360,14 +6360,11 @@ ice_rem_adv_rule(struct ice_hw *hw, struct 
ice_adv_lkup_elem *lkups,
 u16 lkups_cnt, struct ice_adv_rule_info *rinfo)
 {
struct ice_adv_fltr_mgmt_list_entry *list_elem;
-   const struct ice_dummy_pkt_offsets *offsets;
struct ice_prot_lkup_ext lkup_exts;
-   u16 rule_buf_sz, pkt_len, i, rid;
struct ice_lock *rule_lock; /* Lock to protect filter rule list */
enum ice_status status = ICE_SUCCESS;
bool remove_rule = false;
-   const u8 *pkt = NULL;
-   u16 vsi_handle;
+   u16 i, rid, vsi_handle;
 
ice_memset(&lkup_exts, 0, sizeof(lkup_exts), ICE_NONDMA_MEM);
for (i = 0; i < lkups_cnt; i++) {
@@ -6419,10 +6416,9 @@ ice_rem_adv_rule(struct ice_hw *hw, struct 
ice_adv_lkup_elem *lkups,
ice_release_lock(rule_lock);
if (remove_rule) {
struct ice_aqc_sw_rules_elem *s_rule;
+   u16 rule_buf_sz;
 
-   ice_find_dummy_packet(lkups, lkups_cnt, rinfo->tun_type, &pkt,
- &pkt_len, &offsets);
-   rule_buf_sz = ICE_SW_RULE_RX_TX_NO_HDR_SIZE + pkt_len;
+   rule_buf_sz = ICE_SW_RULE_RX_TX_NO_HDR_SIZE;
s_rule =
(struct ice_aqc_sw_rules_elem *)ice_malloc(hw,
   rule_buf_sz);
-- 
2.13.6

[dpdk-dev] [PATCH 55/63] net/ice/base: update to register definition file

[Qi Zhang]

Added register definitions for GL_MDCK_TX_TDPU and GL_MDET_TX_TDPU.

Signed-off-by: Bruce Allan 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_hw_autogen.h | 34 ++
 1 file changed, 34 insertions(+)

diff --git a/drivers/net/ice/base/ice_hw_autogen.h 
b/drivers/net/ice/base/ice_hw_autogen.h
index 2b423baf8..6f227adb8 100644
--- a/drivers/net/ice/base/ice_hw_autogen.h
+++ b/drivers/net/ice/base/ice_hw_autogen.h
@@ -5330,6 +5330,29 @@
 #define GL_MDCK_RX 0x0029422C /* Reset Source: 
CORER */
 #define GL_MDCK_RX_DESC_ADDR_S 0
 #define GL_MDCK_RX_DESC_ADDR_M BIT(0)
+#define GL_MDCK_TX_TDPU0x00049348 /* Reset 
Source: CORER */
+#define GL_MDCK_TX_TDPU_TTL_ERR_ITR_DIS_S  0
+#define GL_MDCK_TX_TDPU_TTL_ERR_ITR_DIS_M  BIT(0)
+#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_S 1
+#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_M BIT(1)
+#define GL_MDCK_TX_TDPU_PCIE_UR_ITR_DIS_S  2
+#define GL_MDCK_TX_TDPU_PCIE_UR_ITR_DIS_M  BIT(2)
+#define GL_MDCK_TX_TDPU_MAL_OFFSET_ITR_DIS_S   3
+#define GL_MDCK_TX_TDPU_MAL_OFFSET_ITR_DIS_M   BIT(3)
+#define GL_MDCK_TX_TDPU_MAL_CMD_ITR_DIS_S  4
+#define GL_MDCK_TX_TDPU_MAL_CMD_ITR_DIS_M  BIT(4)
+#define GL_MDCK_TX_TDPU_BIG_PKT_SIZE_ITR_DIS_S 5
+#define GL_MDCK_TX_TDPU_BIG_PKT_SIZE_ITR_DIS_M BIT(5)
+#define GL_MDCK_TX_TDPU_L2_ACCEPT_FAIL_ITR_DIS_S 6
+#define GL_MDCK_TX_TDPU_L2_ACCEPT_FAIL_ITR_DIS_M BIT(6)
+#define GL_MDCK_TX_TDPU_NIC_DSI_ITR_DIS_S  7
+#define GL_MDCK_TX_TDPU_NIC_DSI_ITR_DIS_M  BIT(7)
+#define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_S 8
+#define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_M BIT(8)
+#define GL_MDCK_TX_TDPU_DSCP_CHECK_FAIL_ITR_DIS_S 9
+#define GL_MDCK_TX_TDPU_DSCP_CHECK_FAIL_ITR_DIS_M BIT(9)
+#define GL_MDCK_TX_TDPU_NIC_IPSEC_ITR_DIS_S10
+#define GL_MDCK_TX_TDPU_NIC_IPSEC_ITR_DIS_MBIT(10)
 #define GL_MDET_RX 0x00294C00 /* Reset Source: 
CORER */
 #define GL_MDET_RX_QNUM_S  0
 #define GL_MDET_RX_QNUM_M  MAKEMASK(0x7FFF, 0)
@@ -5363,6 +5386,17 @@
 #define GL_MDET_TX_TCLAN_MAL_TYPE_MMAKEMASK(0x1F, 26)
 #define GL_MDET_TX_TCLAN_VALID_S   31
 #define GL_MDET_TX_TCLAN_VALID_M   BIT(31)
+#define GL_MDET_TX_TDPU0x00049350 /* Reset 
Source: CORER */
+#define GL_MDET_TX_TDPU_QNUM_S 0
+#define GL_MDET_TX_TDPU_QNUM_M MAKEMASK(0x7FFF, 0)
+#define GL_MDET_TX_TDPU_VF_NUM_S   15
+#define GL_MDET_TX_TDPU_VF_NUM_M   MAKEMASK(0xFF, 15)
+#define GL_MDET_TX_TDPU_PF_NUM_S   23
+#define GL_MDET_TX_TDPU_PF_NUM_M   MAKEMASK(0x7, 23)
+#define GL_MDET_TX_TDPU_MAL_TYPE_S 26
+#define GL_MDET_TX_TDPU_MAL_TYPE_M MAKEMASK(0x1F, 26)
+#define GL_MDET_TX_TDPU_VALID_S31
+#define GL_MDET_TX_TDPU_VALID_MBIT(31)
 #define GLRLAN_MDET0x00294200 /* Reset Source: 
CORER */
 #define GLRLAN_MDET_PCKT_EXTRCT_ERR_S  0
 #define GLRLAN_MDET_PCKT_EXTRCT_ERR_M  BIT(0)
-- 
2.13.6

[dpdk-dev] [PATCH 53/63] net/ice/base: remove unnecessary if branch

[Qi Zhang]

We are already in the branch "if (fm_list->vsi_count == 1)"
no need to exit and re-enter.

Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_switch.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/net/ice/base/ice_switch.c 
b/drivers/net/ice/base/ice_switch.c
index 063a26ec5..3ae53d3d8 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -6319,9 +6319,7 @@ ice_adv_rem_update_vsi_list(struct ice_hw *hw, u16 
vsi_handle,
  tmp_fltr.fwd_id.hw_vsi_id, status);
return status;
}
-   }
 
-   if (fm_list->vsi_count == 1) {
/* Remove the VSI list since it is no longer used */
status = ice_remove_vsi_list_rule(hw, vsi_list_id, lkup_type);
if (status) {
-- 
2.13.6

[dpdk-dev] [PATCH 57/63] net/ice/base: delay less

[Qi Zhang]

Shorten the delay for SQ responses, but increase the number of loops.
Max delay time is unchanged, but some operations complete much more
quickly.

In the process, add a new define to make the delay count and delay time
more explicit, and simplify the code so it's the same for both switch
and NIC mode. Add comments to make things more explicit.

Signed-off-by: Mitch Williams 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_controlq.c | 2 +-
 drivers/net/ice/base/ice_controlq.h | 5 +++--
 drivers/net/ice/base/ice_osdep.h| 2 +-
 3 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ice/base/ice_controlq.c 
b/drivers/net/ice/base/ice_controlq.c
index 501f986b9..1ea8f3a24 100644
--- a/drivers/net/ice/base/ice_controlq.c
+++ b/drivers/net/ice/base/ice_controlq.c
@@ -982,7 +982,7 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct 
ice_ctl_q_info *cq,
if (ice_sq_done(hw, cq))
break;
 
-   ice_msec_delay(1, false);
+   ice_usec_delay(ICE_CTL_Q_SQ_CMD_USEC, false);
total_delay++;
} while (total_delay < cq->sq_cmd_timeout);
 
diff --git a/drivers/net/ice/base/ice_controlq.h 
b/drivers/net/ice/base/ice_controlq.h
index acb4ab49e..b1214f670 100644
--- a/drivers/net/ice/base/ice_controlq.h
+++ b/drivers/net/ice/base/ice_controlq.h
@@ -33,8 +33,9 @@ enum ice_ctl_q {
ICE_CTL_Q_MAILBOX,
 };
 
-/* Control Queue default settings */
-#define ICE_CTL_Q_SQ_CMD_TIMEOUT   250  /* msecs */
+/* Control Queue timeout settings - max delay 250ms */
+#define ICE_CTL_Q_SQ_CMD_TIMEOUT   2500  /* Count 2500 times */
+#define ICE_CTL_Q_SQ_CMD_USEC  100   /* Check every 100usec */
 
 struct ice_ctl_q_ring {
void *dma_head; /* Virtual address to DMA head */
diff --git a/drivers/net/ice/base/ice_osdep.h b/drivers/net/ice/base/ice_osdep.h
index 35a17b941..27c1830c5 100644
--- a/drivers/net/ice/base/ice_osdep.h
+++ b/drivers/net/ice/base/ice_osdep.h
@@ -292,7 +292,7 @@ ice_hweight32(u32 num)
 
 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
 #define DELAY(x) rte_delay_us(x)
-#define ice_usec_delay(x) rte_delay_us(x)
+#define ice_usec_delay(x, y) rte_delay_us(x)
 #define ice_msec_delay(x, y) rte_delay_us(1000 * (x))
 #define udelay(x) DELAY(x)
 #define msleep(x) DELAY(1000 * (x))
-- 
2.13.6

[dpdk-dev] [PATCH 59/63] net/ice/base: remove Rx flex descriptor programming

[Qi Zhang]

Removing Rx flex descriptor metadata and flag programming from shared
code. As per HAS these registers cannot be written to as they are read
only. While non-secure NVMs allow write access to them, secure images
will not. The programming for all fields per RxDID is now handled in the
comms package.

Signed-off-by: Vignesh Sridhar 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_common.c | 195 --
 1 file changed, 195 deletions(-)

diff --git a/drivers/net/ice/base/ice_common.c 
b/drivers/net/ice/base/ice_common.c
index d2f903329..11e902ea1 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -11,35 +11,6 @@
 
 #define ICE_PF_RESET_WAIT_COUNT200
 
-#define ICE_PROG_FLEX_ENTRY(hw, rxdid, mdid, idx) \
-   wr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(rxdid), \
-((ICE_RX_OPC_MDID << \
-  GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \
- GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \
-(((mdid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \
- GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M))
-
-#define ICE_PROG_FLEX_ENTRY_EXTRACT(hw, rxdid, protid, off, idx) \
-   wr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(rxdid), \
-((ICE_RX_OPC_EXTRACT << \
-  GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \
- GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \
-(((protid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \
- GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M) | \
-(((off) << GLFLXP_RXDID_FLX_WRD_##idx##_EXTRACTION_OFFSET_S) & \
- GLFLXP_RXDID_FLX_WRD_##idx##_EXTRACTION_OFFSET_M))
-
-#define ICE_PROG_FLG_ENTRY(hw, rxdid, flg_0, flg_1, flg_2, flg_3, idx) \
-   wr32((hw), GLFLXP_RXDID_FLAGS(rxdid, idx), \
-(((flg_0) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) & \
- GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M) | \
-(((flg_1) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S) & \
- GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M) | \
-(((flg_2) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S) & \
- GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M) | \
-(((flg_3) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S) & \
- GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M))
-
 
 /**
  * ice_set_mac_type - Sets MAC type
@@ -431,163 +402,6 @@ ice_aq_get_link_info(struct ice_port_info *pi, bool 
ena_lse,
 }
 
 /**
- * ice_init_flex_flags
- * @hw: pointer to the hardware structure
- * @prof_id: Rx Descriptor Builder profile ID
- *
- * Function to initialize Rx flex flags
- */
-static void ice_init_flex_flags(struct ice_hw *hw, enum ice_rxdid prof_id)
-{
-   u8 idx = 0;
-
-   /* Flex-flag fields (0-2) are programmed with FLG64 bits with layout:
-* flexiflags0[5:0] - TCP flags, is_packet_fragmented, is_packet_UDP_GRE
-* flexiflags1[3:0] - Not used for flag programming
-* flexiflags2[7:0] - Tunnel and VLAN types
-* 2 invalid fields in last index
-*/
-   switch (prof_id) {
-   /* Rx flex flags are currently programmed for the NIC profiles only.
-* Different flag bit programming configurations can be added per
-* profile as needed.
-*/
-   case ICE_RXDID_FLEX_NIC:
-   case ICE_RXDID_FLEX_NIC_2:
-   ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_FRG,
-  ICE_FLG_UDP_GRE, ICE_FLG_PKT_DSI,
-  ICE_FLG_FIN, idx++);
-   /* flex flag 1 is not used for flexi-flag programming, skipping
-* these four FLG64 bits.
-*/
-   ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_SYN, ICE_FLG_RST,
-  ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx++);
-   ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_DSI,
-  ICE_FLG_PKT_DSI, ICE_FLG_EVLAN_x8100,
-  ICE_FLG_EVLAN_x9100, idx++);
-   ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_VLAN_x8100,
-  ICE_FLG_TNL_VLAN, ICE_FLG_TNL_MAC,
-  ICE_FLG_TNL0, idx++);
-   ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_TNL1, ICE_FLG_TNL2,
-  ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx);
-   break;
-
-   default:
-   ice_debug(hw, ICE_DBG_INIT,
- "Flag programming for profile ID %d not supported\n",
- prof_id);
-   }
-}
-
-/**
- * ice_init_flex_flds
- * @hw: pointer to the hardware structure
- * @prof_id: Rx Descriptor Builder profile ID
- *
- * Function to initialize flex descriptors
- */
-static void ice_init_flex_flds(struct ice_hw *hw, enum ice_rxdid prof_id)
-{
-   enum ice_prot_id protid_0, protid_1;
-   u16 offset_0, offset_1;
-   enum ice_flex_mdid mdid;
-
-   switch (p

[dpdk-dev] [PATCH 56/63] net/ice/base: replace open-code duplication

[Qi Zhang]

Use BIT_ULL() instead of ICE_FLOW_HASH_FLD() which does the same bit shift
operation.

Signed-off-by: Bruce Allan 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_flow.h | 24 +++-
 1 file changed, 11 insertions(+), 13 deletions(-)

diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h
index 0bb3efca0..2ec9bb022 100644
--- a/drivers/net/ice/base/ice_flow.h
+++ b/drivers/net/ice/base/ice_flow.h
@@ -14,24 +14,22 @@
 #define ICE_FLOW_VSI_INVAL 0x
 #define ICE_FLOW_FLD_OFF_INVAL 0x
 
-/* Use any of the type from flow field to generate a equivalent hash field */
-#define ICE_FLOW_HASH_FLD(t)   (1ULL << (t))
-
+/* Generate flow hash field from flow field type(s) */
 #define ICE_FLOW_HASH_IPV4 \
-   (ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_IPV4_SA) | \
-ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_IPV4_DA))
+   (BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_SA) | \
+BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_DA))
 #define ICE_FLOW_HASH_IPV6 \
-   (ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_IPV6_SA) | \
-ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_IPV6_DA))
+   (BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_SA) | \
+BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_DA))
 #define ICE_FLOW_HASH_TCP_PORT \
-   (ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_TCP_SRC_PORT) | \
-ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_TCP_DST_PORT))
+   (BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_SRC_PORT) | \
+BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_DST_PORT))
 #define ICE_FLOW_HASH_UDP_PORT \
-   (ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_UDP_SRC_PORT) | \
-ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_UDP_DST_PORT))
+   (BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_SRC_PORT) | \
+BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_DST_PORT))
 #define ICE_FLOW_HASH_SCTP_PORT\
-   (ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_SCTP_SRC_PORT) | \
-ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_SCTP_DST_PORT))
+   (BIT_ULL(ICE_FLOW_FIELD_IDX_SCTP_SRC_PORT) | \
+BIT_ULL(ICE_FLOW_FIELD_IDX_SCTP_DST_PORT))
 
 #define ICE_HASH_INVALID   0
 #define ICE_HASH_TCP_IPV4  (ICE_FLOW_HASH_IPV4 | ICE_FLOW_HASH_TCP_PORT)
-- 
2.13.6

[dpdk-dev] [PATCH 54/63] net/ice/base: correct abbreviations

[Qi Zhang]

Correct abbreviation issues found by running abbrevcheck.

Signed-off-by: Tony Nguyen 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_common.c|  4 ++--
 drivers/net/ice/base/ice_controlq.c  |  2 +-
 drivers/net/ice/base/ice_controlq.h  |  2 +-
 drivers/net/ice/base/ice_flex_pipe.c | 22 +++---
 drivers/net/ice/base/ice_flex_type.h |  2 +-
 drivers/net/ice/base/ice_flow.c  |  2 +-
 drivers/net/ice/base/ice_type.h  |  2 +-
 7 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/net/ice/base/ice_common.c 
b/drivers/net/ice/base/ice_common.c
index c2d4f1f05..feb7676f8 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -655,10 +655,10 @@ static void ice_cleanup_fltr_mgmt_struct(struct ice_hw 
*hw)
 
 
 /**
- * ice_get_itr_intrl_gran - determine int/intrl granularity
+ * ice_get_itr_intrl_gran
  * @hw: pointer to the HW struct
  *
- * Determines the itr/intrl granularities based on the maximum aggregate
+ * Determines the ITR/INTRL granularities based on the maximum aggregate
  * bandwidth according to the device's configuration during power-on.
  */
 static void ice_get_itr_intrl_gran(struct ice_hw *hw)
diff --git a/drivers/net/ice/base/ice_controlq.c 
b/drivers/net/ice/base/ice_controlq.c
index 70a50bff4..501f986b9 100644
--- a/drivers/net/ice/base/ice_controlq.c
+++ b/drivers/net/ice/base/ice_controlq.c
@@ -412,7 +412,7 @@ do {
\
/* free the buffer info list */ \
if ((qi)->ring.cmd_buf) \
ice_free(hw, (qi)->ring.cmd_buf);   \
-   /* free dma head */ \
+   /* free DMA head */ \
ice_free(hw, (qi)->ring.dma_head);  \
 } while (0)
 
diff --git a/drivers/net/ice/base/ice_controlq.h 
b/drivers/net/ice/base/ice_controlq.h
index 21c8722e5..acb4ab49e 100644
--- a/drivers/net/ice/base/ice_controlq.h
+++ b/drivers/net/ice/base/ice_controlq.h
@@ -37,7 +37,7 @@ enum ice_ctl_q {
 #define ICE_CTL_Q_SQ_CMD_TIMEOUT   250  /* msecs */
 
 struct ice_ctl_q_ring {
-   void *dma_head; /* Virtual address to dma head */
+   void *dma_head; /* Virtual address to DMA head */
struct ice_dma_mem desc_buf;/* descriptor ring memory */
void *cmd_buf;  /* command buffer memory */
 
diff --git a/drivers/net/ice/base/ice_flex_pipe.c 
b/drivers/net/ice/base/ice_flex_pipe.c
index 6ae71e698..4ad816874 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -1921,7 +1921,7 @@ ice_create_tunnel(struct ice_hw *hw, enum ice_tunnel_type 
type, u16 port)
if (!bld)
return ICE_ERR_NO_MEMORY;
 
-   /* allocate 2 sections, one for RX parser, one for TX parser */
+   /* allocate 2 sections, one for Rx parser, one for Tx parser */
if (ice_pkg_buf_reserve_section(bld, 2))
goto ice_create_tunnel_err;
 
@@ -1951,7 +1951,7 @@ ice_create_tunnel(struct ice_hw *hw, enum ice_tunnel_type 
type, u16 port)
offsetof(struct ice_boost_key_value, hv_dst_port_key),
sizeof(sect_rx->tcam[0].key.key.hv_dst_port_key));
 
-   /* exact copy of entry to TX section entry */
+   /* exact copy of entry to Tx section entry */
ice_memcpy(sect_tx->tcam, sect_rx->tcam, sizeof(*sect_tx->tcam),
   ICE_NONDMA_TO_NONDMA);
 
@@ -2002,7 +2002,7 @@ enum ice_status ice_destroy_tunnel(struct ice_hw *hw, u16 
port, bool all)
if (!bld)
return ICE_ERR_NO_MEMORY;
 
-   /* allocate 2 sections, one for RX parser, one for TX parser */
+   /* allocate 2 sections, one for Rx parser, one for Tx parser */
if (ice_pkg_buf_reserve_section(bld, 2))
goto ice_destroy_tunnel_err;
 
@@ -2020,8 +2020,8 @@ enum ice_status ice_destroy_tunnel(struct ice_hw *hw, u16 
port, bool all)
goto ice_destroy_tunnel_err;
sect_tx->count = CPU_TO_LE16(1);
 
-   /* copy original boost entry to update package buffer, one copy to RX
-* section, another copy to the TX section
+   /* copy original boost entry to update package buffer, one copy to Rx
+* section, another copy to the Tx section
 */
for (i = 0; i < hw->tnl.count && i < ICE_TUNNEL_MAX_ENTRIES; i++)
if (hw->tnl.tbl[i].valid && hw->tnl.tbl[i].in_use &&
@@ -2919,7 +2919,7 @@ ice_write_prof_mask_reg(struct ice_hw *hw, enum ice_block 
blk, u16 mask_idx,
  * ice_write_prof_mask_enable_res - write profile mask enable register
  * @hw: pointer to the HW struct
  * @blk: hardware block
- * @prof_id: profile id
+ * @prof_id: profile ID
  * @enable_mask: enabl

[dpdk-dev] [PATCH 58/63] net/ice/base: add AQC get link topology handle support

[Qi Zhang]

Add AQC get link topology handle support. This is needed to determine
Direct Attach (DA) or backplane media type for PHY types that support
either. Get link topology handle cage node type request can be used to
determine if a cage is present or not. If a cage is present for PHY
types that supports both DA and backplane media type, then the media
type is DA, else the media type is backplane.

Signed-off-by: Paul Greenwalt 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_adminq_cmd.h | 52 +++
 drivers/net/ice/base/ice_common.c | 68 ++-
 2 files changed, 119 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ice/base/ice_adminq_cmd.h 
b/drivers/net/ice/base/ice_adminq_cmd.h
index 9a063592f..8e1d6a07d 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -1654,6 +1654,56 @@ struct ice_aqc_set_mac_lb {
 
 
 
+struct ice_aqc_link_topo_addr {
+   u8 lport_num;
+   u8 lport_num_valid;
+#define ICE_AQC_LINK_TOPO_PORT_NUM_VALID   BIT(0)
+   u8 node_type_ctx;
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_S  0
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_M  (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S)
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY0
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL  1
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL   2
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL   3
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_LED4
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL5
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE   6
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ   7
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM  8
+#define ICE_AQC_LINK_TOPO_NODE_CTX_S   4
+#define ICE_AQC_LINK_TOPO_NODE_CTX_M   \
+   (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S)
+#define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL  0
+#define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD   1
+#define ICE_AQC_LINK_TOPO_NODE_CTX_PORT2
+#define ICE_AQC_LINK_TOPO_NODE_CTX_NODE3
+#define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED4
+#define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE5
+   u8 index;
+   __le16 handle;
+#define ICE_AQC_LINK_TOPO_HANDLE_S 0
+#define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S)
+/* Used to decode the handle field */
+#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MBIT(9)
+#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM  BIT(9)
+#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0
+#define ICE_AQC_LINK_TOPO_HANDLE_NODE_S0
+/* In case of a Mezzanine type */
+#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M   \
+   (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
+#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S6
+#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M(0x7 << 
ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S)
+/* In case of a LOM type */
+#define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M\
+   (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
+};
+
+/* Get Link Topology Handle (direct, 0x06E0) */
+struct ice_aqc_get_link_topo {
+   struct ice_aqc_link_topo_addr addr;
+   u8 node_part_num;
+   u8 rsvd[9];
+};
 
 /* Set Port Identification LED (direct, 0x06E9) */
 struct ice_aqc_set_port_id_led {
@@ -2307,6 +2357,7 @@ struct ice_aq_desc {
struct ice_aqc_set_event_mask set_event_mask;
struct ice_aqc_get_link_status get_link_status;
struct ice_aqc_event_lan_overflow lan_overflow;
+   struct ice_aqc_get_link_topo get_link_topo;
} params;
 };
 
@@ -2470,6 +2521,7 @@ enum ice_adminq_opc {
ice_aqc_opc_get_link_status = 0x0607,
ice_aqc_opc_set_event_mask  = 0x0613,
ice_aqc_opc_set_mac_lb  = 0x0620,
+   ice_aqc_opc_get_link_topo   = 0x06E0,
ice_aqc_opc_set_port_id_led = 0x06E9,
ice_aqc_opc_get_port_options= 0x06EA,
ice_aqc_opc_set_port_option = 0x06EB,
diff --git a/drivers/net/ice/base/ice_common.c 
b/drivers/net/ice/base/ice_common.c
index feb7676f8..d2f903329 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -188,6 +188,59 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool 
qual_mods, u8 report_mode,
 }
 
 /**
+ * ice_aq_get_link_topo_handle - get link topology node return status
+ * @pi: port information structure
+ * @node_type: requested node type
+ * @cd: pointer to command details structure or NULL
+ *
+ * Get link topology node return status for specified node type (0x06E0)
+ *
+ * Node type cage can be used to determine if cage is present. If AQC
+ * returns error (ENOENT), then no cage present. If no cage present, then
+ * connection type is backplane or BASE-T.
+ */
+static enum ice_status
+ice_aq_get_link_to

[dpdk-dev] [PATCH 60/63] net/ice/base: enable RSS with ether layer for PPPoE

[Qi Zhang]

Add these two ptype(MAC_PPPOD_PAY and MAC_PPPOE_PAY) in outer mac
bitmap, so it can hash for outer mac.

Signed-off-by: Zhirun Yan 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_flow.c | 8 ++--
 drivers/net/ice/base/ice_flow.h | 5 +
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index abdf10b94..769fd2da7 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -143,7 +143,7 @@ struct ice_flow_field_info 
ice_flds_info[ICE_FLOW_FIELD_IDX_MAX] = {
 static const u32 ice_ptypes_mac_ofos[] = {
0xFDC00CC6, 0xBFBF7F7E, 0xF7EFDFDF, 0xFEFDFDFB,
0x03BF7F7E, 0x, 0x, 0x,
-   0x000B0F0F, 0x, 0x, 0x,
+   0x000B0F0F, 0x3000, 0x, 0x,
0x, 0x, 0x, 0x,
0x, 0x, 0x, 0x,
0x, 0x, 0x, 0x,
@@ -1682,6 +1682,9 @@ ice_flow_add_fld_raw(struct ice_flow_seg_info *seg, u16 
off, u8 len,
seg->raws_cnt++;
 }
 
+#define ICE_FLOW_RSS_SEG_HDR_L2_MASKS \
+(ICE_FLOW_SEG_HDR_ETH | ICE_FLOW_SEG_HDR_VLAN)
+
 #define ICE_FLOW_RSS_SEG_HDR_L3_MASKS \
(ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_PPPOE)
 
@@ -1692,7 +1695,8 @@ ice_flow_add_fld_raw(struct ice_flow_seg_info *seg, u16 
off, u8 len,
 
 
 #define ICE_FLOW_RSS_SEG_HDR_VAL_MASKS \
-   (ICE_FLOW_RSS_SEG_HDR_L3_MASKS | \
+   (ICE_FLOW_RSS_SEG_HDR_L2_MASKS | \
+ICE_FLOW_RSS_SEG_HDR_L3_MASKS | \
 ICE_FLOW_RSS_SEG_HDR_L4_MASKS)
 
 /**
diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h
index 2ec9bb022..3afd201c4 100644
--- a/drivers/net/ice/base/ice_flow.h
+++ b/drivers/net/ice/base/ice_flow.h
@@ -15,6 +15,9 @@
 #define ICE_FLOW_FLD_OFF_INVAL 0x
 
 /* Generate flow hash field from flow field type(s) */
+#define ICE_FLOW_HASH_ETH  \
+   (BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_DA) | \
+BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_SA))
 #define ICE_FLOW_HASH_IPV4 \
(BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_SA) | \
 BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_DA))
@@ -58,6 +61,8 @@
 #define ICE_FLOW_HASH_PPPOE_SESS_ID \
(BIT_ULL(ICE_FLOW_FIELD_IDX_PPPOE_SESS_ID))
 
+#define ICE_FLOW_HASH_PPPOE_SESS_ID_ETH \
+   (ICE_FLOW_HASH_ETH | ICE_FLOW_HASH_PPPOE_SESS_ID)
 #define ICE_FLOW_HASH_PPPOE_TCP_ID \
(ICE_FLOW_HASH_TCP_PORT | ICE_FLOW_HASH_PPPOE_SESS_ID)
 #define ICE_FLOW_HASH_PPPOE_UDP_ID \
-- 
2.13.6

Re: [dpdk-dev] [PATCH 0/2] IXGBE vPMD changes for aarch64

[Ruifeng Wang (Arm Technology China)]

> -Original Message-
> From: Ferruh Yigit 
> Sent: Monday, August 26, 2019 18:40
> To: Ruifeng Wang (Arm Technology China) ; Ye
> Xiaolong 
> Cc: jer...@marvell.com; Gavin Hu (Arm Technology China)
> ; dev@dpdk.org; Honnappa Nagarahalli
> ; nd ; Kevin Traynor
> ; Luca Boccassi 
> Subject: Re: [dpdk-dev] [PATCH 0/2] IXGBE vPMD changes for aarch64
> 
> On 8/26/2019 3:52 AM, Ruifeng Wang (Arm Technology China) wrote:
> > Hi Xiaolong,
> >
> >> -Original Message-
> >> From: Ye Xiaolong 
> >> Sent: Sunday, August 25, 2019 09:34
> >> To: Ruifeng Wang (Arm Technology China) 
> >> Cc: jer...@marvell.com; Gavin Hu (Arm Technology China)
> >> ; dev@dpdk.org; Honnappa Nagarahalli
> >> ; nd 
> >> Subject: Re: [dpdk-dev] [PATCH 0/2] IXGBE vPMD changes for aarch64
> >>
> >> Hi,
> >>
> >> Thanks for the patches, could you also provide the Fixes tag and cc stable?
> >> The patchset looks good to me.
> >
> > Code changes in both patches are not for bug fixing.
> > Patch 1/2 includes fix for code comments. I don't think it deserves a Fixes
> tag or backporting. Can we skip the Fixes tag?
> 
> In 1/2 a memory barrier is removed, it means it was wrong to add it at first
> place and you are fixing it, no?
> 
> 
> Performance improvements are in gray are, but if there is no ABI/API break
> why not take is performance fix and backport and have the performance
> improvement in LTS?
> Also I think taking as much as possible may help to maintain LTS, since it
> reduces the chance of conflict in later commits, LTS is two years and these
> small things can accumulate and make getting important fixes hard by time.
> 
> Is there any specific reason not to backport these patches to LTS releases?
> 
Thanks for your explanation.
Understand that. No objection to backporting.
I'll send out new version.

> 
> >
> >>
> >> Thanks,
> >> Xiaolong
> >>
> >> On 08/13, Ruifeng Wang wrote:
> >>> Couple of changes to IXGBE vector PMD on aarch64 platform.
> >>> An unnecessary memory barrier was identified and removed.
> >>> Also part of processing was replaced with NEON intrinsics.
> >>> Both of the changes will help to improve performance.
> >>>
> >>> Ruifeng Wang (2):
> >>>  net/ixgbe: remove barrier in vPMD for aarch64
> >>>  net/ixgbe: use neon intrinsics to count packet for aarch64
> >>>
> >>> drivers/net/ixgbe/ixgbe_rxtx_vec_neon.c | 32
> >>> -
> >>> 1 file changed, 16 insertions(+), 16 deletions(-)
> >>>
> >>> --
> >>> 2.17.1
> >>>

[dpdk-dev] [PATCH 62/63] net/ice/base: update profile to recipe bitmap array

[Qi Zhang]

Correctly update profile to recipe bitmap array after adding and
associating recipes. This fixes an issue where determining unused
recipe result index slots was incorrect.

Signed-off-by: Dan Nowlin 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_switch.c | 21 ++---
 1 file changed, 18 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ice/base/ice_switch.c 
b/drivers/net/ice/base/ice_switch.c
index 8f20b9ed6..59da7eaa8 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -594,11 +594,14 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct 
ice_sw_recipe *recps, u8 rid,
/* Propagate some data to the recipe database */
recps[idx].is_root = is_root;
recps[idx].priority = root_bufs.content.act_ctrl_fwd_priority;
-   if (root_bufs.content.result_indx & ICE_AQ_RECIPE_RESULT_EN)
+   ice_zero_bitmap(recps[idx].res_idxs, ICE_MAX_FV_WORDS);
+   if (root_bufs.content.result_indx & ICE_AQ_RECIPE_RESULT_EN) {
recps[idx].chain_idx = root_bufs.content.result_indx &
~ICE_AQ_RECIPE_RESULT_EN;
-   else
+   ice_set_bit(recps[idx].chain_idx, recps[idx].res_idxs);
+   } else {
recps[idx].chain_idx = ICE_INVAL_CHAIN_IND;
+   }
 
if (!is_root)
continue;
@@ -609,11 +612,11 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct 
ice_sw_recipe *recps, u8 rid,
recps[idx].root_rid = root_bufs.content.rid &
~ICE_AQ_RECIPE_ID_IS_ROOT;
recps[idx].priority = root_bufs.content.act_ctrl_fwd_priority;
-   recps[idx].big_recp = (recps[rid].n_grp_count > 1);
}
 
/* Complete initialization of the root recipe entry */
lkup_exts->n_val_words = fv_word_idx;
+   recps[rid].big_recp = (num_recps > 1);
recps[rid].n_grp_count = num_recps;
recps[rid].root_buf = (struct ice_aqc_recipe_data_elem *)
ice_calloc(hw, recps[rid].n_grp_count,
@@ -5287,6 +5290,7 @@ ice_add_sw_recipe(struct ice_hw *hw, struct ice_sw_recipe 
*rm,
recp->n_ext_words = entry->r_group.n_val_pairs;
recp->chain_idx = entry->chain_idx;
recp->priority = buf[buf_idx].content.act_ctrl_fwd_priority;
+   recp->n_grp_count = rm->n_grp_count;
recp->tun_type = rm->tun_type;
recp->recp_created = true;
recp->adv_rule = 1;
@@ -5568,6 +5572,7 @@ ice_add_adv_recipe(struct ice_hw *hw, struct 
ice_adv_lkup_elem *lkups,
LIST_FOR_EACH_ENTRY(fvit, &rm->fv_list, ice_sw_fv_list_entry,
list_entry) {
ice_declare_bitmap(r_bitmap, ICE_MAX_NUM_RECIPES);
+   u16 j;
 
status = ice_aq_get_recipe_to_profile(hw, fvit->profile_id,
  (u8 *)r_bitmap, NULL);
@@ -5587,6 +5592,16 @@ ice_add_adv_recipe(struct ice_hw *hw, struct 
ice_adv_lkup_elem *lkups,
 
if (status)
goto err_unroll;
+
+   /* Update profile to recipe bitmap array */
+   ice_memcpy(profile_to_recipe[fvit->profile_id], rm->r_bitmap,
+  sizeof(rm->r_bitmap), ICE_NONDMA_TO_NONDMA);
+
+   /* Update recipe to profile bitmap array */
+   for (j = 0; j < ICE_MAX_NUM_RECIPES; j++)
+   if (ice_is_bit_set(rm->r_bitmap, j))
+   ice_set_bit((u16)fvit->profile_id,
+   recipe_to_profile[j]);
}
 
*rid = rm->root_rid;
-- 
2.13.6

[dpdk-dev] [PATCH 63/63] net/ice/base: ignore inverse switch recipes

[Qi Zhang]

When looking for an existing recipes, never choose an inverse
recipe as these are used for anti-spoofing. Choosing inverse
recipes for source MAC address rules was causing errors while
adding the rule.

Signed-off-by: Dan Nowlin 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_switch.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/net/ice/base/ice_switch.c 
b/drivers/net/ice/base/ice_switch.c
index 59da7eaa8..2437faead 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -4709,6 +4709,11 @@ static u16 ice_find_recp(struct ice_hw *hw, struct 
ice_prot_lkup_ext *lkup_exts)
&refresh_required))
continue;
 
+   /* Skip inverse action recipes */
+   if (recp[i].root_buf && recp[i].root_buf->content.act_ctrl &
+   ICE_AQ_RECIPE_ACT_INV_ACT)
+   continue;
+
/* if number of words we are looking for match */
if (lkup_exts->n_val_words == recp[i].lkup_exts.n_val_words) {
struct ice_fv_word *a = lkup_exts->fv_words;
-- 
2.13.6

[dpdk-dev] [PATCH 61/63] net/ice/base: add GENEVE offset

[Qi Zhang]

Add Geneve offset for tunneled packets to allow dummy packets to be
properly created.

Signed-off-by: Doug Dziggel 
Signed-off-by: Paul M Stillwell Jr 
Signed-off-by: Qi Zhang 
---
 drivers/net/ice/base/ice_switch.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/ice/base/ice_switch.c 
b/drivers/net/ice/base/ice_switch.c
index 3ae53d3d8..8f20b9ed6 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -156,6 +156,7 @@ struct ice_dummy_pkt_offsets 
dummy_udp_tun_tcp_packet_offsets[] = {
{ ICE_IPV4_OFOS,14 },
{ ICE_UDP_OF,   34 },
{ ICE_VXLAN,42 },
+   { ICE_GENEVE,   42 },
{ ICE_MAC_IL,   50 },
{ ICE_IPV4_IL,  64 },
{ ICE_TCP_IL,   84 },
@@ -207,6 +208,7 @@ struct ice_dummy_pkt_offsets 
dummy_udp_tun_udp_packet_offsets[] = {
{ ICE_IPV4_OFOS,14 },
{ ICE_UDP_OF,   34 },
{ ICE_VXLAN,42 },
+   { ICE_GENEVE,   42 },
{ ICE_MAC_IL,   50 },
{ ICE_IPV4_IL,  64 },
{ ICE_UDP_ILOS, 84 },
-- 
2.13.6

[dpdk-dev] [PATCH v1] net/memif: optimized with one-way barrier

[Phil Yang]

Using 'rte_mb' to synchronize the shared ring head/tail between producer
and consumer will stall the pipeline and damage performance on the weak
memory model platforms, such like aarch64. Meanwhile update the shared
ring head and tail are observable and ordered between CPUs on IA.

Optimized this full barrier with the one-way barrier can improve the
throughput. On aarch64 n1sdp server this patch make testpmd throughput
boost 2.1%. On Intel E5-2640, testpmd got 3.98% performance gain.

Signed-off-by: Phil Yang 
Reviewed-by: Gavin Hu 
---
 drivers/net/memif/memif.h |  4 +--
 drivers/net/memif/rte_eth_memif.c | 53 +--
 2 files changed, 31 insertions(+), 26 deletions(-)

diff --git a/drivers/net/memif/memif.h b/drivers/net/memif/memif.h
index 3948b1f..a4d88c0 100644
--- a/drivers/net/memif/memif.h
+++ b/drivers/net/memif/memif.h
@@ -169,9 +169,9 @@ typedef struct {
uint32_t cookie;/**< MEMIF_COOKIE */
uint16_t flags; /**< flags */
 #define MEMIF_RING_FLAG_MASK_INT 1 /**< disable interrupt mode */
-   volatile uint16_t head; /**< pointer to ring buffer 
head */
+   uint16_t head;  /**< pointer to ring buffer head */
MEMIF_CACHELINE_ALIGN_MARK(cacheline1);
-   volatile uint16_t tail; /**< pointer to ring buffer 
tail */
+   uint16_t tail;  /**< pointer to ring buffer tail */
MEMIF_CACHELINE_ALIGN_MARK(cacheline2);
memif_desc_t desc[0];   /**< buffer descriptors */
 } memif_ring_t;
diff --git a/drivers/net/memif/rte_eth_memif.c 
b/drivers/net/memif/rte_eth_memif.c
index a59f809..b1c871e 100644
--- a/drivers/net/memif/rte_eth_memif.c
+++ b/drivers/net/memif/rte_eth_memif.c
@@ -275,8 +275,14 @@ eth_memif_rx(void *queue, struct rte_mbuf **bufs, uint16_t 
nb_pkts)
ring_size = 1 << mq->log2_ring_size;
mask = ring_size - 1;
 
-   cur_slot = (type == MEMIF_RING_S2M) ? mq->last_head : mq->last_tail;
-   last_slot = (type == MEMIF_RING_S2M) ? ring->head : ring->tail;
+   if (type == MEMIF_RING_S2M) {
+   cur_slot = mq->last_head;
+   last_slot = __atomic_load_n(&ring->head, __ATOMIC_ACQUIRE);
+   } else {
+   cur_slot = mq->last_tail;
+   last_slot = __atomic_load_n(&ring->tail, __ATOMIC_ACQUIRE);
+   }
+
if (cur_slot == last_slot)
goto refill;
n_slots = last_slot - cur_slot;
@@ -344,8 +350,7 @@ eth_memif_rx(void *queue, struct rte_mbuf **bufs, uint16_t 
nb_pkts)
 
 no_free_bufs:
if (type == MEMIF_RING_S2M) {
-   rte_mb();
-   ring->tail = cur_slot;
+   __atomic_store_n(&ring->tail, cur_slot, __ATOMIC_RELEASE);
mq->last_head = cur_slot;
} else {
mq->last_tail = cur_slot;
@@ -353,7 +358,7 @@ eth_memif_rx(void *queue, struct rte_mbuf **bufs, uint16_t 
nb_pkts)
 
 refill:
if (type == MEMIF_RING_M2S) {
-   head = ring->head;
+   head = __atomic_load_n(&ring->head, __ATOMIC_ACQUIRE);
n_slots = ring_size - head + mq->last_tail;
 
while (n_slots--) {
@@ -361,8 +366,7 @@ eth_memif_rx(void *queue, struct rte_mbuf **bufs, uint16_t 
nb_pkts)
d0 = &ring->desc[s0];
d0->length = pmd->run.pkt_buffer_size;
}
-   rte_mb();
-   ring->head = head;
+   __atomic_store_n(&ring->head, head, __ATOMIC_RELEASE);
}
 
mq->n_pkts += n_rx_pkts;
@@ -398,14 +402,16 @@ eth_memif_tx(void *queue, struct rte_mbuf **bufs, 
uint16_t nb_pkts)
ring_size = 1 << mq->log2_ring_size;
mask = ring_size - 1;
 
-   n_free = ring->tail - mq->last_tail;
+   n_free = __atomic_load_n(&ring->tail, __ATOMIC_ACQUIRE) - mq->last_tail;
mq->last_tail += n_free;
-   slot = (type == MEMIF_RING_S2M) ? ring->head : ring->tail;
 
-   if (type == MEMIF_RING_S2M)
-   n_free = ring_size - ring->head + mq->last_tail;
-   else
-   n_free = ring->head - ring->tail;
+   if (type == MEMIF_RING_S2M) {
+   slot = __atomic_load_n(&ring->head, __ATOMIC_ACQUIRE);
+   n_free = ring_size - slot + mq->last_tail;
+   } else {
+   slot = __atomic_load_n(&ring->tail, __ATOMIC_ACQUIRE);
+   n_free = __atomic_load_n(&ring->head, __ATOMIC_ACQUIRE) - slot;
+   }
 
while (n_tx_pkts < nb_pkts && n_free) {
mbuf_head = *bufs++;
@@ -464,11 +470,10 @@ eth_memif_tx(void *queue, struct rte_mbuf **bufs, 
uint16_t nb_pkts)
}
 
 no_free_slots:
-   rte_mb();
if (type == MEMIF_RING_S2M)
-   ring->head = slot;
+   __atomic_store_n(&ring->head, slot, __ATOMIC_RELEASE);
else
-   ring->tail = slot;
+   

Re: [dpdk-dev] [PATCH v1] net/memif: optimized with one-way barrier

[Phil Yang (Arm Technology China)]

+ Gavin

> -Original Message-
> From: dev  On Behalf Of Phil Yang
> Sent: Monday, August 26, 2019 7:00 PM
> To: jgraj...@cisco.com; dev@dpdk.org
> Cc: tho...@monjalon.net; jer...@marvell.com; Honnappa Nagarahalli
> ; damar...@cisco.com; nd
> 
> Subject: [dpdk-dev] [PATCH v1] net/memif: optimized with one-way barrier
> 
> Using 'rte_mb' to synchronize the shared ring head/tail between producer
> and consumer will stall the pipeline and damage performance on the weak
> memory model platforms, such like aarch64. Meanwhile update the shared
> ring head and tail are observable and ordered between CPUs on IA.
> 
> Optimized this full barrier with the one-way barrier can improve the
> throughput. On aarch64 n1sdp server this patch make testpmd throughput
> boost 2.1%. On Intel E5-2640, testpmd got 3.98% performance gain.
> 
> Signed-off-by: Phil Yang 
> Reviewed-by: Gavin Hu 
> ---
>  drivers/net/memif/memif.h |  4 +--
>  drivers/net/memif/rte_eth_memif.c | 53 +
> --
>  2 files changed, 31 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/net/memif/memif.h b/drivers/net/memif/memif.h
> index 3948b1f..a4d88c0 100644
> --- a/drivers/net/memif/memif.h
> +++ b/drivers/net/memif/memif.h
> @@ -169,9 +169,9 @@ typedef struct {
>   uint32_t cookie;/**< MEMIF_COOKIE */
>   uint16_t flags; /**< flags */
>  #define MEMIF_RING_FLAG_MASK_INT 1   /**< disable interrupt
> mode */
> - volatile uint16_t head; /**< pointer to ring buffer
> head */
> + uint16_t head;  /**< pointer to ring buffer head */
>   MEMIF_CACHELINE_ALIGN_MARK(cacheline1);
> - volatile uint16_t tail; /**< pointer to ring buffer
> tail */
> + uint16_t tail;  /**< pointer to ring buffer tail */
>   MEMIF_CACHELINE_ALIGN_MARK(cacheline2);
>   memif_desc_t desc[0];   /**< buffer descriptors */
>  } memif_ring_t;
> diff --git a/drivers/net/memif/rte_eth_memif.c
> b/drivers/net/memif/rte_eth_memif.c
> index a59f809..b1c871e 100644
> --- a/drivers/net/memif/rte_eth_memif.c
> +++ b/drivers/net/memif/rte_eth_memif.c
> @@ -275,8 +275,14 @@ eth_memif_rx(void *queue, struct rte_mbuf **bufs,
> uint16_t nb_pkts)
>   ring_size = 1 << mq->log2_ring_size;
>   mask = ring_size - 1;
> 
> - cur_slot = (type == MEMIF_RING_S2M) ? mq->last_head : mq-
> >last_tail;
> - last_slot = (type == MEMIF_RING_S2M) ? ring->head : ring->tail;
> + if (type == MEMIF_RING_S2M) {
> + cur_slot = mq->last_head;
> + last_slot = __atomic_load_n(&ring->head,
> __ATOMIC_ACQUIRE);
> + } else {
> + cur_slot = mq->last_tail;
> + last_slot = __atomic_load_n(&ring->tail,
> __ATOMIC_ACQUIRE);
> + }
> +
>   if (cur_slot == last_slot)
>   goto refill;
>   n_slots = last_slot - cur_slot;
> @@ -344,8 +350,7 @@ eth_memif_rx(void *queue, struct rte_mbuf **bufs,
> uint16_t nb_pkts)
> 
>  no_free_bufs:
>   if (type == MEMIF_RING_S2M) {
> - rte_mb();
> - ring->tail = cur_slot;
> + __atomic_store_n(&ring->tail, cur_slot,
> __ATOMIC_RELEASE);
>   mq->last_head = cur_slot;
>   } else {
>   mq->last_tail = cur_slot;
> @@ -353,7 +358,7 @@ eth_memif_rx(void *queue, struct rte_mbuf **bufs,
> uint16_t nb_pkts)
> 
>  refill:
>   if (type == MEMIF_RING_M2S) {
> - head = ring->head;
> + head = __atomic_load_n(&ring->head,
> __ATOMIC_ACQUIRE);
>   n_slots = ring_size - head + mq->last_tail;
> 
>   while (n_slots--) {
> @@ -361,8 +366,7 @@ eth_memif_rx(void *queue, struct rte_mbuf **bufs,
> uint16_t nb_pkts)
>   d0 = &ring->desc[s0];
>   d0->length = pmd->run.pkt_buffer_size;
>   }
> - rte_mb();
> - ring->head = head;
> + __atomic_store_n(&ring->head, head, __ATOMIC_RELEASE);
>   }
> 
>   mq->n_pkts += n_rx_pkts;
> @@ -398,14 +402,16 @@ eth_memif_tx(void *queue, struct rte_mbuf
> **bufs, uint16_t nb_pkts)
>   ring_size = 1 << mq->log2_ring_size;
>   mask = ring_size - 1;
> 
> - n_free = ring->tail - mq->last_tail;
> + n_free = __atomic_load_n(&ring->tail, __ATOMIC_ACQUIRE) - mq-
> >last_tail;
>   mq->last_tail += n_free;
> - slot = (type == MEMIF_RING_S2M) ? ring->head : ring->tail;
> 
> - if (type == MEMIF_RING_S2M)
> - n_free = ring_size - ring->head + mq->last_tail;
> - else
> - n_free = ring->head - ring->tail;
> + if (type == MEMIF_RING_S2M) {
> + slot = __atomic_load_n(&ring->head, __ATOMIC_ACQUIRE);
> + n_free = ring_size - slot + mq->last_tail;
> + } else {
> + slot = __atomic_load_n(&ring->tail, __ATOMIC_ACQUIRE);
> + n_free = __atomic_load_n(&ring->head,
> __ATOMIC_ACQUIRE) - s

[dpdk-dev] [PATCH v1] net/ixgbe: fix Rx/Tx queue interrupt for X552/557 devices

[junyux . jiang]

From: Jiang JunyuX 

X552/557 devices don't map interrupt vector before
enabling Rx/Tx queue interrupt.

Fixes: d2e72774e58c ("ixgbe/base: support X550")

Signed-off-by: Jiang JunyuX 
---
 drivers/net/ixgbe/ixgbe_ethdev.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c
index 03fc1f717..e36e1c58e 100644
--- a/drivers/net/ixgbe/ixgbe_ethdev.c
+++ b/drivers/net/ixgbe/ixgbe_ethdev.c
@@ -5896,7 +5896,8 @@ ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
} else if ((hw->mac.type == ixgbe_mac_82599EB) ||
(hw->mac.type == ixgbe_mac_X540) ||
-   (hw->mac.type == ixgbe_mac_X550)) {
+   (hw->mac.type == ixgbe_mac_X550) ||
+   (hw->mac.type == ixgbe_mac_X550EM_x)) {
if (direction == -1) {
/* other causes */
idx = ((queue & 1) * 8);
@@ -6026,6 +6027,7 @@ ixgbe_configure_msix(struct rte_eth_dev *dev)
case ixgbe_mac_82599EB:
case ixgbe_mac_X540:
case ixgbe_mac_X550:
+   case ixgbe_mac_X550EM_x:
ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
break;
default:
-- 
2.17.1

Re: [dpdk-dev] [PATCH] net/null: replace BSD text with SPDX id

[Ferruh Yigit]

On 8/26/2019 4:15 AM, Takanari Hayama wrote:
> 
> On 2019/08/26 10:07, Tetsuya Mukawa wrote:
>> 2019年8月17日(土) 5:43 Stephen Hemminger :
>>>
>>> Replace the boilerplate BSD license text with the equivalent
>>> SPDX license id.
>>>
>>> Signed-off-by: Stephen Hemminger 
>>> Acked-by: Tetsuya Mukawa 
> 
> Acked-by: Takanari Hayama 
> 
>>> ---
>>>  drivers/net/null/rte_eth_null.c | 34 +++--
>>>  1 file changed, 3 insertions(+), 31 deletions(-)
>>>
>>> diff --git a/drivers/net/null/rte_eth_null.c 
>>> b/drivers/net/null/rte_eth_null.c
>>> index b2c92ab72aec..0c60d241ac19 100644
>>> --- a/drivers/net/null/rte_eth_null.c
>>> +++ b/drivers/net/null/rte_eth_null.c
>>> @@ -1,34 +1,6 @@
>>> -/*-
>>> - *   BSD LICENSE
>>> - *
>>> - *   Copyright (C) IGEL Co.,Ltd.
>>> - *   All rights reserved.
>>> - *
>>> - *   Redistribution and use in source and binary forms, with or without
>>> - *   modification, are permitted provided that the following conditions
>>> - *   are met:
>>> - *
>>> - * * Redistributions of source code must retain the above copyright
>>> - *   notice, this list of conditions and the following disclaimer.
>>> - * * Redistributions in binary form must reproduce the above copyright
>>> - *   notice, this list of conditions and the following disclaimer in
>>> - *   the documentation and/or other materials provided with the
>>> - *   distribution.
>>> - * * Neither the name of IGEL Co.,Ltd. nor the names of its
>>> - *   contributors may be used to endorse or promote products derived
>>> - *   from this software without specific prior written permission.
>>> - *
>>> - *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
>>> - *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
>>> - *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
>>> - *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
>>> - *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
>>> - *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
>>> - *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
>>> - *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
>>> - *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
>>> - *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
>>> - *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>>> +/* SPDX-License-Identifier: BSD-3-Clause
>>> + * Copyright (C) IGEL Co.,Ltd.
>>> + *  All rights reserved.
>>>   */
>>>
>>>  #include 
>>> --
>>> 2.20.1
>>>
>>
>> I've already moved to other company.
>> I'm not sure you need 'acked' from me or IGEL.
>> Anyway, I added acked below, also Hayama-san will send 'acked' too.
>>
>> Acked-by: Tetsuya Mukawa 

Applied to dpdk-next-net/master, thanks.

[dpdk-dev] [PATCH v4 01/11] crypto/nitrox: add Nitrox build and doc skeleton

[Nagadheeraj Rottela]

Add bare minimum Nitrox PMD library and doc build infrastructure and
claim responsibility by updating the maintainers file.

Signed-off-by: Nagadheeraj Rottela 
---
 MAINTAINERS  |  7 ++
 config/common_base   |  5 +
 doc/guides/cryptodevs/index.rst  |  1 +
 doc/guides/cryptodevs/nitrox.rst | 11 ++
 drivers/crypto/Makefile  |  1 +
 drivers/crypto/meson.build   |  4 ++--
 drivers/crypto/nitrox/Makefile   | 28 
 drivers/crypto/nitrox/meson.build| 13 +++
 drivers/crypto/nitrox/nitrox_device.c|  3 +++
 drivers/crypto/nitrox/rte_pmd_nitrox_version.map |  3 +++
 mk/rte.app.mk|  1 +
 11 files changed, 75 insertions(+), 2 deletions(-)
 create mode 100644 doc/guides/cryptodevs/nitrox.rst
 create mode 100644 drivers/crypto/nitrox/Makefile
 create mode 100644 drivers/crypto/nitrox/meson.build
 create mode 100644 drivers/crypto/nitrox/nitrox_device.c
 create mode 100644 drivers/crypto/nitrox/rte_pmd_nitrox_version.map

diff --git a/MAINTAINERS b/MAINTAINERS
index 410026086..8a865b73f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -965,6 +965,13 @@ F: drivers/crypto/mvsam/
 F: doc/guides/cryptodevs/mvsam.rst
 F: doc/guides/cryptodevs/features/mvsam.ini
 
+Nitrox
+M: Nagadheeraj Rottela 
+M: Srikanth Jampala 
+F: drivers/crypto/nitrox/
+F: doc/guides/cryptodevs/nitrox.rst
+F: doc/guides/cryptodevs/features/nitrox.ini
+
 Null Crypto
 M: Declan Doherty 
 F: drivers/crypto/null/
diff --git a/config/common_base b/config/common_base
index 8ef75c203..92ecb4a68 100644
--- a/config/common_base
+++ b/config/common_base
@@ -664,6 +664,11 @@ CONFIG_RTE_LIBRTE_PMD_CCP=n
 CONFIG_RTE_LIBRTE_PMD_MVSAM_CRYPTO=n
 
 #
+# Compile PMD for NITROX crypto device
+#
+CONFIG_RTE_LIBRTE_PMD_NITROX=y
+
+#
 # Compile generic security library
 #
 CONFIG_RTE_LIBRTE_SECURITY=y
diff --git a/doc/guides/cryptodevs/index.rst b/doc/guides/cryptodevs/index.rst
index 83610e64f..d1e0d3203 100644
--- a/doc/guides/cryptodevs/index.rst
+++ b/doc/guides/cryptodevs/index.rst
@@ -21,6 +21,7 @@ Crypto Device Drivers
 octeontx
 openssl
 mvsam
+nitrox
 null
 scheduler
 snow3g
diff --git a/doc/guides/cryptodevs/nitrox.rst b/doc/guides/cryptodevs/nitrox.rst
new file mode 100644
index 0..b6b86dda5
--- /dev/null
+++ b/doc/guides/cryptodevs/nitrox.rst
@@ -0,0 +1,11 @@
+..  SPDX-License-Identifier: BSD-3-Clause
+Copyright(C) 2019 Marvell International Ltd.
+
+Nitrox Crypto Poll Mode Driver
+==
+
+The Nitrox crypto poll mode driver provides support for offloading
+cryptographic operations to the NITROX V security processor. Detailed
+information about the NITROX V security processor can be obtained here:
+
+* 
https://www.marvell.com/security-solutions/nitrox-security-processors/nitrox-v/
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index 009f8443d..7129bcfc9 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -25,5 +25,6 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_CAAM_JR) += caam_jr
 endif # CONFIG_RTE_LIBRTE_PMD_DPAA_SEC
 endif # CONFIG_RTE_LIBRTE_SECURITY
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_VIRTIO_CRYPTO) += virtio
+DIRS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox
 
 include $(RTE_SDK)/mk/rte.subdir.mk
diff --git a/drivers/crypto/meson.build b/drivers/crypto/meson.build
index 83e78860e..1a358ff8b 100644
--- a/drivers/crypto/meson.build
+++ b/drivers/crypto/meson.build
@@ -2,8 +2,8 @@
 # Copyright(c) 2017 Intel Corporation
 
 drivers = ['aesni_gcm', 'aesni_mb', 'caam_jr', 'ccp', 'dpaa_sec', 'dpaa2_sec',
-   'kasumi', 'mvsam', 'null', 'octeontx', 'openssl', 'qat', 'scheduler',
-   'snow3g', 'virtio', 'zuc']
+   'kasumi', 'mvsam', 'nitrox', 'null', 'octeontx', 'openssl', 'qat',
+   'scheduler', 'snow3g', 'virtio', 'zuc']
 
 std_deps = ['cryptodev'] # cryptodev pulls in all other needed deps
 config_flag_fmt = 'RTE_LIBRTE_@0@_PMD'
diff --git a/drivers/crypto/nitrox/Makefile b/drivers/crypto/nitrox/Makefile
new file mode 100644
index 0..da33a1d2a
--- /dev/null
+++ b/drivers/crypto/nitrox/Makefile
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(C) 2019 Marvell International Ltd.
+
+include $(RTE_SDK)/mk/rte.vars.mk
+
+# library name
+LIB = librte_pmd_nitrox.a
+
+# build flags
+CFLAGS += -O3
+CFLAGS += $(WERROR_FLAGS)
+CFLAGS += -DALLOW_EXPERIMENTAL_API
+
+# library version
+LIBABIVER := 1
+
+# versioning export map
+EXPORT_MAP := rte_pmd_nitrox_version.map
+
+# external library dependencies
+LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool
+LDLIBS += -lrte_pci -lrte_bus_pci
+LDLIBS += -lrte_cryptodev
+
+# library source files
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_device.c
+
+include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/crypto/nitrox/meson.build 
b/drivers/crypto/nitrox/me

[dpdk-dev] [PATCH v4 00/11] add Nitrox crypto device support

[Nagadheeraj Rottela]

Add the Nitrox PMD to support Nitrox crypto device.
---
v4:
* Added wmb between pending_count store and sr pointer store in enqueue
  operation. This is required to safely read sr in dequeue operation.

v3:
* Add SHA224 and SHA256 HMAC algorithms

v2:
* Fix compilation error on AARCH64.
* Fix checkpatch warning "UNNECESSARY_ELSE: else is not generally
  useful after a break or return".

Nagadheeraj Rottela (11):
  crypto/nitrox: add Nitrox build and doc skeleton
  crypto/nitrox: add PCI probe and remove routines
  crypto/nitrox: create Nitrox symmetric cryptodev
  crypto/nitrox: add basic symmetric cryptodev operations
  crypto/nitrox: add software queue management functionality
  crypto/nitrox: add hardware queue management functionality
  crypto/nitrox: add session management operations
  crypto/nitrox: add burst enqueue and dequeue operations
  crypto/nitrox: add cipher auth crypto chain processing
  test/crypto: add tests for Nitrox PMD
  crypto/nitrox: add SHA224 and SHA256 HMAC algorithms

 MAINTAINERS  |   7 +
 app/test/test_cryptodev.c|  52 ++
 app/test/test_cryptodev.h|   1 +
 app/test/test_cryptodev_aes_test_vectors.h   |  48 +-
 app/test/test_cryptodev_blockcipher.c|   9 +-
 app/test/test_cryptodev_blockcipher.h|   1 +
 config/common_base   |   5 +
 doc/guides/cryptodevs/features/nitrox.ini|  40 ++
 doc/guides/cryptodevs/index.rst  |   1 +
 doc/guides/cryptodevs/nitrox.rst |  48 ++
 drivers/crypto/Makefile  |   1 +
 drivers/crypto/meson.build   |   4 +-
 drivers/crypto/nitrox/Makefile   |  34 ++
 drivers/crypto/nitrox/meson.build|  19 +
 drivers/crypto/nitrox/nitrox_csr.h   |  41 ++
 drivers/crypto/nitrox/nitrox_device.c| 117 
 drivers/crypto/nitrox/nitrox_device.h|  24 +
 drivers/crypto/nitrox/nitrox_hal.c   | 237 
 drivers/crypto/nitrox/nitrox_hal.h   | 165 +
 drivers/crypto/nitrox/nitrox_logs.c  |  14 +
 drivers/crypto/nitrox/nitrox_logs.h  |  16 +
 drivers/crypto/nitrox/nitrox_qp.c| 117 
 drivers/crypto/nitrox/nitrox_qp.h| 108 
 drivers/crypto/nitrox/nitrox_sym.c   | 727 +++
 drivers/crypto/nitrox/nitrox_sym.h   |  13 +
 drivers/crypto/nitrox/nitrox_sym_capabilities.c  |  99 +++
 drivers/crypto/nitrox/nitrox_sym_capabilities.h  |  12 +
 drivers/crypto/nitrox/nitrox_sym_ctx.h   |  85 +++
 drivers/crypto/nitrox/nitrox_sym_reqmgr.c| 653 
 drivers/crypto/nitrox/nitrox_sym_reqmgr.h|  23 +
 drivers/crypto/nitrox/rte_pmd_nitrox_version.map |   3 +
 mk/rte.app.mk|   1 +
 32 files changed, 2706 insertions(+), 19 deletions(-)
 create mode 100644 doc/guides/cryptodevs/features/nitrox.ini
 create mode 100644 doc/guides/cryptodevs/nitrox.rst
 create mode 100644 drivers/crypto/nitrox/Makefile
 create mode 100644 drivers/crypto/nitrox/meson.build
 create mode 100644 drivers/crypto/nitrox/nitrox_csr.h
 create mode 100644 drivers/crypto/nitrox/nitrox_device.c
 create mode 100644 drivers/crypto/nitrox/nitrox_device.h
 create mode 100644 drivers/crypto/nitrox/nitrox_hal.c
 create mode 100644 drivers/crypto/nitrox/nitrox_hal.h
 create mode 100644 drivers/crypto/nitrox/nitrox_logs.c
 create mode 100644 drivers/crypto/nitrox/nitrox_logs.h
 create mode 100644 drivers/crypto/nitrox/nitrox_qp.c
 create mode 100644 drivers/crypto/nitrox/nitrox_qp.h
 create mode 100644 drivers/crypto/nitrox/nitrox_sym.c
 create mode 100644 drivers/crypto/nitrox/nitrox_sym.h
 create mode 100644 drivers/crypto/nitrox/nitrox_sym_capabilities.c
 create mode 100644 drivers/crypto/nitrox/nitrox_sym_capabilities.h
 create mode 100644 drivers/crypto/nitrox/nitrox_sym_ctx.h
 create mode 100644 drivers/crypto/nitrox/nitrox_sym_reqmgr.c
 create mode 100644 drivers/crypto/nitrox/nitrox_sym_reqmgr.h
 create mode 100644 drivers/crypto/nitrox/rte_pmd_nitrox_version.map

-- 
2.13.6

[dpdk-dev] [PATCH v4 02/11] crypto/nitrox: add PCI probe and remove routines

[Nagadheeraj Rottela]

Add pci probe, remove and hardware init routines.

Signed-off-by: Nagadheeraj Rottela 
---
 drivers/crypto/nitrox/Makefile|   1 +
 drivers/crypto/nitrox/meson.build |   1 +
 drivers/crypto/nitrox/nitrox_csr.h|  28 +
 drivers/crypto/nitrox/nitrox_device.c | 105 ++
 drivers/crypto/nitrox/nitrox_device.h |  18 ++
 drivers/crypto/nitrox/nitrox_hal.c|  86 
 drivers/crypto/nitrox/nitrox_hal.h|  37 
 7 files changed, 276 insertions(+)
 create mode 100644 drivers/crypto/nitrox/nitrox_csr.h
 create mode 100644 drivers/crypto/nitrox/nitrox_device.h
 create mode 100644 drivers/crypto/nitrox/nitrox_hal.c
 create mode 100644 drivers/crypto/nitrox/nitrox_hal.h

diff --git a/drivers/crypto/nitrox/Makefile b/drivers/crypto/nitrox/Makefile
index da33a1d2a..bc0220964 100644
--- a/drivers/crypto/nitrox/Makefile
+++ b/drivers/crypto/nitrox/Makefile
@@ -24,5 +24,6 @@ LDLIBS += -lrte_cryptodev
 
 # library source files
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_device.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_hal.c
 
 include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/crypto/nitrox/meson.build 
b/drivers/crypto/nitrox/meson.build
index 0afb14b00..f1c96b84d 100644
--- a/drivers/crypto/nitrox/meson.build
+++ b/drivers/crypto/nitrox/meson.build
@@ -10,4 +10,5 @@ deps += ['bus_pci']
 allow_experimental_apis = true
 sources = files(
'nitrox_device.c',
+   'nitrox_hal.c',
)
diff --git a/drivers/crypto/nitrox/nitrox_csr.h 
b/drivers/crypto/nitrox/nitrox_csr.h
new file mode 100644
index 0..879104515
--- /dev/null
+++ b/drivers/crypto/nitrox/nitrox_csr.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2019 Marvell International Ltd.
+ */
+
+#ifndef _NITROX_CSR_H_
+#define _NITROX_CSR_H_
+
+#include 
+#include 
+
+#define CSR_DELAY  30
+
+/* AQM Virtual Function Registers */
+#define AQMQ_QSZX(_i)  (0x20008 + ((_i)*0x4))
+
+static inline uint64_t
+nitrox_read_csr(uint8_t *bar_addr, uint64_t offset)
+{
+   return rte_read64(bar_addr + offset);
+}
+
+static inline void
+nitrox_write_csr(uint8_t *bar_addr, uint64_t offset, uint64_t value)
+{
+   rte_write64(value, (bar_addr + offset));
+}
+
+#endif /* _NITROX_CSR_H_ */
diff --git a/drivers/crypto/nitrox/nitrox_device.c 
b/drivers/crypto/nitrox/nitrox_device.c
index d26535dee..5628c6d8b 100644
--- a/drivers/crypto/nitrox/nitrox_device.c
+++ b/drivers/crypto/nitrox/nitrox_device.c
@@ -1,3 +1,108 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  * Copyright(C) 2019 Marvell International Ltd.
  */
+
+#include 
+
+#include "nitrox_device.h"
+#include "nitrox_hal.h"
+
+TAILQ_HEAD(ndev_list, nitrox_device);
+static struct ndev_list ndev_list = TAILQ_HEAD_INITIALIZER(ndev_list);
+
+static struct nitrox_device *
+ndev_allocate(struct rte_pci_device *pdev)
+{
+   struct nitrox_device *ndev;
+
+   ndev = rte_zmalloc_socket("nitrox device", sizeof(*ndev),
+  RTE_CACHE_LINE_SIZE,
+  pdev->device.numa_node);
+   if (!ndev)
+   return NULL;
+
+   TAILQ_INSERT_TAIL(&ndev_list, ndev, next);
+   return ndev;
+}
+
+static void
+ndev_init(struct nitrox_device *ndev, struct rte_pci_device *pdev)
+{
+   enum nitrox_vf_mode vf_mode;
+
+   ndev->pdev = pdev;
+   ndev->bar_addr = pdev->mem_resource[0].addr;
+   vf_mode = vf_get_vf_config_mode(ndev->bar_addr);
+   ndev->nr_queues = vf_config_mode_to_nr_queues(vf_mode);
+}
+
+static struct nitrox_device *
+find_ndev(struct rte_pci_device *pdev)
+{
+   struct nitrox_device *ndev;
+
+   TAILQ_FOREACH(ndev, &ndev_list, next)
+   if (ndev->pdev == pdev)
+   return ndev;
+
+   return NULL;
+}
+
+static void
+ndev_release(struct nitrox_device *ndev)
+{
+   if (!ndev)
+   return;
+
+   TAILQ_REMOVE(&ndev_list, ndev, next);
+   rte_free(ndev);
+}
+
+static int
+nitrox_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
+   struct rte_pci_device *pdev)
+{
+   struct nitrox_device *ndev;
+
+   /* Nitrox CSR space */
+   if (!pdev->mem_resource[0].addr)
+   return -EINVAL;
+
+   ndev = ndev_allocate(pdev);
+   if (!ndev)
+   return -ENOMEM;
+
+   ndev_init(ndev, pdev);
+   return 0;
+}
+
+static int
+nitrox_pci_remove(struct rte_pci_device *pdev)
+{
+   struct nitrox_device *ndev;
+
+   ndev = find_ndev(pdev);
+   if (!ndev)
+   return -ENODEV;
+
+   ndev_release(ndev);
+   return 0;
+}
+
+static struct rte_pci_id pci_id_nitrox_map[] = {
+   {
+   /* Nitrox 5 VF */
+   RTE_PCI_DEVICE(0x177d, 0x13)
+   },
+   {.device_id = 0},
+};
+
+static struct rte_pci_driver nitrox_pmd = {
+   .id_table   = pci_id_nitrox_map,
+   .drv_fla

[dpdk-dev] [PATCH v4 03/11] crypto/nitrox: create Nitrox symmetric cryptodev

[Nagadheeraj Rottela]

Add Nitrox symmetric cryptodev with no operations. Cryptodev
operations will be added in the next set of patches. Also, registered
nitrox log type.

Signed-off-by: Nagadheeraj Rottela 
---
 drivers/crypto/nitrox/Makefile|  2 +
 drivers/crypto/nitrox/meson.build |  2 +
 drivers/crypto/nitrox/nitrox_device.c |  9 
 drivers/crypto/nitrox/nitrox_device.h |  6 +++
 drivers/crypto/nitrox/nitrox_logs.c   | 14 ++
 drivers/crypto/nitrox/nitrox_logs.h   | 16 +++
 drivers/crypto/nitrox/nitrox_sym.c| 83 +++
 drivers/crypto/nitrox/nitrox_sym.h| 13 ++
 8 files changed, 145 insertions(+)
 create mode 100644 drivers/crypto/nitrox/nitrox_logs.c
 create mode 100644 drivers/crypto/nitrox/nitrox_logs.h
 create mode 100644 drivers/crypto/nitrox/nitrox_sym.c
 create mode 100644 drivers/crypto/nitrox/nitrox_sym.h

diff --git a/drivers/crypto/nitrox/Makefile b/drivers/crypto/nitrox/Makefile
index bc0220964..06c96ccd7 100644
--- a/drivers/crypto/nitrox/Makefile
+++ b/drivers/crypto/nitrox/Makefile
@@ -25,5 +25,7 @@ LDLIBS += -lrte_cryptodev
 # library source files
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_device.c
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_hal.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_logs.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_sym.c
 
 include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/crypto/nitrox/meson.build 
b/drivers/crypto/nitrox/meson.build
index f1c96b84d..1277cf58e 100644
--- a/drivers/crypto/nitrox/meson.build
+++ b/drivers/crypto/nitrox/meson.build
@@ -11,4 +11,6 @@ allow_experimental_apis = true
 sources = files(
'nitrox_device.c',
'nitrox_hal.c',
+   'nitrox_logs.c',
+   'nitrox_sym.c',
)
diff --git a/drivers/crypto/nitrox/nitrox_device.c 
b/drivers/crypto/nitrox/nitrox_device.c
index 5628c6d8b..ec2aae588 100644
--- a/drivers/crypto/nitrox/nitrox_device.c
+++ b/drivers/crypto/nitrox/nitrox_device.c
@@ -6,6 +6,7 @@
 
 #include "nitrox_device.h"
 #include "nitrox_hal.h"
+#include "nitrox_sym.h"
 
 TAILQ_HEAD(ndev_list, nitrox_device);
 static struct ndev_list ndev_list = TAILQ_HEAD_INITIALIZER(ndev_list);
@@ -63,6 +64,7 @@ nitrox_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
struct rte_pci_device *pdev)
 {
struct nitrox_device *ndev;
+   int err;
 
/* Nitrox CSR space */
if (!pdev->mem_resource[0].addr)
@@ -73,6 +75,12 @@ nitrox_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
return -ENOMEM;
 
ndev_init(ndev, pdev);
+   err = nitrox_sym_pmd_create(ndev);
+   if (err) {
+   ndev_release(ndev);
+   return err;
+   }
+
return 0;
 }
 
@@ -85,6 +93,7 @@ nitrox_pci_remove(struct rte_pci_device *pdev)
if (!ndev)
return -ENODEV;
 
+   nitrox_sym_pmd_destroy(ndev);
ndev_release(ndev);
return 0;
 }
diff --git a/drivers/crypto/nitrox/nitrox_device.h 
b/drivers/crypto/nitrox/nitrox_device.h
index 0d0167de2..82ba8b4e4 100644
--- a/drivers/crypto/nitrox/nitrox_device.h
+++ b/drivers/crypto/nitrox/nitrox_device.h
@@ -8,10 +8,16 @@
 #include 
 #include 
 
+#define NITROX_DEV_NAME_MAX_LEN RTE_CRYPTODEV_NAME_MAX_LEN
+
+struct nitrox_sym_device;
+
 struct nitrox_device {
TAILQ_ENTRY(nitrox_device) next;
struct rte_pci_device *pdev;
uint8_t *bar_addr;
+   struct nitrox_sym_device *sym_dev;
+   struct rte_device rte_sym_dev;
uint16_t nr_queues;
 };
 
diff --git a/drivers/crypto/nitrox/nitrox_logs.c 
b/drivers/crypto/nitrox/nitrox_logs.c
new file mode 100644
index 0..007056cb4
--- /dev/null
+++ b/drivers/crypto/nitrox/nitrox_logs.c
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2019 Marvell International Ltd.
+ */
+
+#include 
+
+int nitrox_logtype;
+
+RTE_INIT(nitrox_init_log)
+{
+   nitrox_logtype = rte_log_register("pmd.crypto.nitrox");
+   if (nitrox_logtype >= 0)
+   rte_log_set_level(nitrox_logtype, RTE_LOG_NOTICE);
+}
diff --git a/drivers/crypto/nitrox/nitrox_logs.h 
b/drivers/crypto/nitrox/nitrox_logs.h
new file mode 100644
index 0..06fd21a95
--- /dev/null
+++ b/drivers/crypto/nitrox/nitrox_logs.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2019 Marvell International Ltd.
+ */
+
+#ifndef _NITROX_LOGS_H_
+#define _NITROX_LOGS_H_
+
+#define LOG_PREFIX "NITROX: "
+
+extern int nitrox_logtype;
+
+#define NITROX_LOG(level, fmt, args...)
\
+   rte_log(RTE_LOG_ ## level, nitrox_logtype,  \
+   LOG_PREFIX "%s:%d " fmt, __func__, __LINE__, ## args)
+
+#endif /* _NITROX_LOGS_H_ */
diff --git a/drivers/crypto/nitrox/nitrox_sym.c 
b/drivers/crypto/nitrox/nitrox_sym.c
new file mode 100644
index 0..c72016dd0
--- /dev/null
+++ b/drivers/crypto/nitrox/nitrox_sym.c
@@ -0,0 +1,8

[dpdk-dev] [PATCH v4 05/11] crypto/nitrox: add software queue management functionality

[Nagadheeraj Rottela]

Add software queue management code corresponding to queue pair setup
and release functions.

Signed-off-by: Nagadheeraj Rottela 
---
 drivers/crypto/nitrox/Makefile|   2 +
 drivers/crypto/nitrox/meson.build |   2 +
 drivers/crypto/nitrox/nitrox_qp.c |  74 +
 drivers/crypto/nitrox/nitrox_qp.h |  40 +
 drivers/crypto/nitrox/nitrox_sym.c| 132 --
 drivers/crypto/nitrox/nitrox_sym_reqmgr.c |  56 +
 drivers/crypto/nitrox/nitrox_sym_reqmgr.h |  13 +++
 7 files changed, 312 insertions(+), 7 deletions(-)
 create mode 100644 drivers/crypto/nitrox/nitrox_qp.c
 create mode 100644 drivers/crypto/nitrox/nitrox_qp.h
 create mode 100644 drivers/crypto/nitrox/nitrox_sym_reqmgr.c
 create mode 100644 drivers/crypto/nitrox/nitrox_sym_reqmgr.h

diff --git a/drivers/crypto/nitrox/Makefile b/drivers/crypto/nitrox/Makefile
index dedb74a34..f56992770 100644
--- a/drivers/crypto/nitrox/Makefile
+++ b/drivers/crypto/nitrox/Makefile
@@ -28,5 +28,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_hal.c
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_logs.c
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_sym.c
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_sym_capabilities.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_sym_reqmgr.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_qp.c
 
 include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/crypto/nitrox/meson.build 
b/drivers/crypto/nitrox/meson.build
index 7c565c5a4..03788366b 100644
--- a/drivers/crypto/nitrox/meson.build
+++ b/drivers/crypto/nitrox/meson.build
@@ -14,4 +14,6 @@ sources = files(
'nitrox_logs.c',
'nitrox_sym.c',
'nitrox_sym_capabilities.c',
+   'nitrox_sym_reqmgr.c',
+   'nitrox_qp.c'
)
diff --git a/drivers/crypto/nitrox/nitrox_qp.c 
b/drivers/crypto/nitrox/nitrox_qp.c
new file mode 100644
index 0..9673bb4f3
--- /dev/null
+++ b/drivers/crypto/nitrox/nitrox_qp.c
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2019 Marvell International Ltd.
+ */
+
+#include 
+#include 
+
+#include "nitrox_qp.h"
+#include "nitrox_hal.h"
+#include "nitrox_logs.h"
+
+#define MAX_CMD_QLEN 16384
+
+static int
+nitrox_setup_ridq(struct nitrox_qp *qp, int socket_id)
+{
+   size_t ridq_size = qp->count * sizeof(*qp->ridq);
+
+   qp->ridq = rte_zmalloc_socket("nitrox ridq", ridq_size,
+  RTE_CACHE_LINE_SIZE,
+  socket_id);
+   if (!qp->ridq) {
+   NITROX_LOG(ERR, "Failed to create rid queue\n");
+   return -ENOMEM;
+   }
+
+   return 0;
+}
+
+int
+nitrox_qp_setup(struct nitrox_qp *qp, uint8_t *bar_addr, const char *dev_name,
+   uint32_t nb_descriptors, uint8_t instr_size, int socket_id)
+{
+   int err;
+   uint32_t count;
+
+   RTE_SET_USED(bar_addr);
+   RTE_SET_USED(instr_size);
+   count = rte_align32pow2(nb_descriptors);
+   if (count > MAX_CMD_QLEN) {
+   NITROX_LOG(ERR, "%s: Number of descriptors too big %d,"
+  " greater than max queue length %d\n",
+  dev_name, count,
+  MAX_CMD_QLEN);
+   return -EINVAL;
+   }
+
+   qp->count = count;
+   qp->head = qp->tail = 0;
+   rte_atomic16_init(&qp->pending_count);
+   err = nitrox_setup_ridq(qp, socket_id);
+   if (err)
+   goto ridq_err;
+
+   return 0;
+
+ridq_err:
+   return err;
+
+}
+
+static void
+nitrox_release_ridq(struct nitrox_qp *qp)
+{
+   rte_free(qp->ridq);
+}
+
+int
+nitrox_qp_release(struct nitrox_qp *qp, uint8_t *bar_addr)
+{
+   RTE_SET_USED(bar_addr);
+   nitrox_release_ridq(qp);
+   return 0;
+}
diff --git a/drivers/crypto/nitrox/nitrox_qp.h 
b/drivers/crypto/nitrox/nitrox_qp.h
new file mode 100644
index 0..cf0102ff9
--- /dev/null
+++ b/drivers/crypto/nitrox/nitrox_qp.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2019 Marvell International Ltd.
+ */
+
+#ifndef _NITROX_QP_H_
+#define _NITROX_QP_H_
+
+#include 
+
+#include 
+
+struct nitrox_softreq;
+
+struct rid {
+   struct nitrox_softreq *sr;
+};
+
+struct nitrox_qp {
+   struct rid *ridq;
+   uint32_t count;
+   uint32_t head;
+   uint32_t tail;
+   struct rte_mempool *sr_mp;
+   struct rte_cryptodev_stats stats;
+   uint16_t qno;
+   rte_atomic16_t pending_count;
+};
+
+static inline bool
+nitrox_qp_is_empty(struct nitrox_qp *qp)
+{
+   return (rte_atomic16_read(&qp->pending_count) == 0);
+}
+
+int nitrox_qp_setup(struct nitrox_qp *qp, uint8_t *bar_addr,
+   const char *dev_name, uint32_t nb_descriptors,
+   uint8_t inst_size, int socket_id);
+int nitrox_qp_release(struct nitrox_qp *qp, uint8_t *bar_addr);
+
+#endif /* _NITROX_QP_H_ *

[dpdk-dev] [PATCH v4 04/11] crypto/nitrox: add basic symmetric cryptodev operations

[Nagadheeraj Rottela]

Add the following cryptodev operations,
- dev_configure
- dev_start
- dev_stop
- dev_close
- dev_infos_get

Signed-off-by: Nagadheeraj Rottela 
---
 doc/guides/cryptodevs/features/nitrox.ini   | 38 
 doc/guides/cryptodevs/nitrox.rst| 37 +++
 drivers/crypto/nitrox/Makefile  |  1 +
 drivers/crypto/nitrox/meson.build   |  1 +
 drivers/crypto/nitrox/nitrox_sym.c  | 81 -
 drivers/crypto/nitrox/nitrox_sym_capabilities.c | 57 +
 drivers/crypto/nitrox/nitrox_sym_capabilities.h | 12 
 7 files changed, 226 insertions(+), 1 deletion(-)
 create mode 100644 doc/guides/cryptodevs/features/nitrox.ini
 create mode 100644 drivers/crypto/nitrox/nitrox_sym_capabilities.c
 create mode 100644 drivers/crypto/nitrox/nitrox_sym_capabilities.h

diff --git a/doc/guides/cryptodevs/features/nitrox.ini 
b/doc/guides/cryptodevs/features/nitrox.ini
new file mode 100644
index 0..9f9e2619c
--- /dev/null
+++ b/doc/guides/cryptodevs/features/nitrox.ini
@@ -0,0 +1,38 @@
+;
+; Supported features of the 'nitrox' crypto driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Symmetric crypto   = Y
+Sym operation chaining = Y
+HW Accelerated = Y
+In Place SGL   = Y
+OOP SGL In SGL Out = Y
+OOP SGL In LB  Out = Y
+OOP LB  In SGL Out = Y
+OOP LB  In LB  Out = Y
+
+;
+; Supported crypto algorithms of the 'nitrox' crypto driver.
+;
+[Cipher]
+AES CBC (128)  = Y
+AES CBC (192)  = Y
+AES CBC (256)  = Y
+
+;
+; Supported authentication algorithms of the 'nitrox' crypto driver.
+;
+[Auth]
+SHA1 HMAC= Y
+
+;
+; Supported AEAD algorithms of the 'nitrox' crypto driver.
+;
+[AEAD]
+
+;
+; Supported Asymmetric algorithms of the 'nitrox' crypto driver.
+;
+[Asymmetric]
diff --git a/doc/guides/cryptodevs/nitrox.rst b/doc/guides/cryptodevs/nitrox.rst
index b6b86dda5..c16a5e393 100644
--- a/doc/guides/cryptodevs/nitrox.rst
+++ b/doc/guides/cryptodevs/nitrox.rst
@@ -9,3 +9,40 @@ cryptographic operations to the NITROX V security processor. 
Detailed
 information about the NITROX V security processor can be obtained here:
 
 * 
https://www.marvell.com/security-solutions/nitrox-security-processors/nitrox-v/
+
+Features
+
+
+Nitrox crypto PMD has support for:
+
+Cipher algorithms:
+
+* ``RTE_CRYPTO_CIPHER_AES_CBC``
+
+Hash algorithms:
+
+* ``RTE_CRYPTO_AUTH_SHA1_HMAC``
+
+Limitations
+---
+
+* AES_CBC Cipher Only combination is not supported.
+
+Installation
+
+
+For compiling the Nitrox crypto PMD, please check if the
+CONFIG_RTE_LIBRTE_PMD_NITROX setting is set to `y` in config/common_base file.
+
+* ``CONFIG_RTE_LIBRTE_PMD_NITROX=y``
+
+Initialization
+--
+
+Nitrox crypto PMD depend on Nitrox kernel PF driver being installed on the
+platform. Nitrox PF driver is required to create VF devices which will
+be used by the PMD. Each VF device can enable one cryptodev PMD.
+
+Nitrox kernel PF driver is available as part of CNN55XX-Driver SDK. The SDK
+and it's installation instructions can be obtained from:
+`Marvell Technical Documentation Portal `_.
diff --git a/drivers/crypto/nitrox/Makefile b/drivers/crypto/nitrox/Makefile
index 06c96ccd7..dedb74a34 100644
--- a/drivers/crypto/nitrox/Makefile
+++ b/drivers/crypto/nitrox/Makefile
@@ -27,5 +27,6 @@ SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_device.c
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_hal.c
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_logs.c
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_sym.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_sym_capabilities.c
 
 include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/crypto/nitrox/meson.build 
b/drivers/crypto/nitrox/meson.build
index 1277cf58e..7c565c5a4 100644
--- a/drivers/crypto/nitrox/meson.build
+++ b/drivers/crypto/nitrox/meson.build
@@ -13,4 +13,5 @@ sources = files(
'nitrox_hal.c',
'nitrox_logs.c',
'nitrox_sym.c',
+   'nitrox_sym_capabilities.c',
)
diff --git a/drivers/crypto/nitrox/nitrox_sym.c 
b/drivers/crypto/nitrox/nitrox_sym.c
index c72016dd0..c05042e54 100644
--- a/drivers/crypto/nitrox/nitrox_sym.c
+++ b/drivers/crypto/nitrox/nitrox_sym.c
@@ -9,6 +9,7 @@
 
 #include "nitrox_sym.h"
 #include "nitrox_device.h"
+#include "nitrox_sym_capabilities.h"
 #include "nitrox_logs.h"
 
 #define CRYPTODEV_NAME_NITROX_PMD crypto_nitrox
@@ -25,6 +26,84 @@ static const struct rte_driver nitrox_rte_sym_drv = {
.alias = nitrox_sym_drv_name
 };
 
+static int nitrox_sym_dev_qp_release(struct rte_cryptodev *cdev,
+uint16_t qp_id);
+
+static int
+nitrox_sym_dev_config(__rte_unused struct rte_cryptodev *cdev,
+ __rte_unused struct rte_cryptodev_config *config)
+{
+   return 0;
+}
+
+static int
+nitrox_sym_dev_start(__rte_unused struct rte_c

[dpdk-dev] [PATCH v4 06/11] crypto/nitrox: add hardware queue management functionality

[Nagadheeraj Rottela]

Add hardware queue management code corresponding to queue pair setup
and release functions.

Signed-off-by: Nagadheeraj Rottela 
---
 drivers/crypto/nitrox/nitrox_csr.h |  13 
 drivers/crypto/nitrox/nitrox_hal.c | 151 +
 drivers/crypto/nitrox/nitrox_hal.h | 128 +++
 drivers/crypto/nitrox/nitrox_qp.c  |  51 -
 drivers/crypto/nitrox/nitrox_qp.h  |   8 ++
 5 files changed, 347 insertions(+), 4 deletions(-)

diff --git a/drivers/crypto/nitrox/nitrox_csr.h 
b/drivers/crypto/nitrox/nitrox_csr.h
index 879104515..fb9a34817 100644
--- a/drivers/crypto/nitrox/nitrox_csr.h
+++ b/drivers/crypto/nitrox/nitrox_csr.h
@@ -9,6 +9,19 @@
 #include 
 
 #define CSR_DELAY  30
+#define NITROX_CSR_ADDR(bar_addr, offset) (bar_addr + (offset))
+
+/* NPS packet registers */
+#define NPS_PKT_IN_INSTR_CTLX(_i)  (0x10060 + ((_i) * 0x4))
+#define NPS_PKT_IN_INSTR_BADDRX(_i)(0x10068 + ((_i) * 0x4))
+#define NPS_PKT_IN_INSTR_RSIZEX(_i)(0x10070 + ((_i) * 0x4))
+#define NPS_PKT_IN_DONE_CNTSX(_i)  (0x10080 + ((_i) * 0x4))
+#define NPS_PKT_IN_INSTR_BAOFF_DBELLX(_i)  (0x10078 + ((_i) * 0x4))
+#define NPS_PKT_IN_INT_LEVELSX(_i) (0x10088 + ((_i) * 0x4))
+
+#define NPS_PKT_SLC_CTLX(_i)   (0x1 + ((_i) * 0x4))
+#define NPS_PKT_SLC_CNTSX(_i)  (0x10008 + ((_i) * 0x4))
+#define NPS_PKT_SLC_INT_LEVELSX(_i)(0x10010 + ((_i) * 0x4))
 
 /* AQM Virtual Function Registers */
 #define AQMQ_QSZX(_i)  (0x20008 + ((_i)*0x4))
diff --git a/drivers/crypto/nitrox/nitrox_hal.c 
b/drivers/crypto/nitrox/nitrox_hal.c
index 3dee59215..3c2c24c23 100644
--- a/drivers/crypto/nitrox/nitrox_hal.c
+++ b/drivers/crypto/nitrox/nitrox_hal.c
@@ -12,6 +12,157 @@
 
 #define MAX_VF_QUEUES  8
 #define MAX_PF_QUEUES  64
+#define NITROX_TIMER_THOLD 0x3F
+#define NITROX_COUNT_THOLD  0x
+
+void
+nps_pkt_input_ring_disable(uint8_t *bar_addr, uint16_t ring)
+{
+   union nps_pkt_in_instr_ctl pkt_in_instr_ctl;
+   uint64_t reg_addr;
+   int max_retries = 5;
+
+   reg_addr = NPS_PKT_IN_INSTR_CTLX(ring);
+   pkt_in_instr_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr);
+   pkt_in_instr_ctl.s.enb = 0;
+   nitrox_write_csr(bar_addr, reg_addr, pkt_in_instr_ctl.u64);
+   rte_delay_us_block(100);
+
+   /* wait for enable bit to be cleared */
+   pkt_in_instr_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr);
+   while (pkt_in_instr_ctl.s.enb && max_retries--) {
+   rte_delay_ms(10);
+   pkt_in_instr_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr);
+   }
+}
+
+void
+nps_pkt_solicited_port_disable(uint8_t *bar_addr, uint16_t port)
+{
+   union nps_pkt_slc_ctl pkt_slc_ctl;
+   uint64_t reg_addr;
+   int max_retries = 5;
+
+   /* clear enable bit */
+   reg_addr = NPS_PKT_SLC_CTLX(port);
+   pkt_slc_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr);
+   pkt_slc_ctl.s.enb = 0;
+   nitrox_write_csr(bar_addr, reg_addr, pkt_slc_ctl.u64);
+   rte_delay_us_block(100);
+
+   pkt_slc_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr);
+   while (pkt_slc_ctl.s.enb && max_retries--) {
+   rte_delay_ms(10);
+   pkt_slc_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr);
+   }
+}
+
+void
+setup_nps_pkt_input_ring(uint8_t *bar_addr, uint16_t ring, uint32_t rsize,
+phys_addr_t raddr)
+{
+   union nps_pkt_in_instr_ctl pkt_in_instr_ctl;
+   union nps_pkt_in_instr_rsize pkt_in_instr_rsize;
+   union nps_pkt_in_instr_baoff_dbell pkt_in_instr_baoff_dbell;
+   union nps_pkt_in_done_cnts pkt_in_done_cnts;
+   uint64_t base_addr, reg_addr;
+   int max_retries = 5;
+
+   nps_pkt_input_ring_disable(bar_addr, ring);
+
+   /* write base address */
+   reg_addr = NPS_PKT_IN_INSTR_BADDRX(ring);
+   base_addr = raddr;
+   nitrox_write_csr(bar_addr, reg_addr, base_addr);
+   rte_delay_us_block(CSR_DELAY);
+
+   /* write ring size */
+   reg_addr = NPS_PKT_IN_INSTR_RSIZEX(ring);
+   pkt_in_instr_rsize.u64 = 0;
+   pkt_in_instr_rsize.s.rsize = rsize;
+   nitrox_write_csr(bar_addr, reg_addr, pkt_in_instr_rsize.u64);
+   rte_delay_us_block(CSR_DELAY);
+
+   /* clear door bell */
+   reg_addr = NPS_PKT_IN_INSTR_BAOFF_DBELLX(ring);
+   pkt_in_instr_baoff_dbell.u64 = 0;
+   pkt_in_instr_baoff_dbell.s.dbell = 0x;
+   nitrox_write_csr(bar_addr, reg_addr, pkt_in_instr_baoff_dbell.u64);
+   rte_delay_us_block(CSR_DELAY);
+
+   /* clear done count */
+   reg_addr = NPS_PKT_IN_DONE_CNTSX(ring);
+   pkt_in_done_cnts.u64 = nitrox_read_csr(bar_addr, reg_addr);
+   nitrox_write_csr(bar_addr, reg_addr, pkt_in_done_cnts.u64);
+   rte_delay_us_block(CSR_DELAY);
+
+   /* Setup PKT IN RING Interrupt Threshold */
+   reg_addr = NPS_PKT_IN_INT_LEVELSX(ring);
+   nitro

[dpdk-dev] [PATCH v4 07/11] crypto/nitrox: add session management operations

[Nagadheeraj Rottela]

Add all the session management operations.

Signed-off-by: Nagadheeraj Rottela 
---
 drivers/crypto/nitrox/nitrox_sym.c | 323 -
 drivers/crypto/nitrox/nitrox_sym_ctx.h |  85 +
 2 files changed, 405 insertions(+), 3 deletions(-)
 create mode 100644 drivers/crypto/nitrox/nitrox_sym_ctx.h

diff --git a/drivers/crypto/nitrox/nitrox_sym.c 
b/drivers/crypto/nitrox/nitrox_sym.c
index 05f089cae..34c62b02e 100644
--- a/drivers/crypto/nitrox/nitrox_sym.c
+++ b/drivers/crypto/nitrox/nitrox_sym.c
@@ -12,16 +12,54 @@
 #include "nitrox_sym_capabilities.h"
 #include "nitrox_qp.h"
 #include "nitrox_sym_reqmgr.h"
+#include "nitrox_sym_ctx.h"
 #include "nitrox_logs.h"
 
 #define CRYPTODEV_NAME_NITROX_PMD crypto_nitrox
+#define MC_MAC_MISMATCH_ERR_CODE 0x4c
 #define NPS_PKT_IN_INSTR_SIZE 64
+#define IV_FROM_DPTR 1
+#define FLEXI_CRYPTO_ENCRYPT_HMAC 0x33
+#define AES_KEYSIZE_128 16
+#define AES_KEYSIZE_192 24
+#define AES_KEYSIZE_256 32
+#define MAX_IV_LEN 16
 
 struct nitrox_sym_device {
struct rte_cryptodev *cdev;
struct nitrox_device *ndev;
 };
 
+/* Cipher opcodes */
+enum flexi_cipher {
+   CIPHER_NULL = 0,
+   CIPHER_3DES_CBC,
+   CIPHER_3DES_ECB,
+   CIPHER_AES_CBC,
+   CIPHER_AES_ECB,
+   CIPHER_AES_CFB,
+   CIPHER_AES_CTR,
+   CIPHER_AES_GCM,
+   CIPHER_AES_XTS,
+   CIPHER_AES_CCM,
+   CIPHER_AES_CBC_CTS,
+   CIPHER_AES_ECB_CTS,
+   CIPHER_INVALID
+};
+
+/* Auth opcodes */
+enum flexi_auth {
+   AUTH_NULL = 0,
+   AUTH_MD5,
+   AUTH_SHA1,
+   AUTH_SHA2_SHA224,
+   AUTH_SHA2_SHA256,
+   AUTH_SHA2_SHA384,
+   AUTH_SHA2_SHA512,
+   AUTH_GMAC,
+   AUTH_INVALID
+};
+
 uint8_t nitrox_sym_drv_id;
 static const char nitrox_sym_drv_name[] = RTE_STR(CRYPTODEV_NAME_NITROX_PMD);
 static const struct rte_driver nitrox_rte_sym_drv = {
@@ -204,6 +242,285 @@ nitrox_sym_dev_qp_release(struct rte_cryptodev *cdev, 
uint16_t qp_id)
return err;
 }
 
+static unsigned int
+nitrox_sym_dev_sess_get_size(__rte_unused struct rte_cryptodev *cdev)
+{
+   return sizeof(struct nitrox_crypto_ctx);
+}
+
+static enum nitrox_chain
+get_crypto_chain_order(const struct rte_crypto_sym_xform *xform)
+{
+   enum nitrox_chain res = NITROX_CHAIN_NOT_SUPPORTED;
+
+   if (unlikely(xform == NULL))
+   return res;
+
+   switch (xform->type) {
+   case RTE_CRYPTO_SYM_XFORM_AUTH:
+   if (xform->next == NULL) {
+   res = NITROX_CHAIN_NOT_SUPPORTED;
+   } else if (xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER) {
+   if (xform->auth.op == RTE_CRYPTO_AUTH_OP_VERIFY &&
+   xform->next->cipher.op ==
+   RTE_CRYPTO_CIPHER_OP_DECRYPT) {
+   res = NITROX_CHAIN_AUTH_CIPHER;
+   } else {
+   NITROX_LOG(ERR, "auth op %d, cipher op %d\n",
+   xform->auth.op, xform->next->cipher.op);
+   }
+   }
+   break;
+   case RTE_CRYPTO_SYM_XFORM_CIPHER:
+   if (xform->next == NULL) {
+   res = NITROX_CHAIN_CIPHER_ONLY;
+   } else if (xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH) {
+   if (xform->cipher.op == RTE_CRYPTO_CIPHER_OP_ENCRYPT &&
+   xform->next->auth.op ==
+   RTE_CRYPTO_AUTH_OP_GENERATE) {
+   res = NITROX_CHAIN_CIPHER_AUTH;
+   } else {
+   NITROX_LOG(ERR, "cipher op %d, auth op %d\n",
+   xform->cipher.op, xform->next->auth.op);
+   }
+   }
+   break;
+   default:
+   break;
+   }
+
+   return res;
+}
+
+static enum flexi_cipher
+get_flexi_cipher_type(enum rte_crypto_cipher_algorithm algo, bool *is_aes)
+{
+   enum flexi_cipher type;
+
+   switch (algo) {
+   case RTE_CRYPTO_CIPHER_AES_CBC:
+   type = CIPHER_AES_CBC;
+   *is_aes = true;
+   break;
+   default:
+   type = CIPHER_INVALID;
+   NITROX_LOG(ERR, "Algorithm not supported %d\n", algo);
+   break;
+   }
+
+   return type;
+}
+
+static int
+flexi_aes_keylen(size_t keylen, bool is_aes)
+{
+   int aes_keylen;
+
+   if (!is_aes)
+   return 0;
+
+   switch (keylen) {
+   case AES_KEYSIZE_128:
+   aes_keylen = 1;
+   break;
+   case AES_KEYSIZE_192:
+   aes_keylen = 2;
+   break;
+   case AES_KEYSIZE_256:
+   aes_keylen = 3;
+   break;
+   default:
+   NITROX_LOG(ERR, "Invalid keylen %zu\n", keylen);
+   aes_keylen = -EINVAL;
+   break;
+   }
+

[dpdk-dev] [PATCH v4 08/11] crypto/nitrox: add burst enqueue and dequeue operations

[Nagadheeraj Rottela]

Add burst enqueue and dequeue operations along with interface for
symmetric request manager.

Signed-off-by: Nagadheeraj Rottela 
---
 drivers/crypto/nitrox/nitrox_qp.h |  60 +++
 drivers/crypto/nitrox/nitrox_sym.c| 128 +-
 drivers/crypto/nitrox/nitrox_sym_reqmgr.c | 174 ++
 drivers/crypto/nitrox/nitrox_sym_reqmgr.h |  10 ++
 4 files changed, 370 insertions(+), 2 deletions(-)

diff --git a/drivers/crypto/nitrox/nitrox_qp.h 
b/drivers/crypto/nitrox/nitrox_qp.h
index 0244c4dbf..e8c564cb1 100644
--- a/drivers/crypto/nitrox/nitrox_qp.h
+++ b/drivers/crypto/nitrox/nitrox_qp.h
@@ -34,12 +34,72 @@ struct nitrox_qp {
rte_atomic16_t pending_count;
 };
 
+static inline uint16_t
+nitrox_qp_free_count(struct nitrox_qp *qp)
+{
+   uint16_t pending_count = rte_atomic16_read(&qp->pending_count);
+
+   RTE_ASSERT(qp->count >= pending_count);
+   return (qp->count - pending_count);
+}
+
 static inline bool
 nitrox_qp_is_empty(struct nitrox_qp *qp)
 {
return (rte_atomic16_read(&qp->pending_count) == 0);
 }
 
+static inline uint16_t
+nitrox_qp_used_count(struct nitrox_qp *qp)
+{
+   return rte_atomic16_read(&qp->pending_count);
+}
+
+static inline struct nitrox_softreq *
+nitrox_qp_get_softreq(struct nitrox_qp *qp)
+{
+   uint32_t tail = qp->tail % qp->count;
+
+   return qp->ridq[tail].sr;
+}
+
+static inline void
+nitrox_ring_dbell(struct nitrox_qp *qp, uint16_t cnt)
+{
+   struct command_queue *cmdq = &qp->cmdq;
+
+   if (!cnt)
+   return;
+
+   rte_write64(cnt, cmdq->dbell_csr_addr);
+}
+
+static inline void
+nitrox_qp_enqueue(struct nitrox_qp *qp, void *instr, struct nitrox_softreq *sr)
+{
+   uint32_t head = qp->head % qp->count;
+
+   qp->head++;
+   memcpy(&qp->cmdq.ring[head * qp->cmdq.instr_size],
+  instr, qp->cmdq.instr_size);
+   qp->ridq[head].sr = sr;
+   rte_wmb();
+   rte_atomic16_inc(&qp->pending_count);
+   rte_wmb();
+}
+
+static inline void
+nitrox_qp_dequeue(struct nitrox_qp *qp)
+{
+   uint32_t tail = qp->tail % qp->count;
+
+   qp->tail++;
+   qp->ridq[tail].sr = NULL;
+   rte_wmb();
+   rte_atomic16_dec(&qp->pending_count);
+   rte_wmb();
+}
+
 int nitrox_qp_setup(struct nitrox_qp *qp, uint8_t *bar_addr,
const char *dev_name, uint32_t nb_descriptors,
uint8_t inst_size, int socket_id);
diff --git a/drivers/crypto/nitrox/nitrox_sym.c 
b/drivers/crypto/nitrox/nitrox_sym.c
index 34c62b02e..2056e1aae 100644
--- a/drivers/crypto/nitrox/nitrox_sym.c
+++ b/drivers/crypto/nitrox/nitrox_sym.c
@@ -521,6 +521,130 @@ nitrox_sym_dev_sess_clear(struct rte_cryptodev *cdev,
rte_mempool_put(sess_mp, ctx);
 }
 
+static struct nitrox_crypto_ctx *
+get_crypto_ctx(struct rte_crypto_op *op)
+{
+   if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) {
+   if (likely(op->sym->session))
+   return get_sym_session_private_data(op->sym->session,
+  nitrox_sym_drv_id);
+
+   }
+
+   return NULL;
+}
+
+static int
+nitrox_enq_single_op(struct nitrox_qp *qp, struct rte_crypto_op *op)
+{
+   struct nitrox_crypto_ctx *ctx;
+   struct nitrox_softreq *sr;
+   int err;
+
+   op->status = RTE_CRYPTO_OP_STATUS_NOT_PROCESSED;
+
+   ctx = get_crypto_ctx(op);
+   if (unlikely(!ctx)) {
+   op->status = RTE_CRYPTO_OP_STATUS_INVALID_SESSION;
+   return -EINVAL;
+   }
+
+   if (unlikely(rte_mempool_get(qp->sr_mp, (void **)&sr)))
+   return -ENOMEM;
+
+   err = nitrox_process_se_req(qp->qno, op, ctx, sr);
+   if (unlikely(err)) {
+   rte_mempool_put(qp->sr_mp, sr);
+   op->status = RTE_CRYPTO_OP_STATUS_ERROR;
+   return err;
+   }
+
+   nitrox_qp_enqueue(qp, nitrox_sym_instr_addr(sr), sr);
+   return 0;
+}
+
+static uint16_t
+nitrox_sym_dev_enq_burst(void *queue_pair, struct rte_crypto_op **ops,
+uint16_t nb_ops)
+{
+   struct nitrox_qp *qp = queue_pair;
+   uint16_t free_slots = 0;
+   uint16_t cnt = 0;
+   bool err = false;
+
+   free_slots = nitrox_qp_free_count(qp);
+   if (nb_ops > free_slots)
+   nb_ops = free_slots;
+
+   for (cnt = 0; cnt < nb_ops; cnt++) {
+   if (unlikely(nitrox_enq_single_op(qp, ops[cnt]))) {
+   err = true;
+   break;
+   }
+   }
+
+   nitrox_ring_dbell(qp, cnt);
+   qp->stats.enqueued_count += cnt;
+   if (unlikely(err))
+   qp->stats.enqueue_err_count++;
+
+   return cnt;
+}
+
+static int
+nitrox_deq_single_op(struct nitrox_qp *qp, struct rte_crypto_op **op_ptr)
+{
+   struct nitrox_softreq *sr;
+   int ret;
+   struct rte_crypto_op *op;
+
+   sr = nitrox_qp_get_softreq(qp);
+   

[dpdk-dev] [PATCH v4 09/11] crypto/nitrox: add cipher auth crypto chain processing

[Nagadheeraj Rottela]

Add cipher auth crypto chain processing functionality in symmetric
request manager.

Signed-off-by: Nagadheeraj Rottela 
---
 drivers/crypto/nitrox/nitrox_sym_reqmgr.c | 427 +-
 1 file changed, 425 insertions(+), 2 deletions(-)

diff --git a/drivers/crypto/nitrox/nitrox_sym_reqmgr.c 
b/drivers/crypto/nitrox/nitrox_sym_reqmgr.c
index a37b754f2..968e74fbe 100644
--- a/drivers/crypto/nitrox/nitrox_sym_reqmgr.c
+++ b/drivers/crypto/nitrox/nitrox_sym_reqmgr.c
@@ -10,9 +10,24 @@
 #include "nitrox_sym_reqmgr.h"
 #include "nitrox_logs.h"
 
+#define MAX_SGBUF_CNT 16
+#define MAX_SGCOMP_CNT 5
+/* SLC_STORE_INFO */
+#define MIN_UDD_LEN 16
+/* PKT_IN_HDR + SLC_STORE_INFO */
+#define FDATA_SIZE 32
+/* Base destination port for the solicited requests */
+#define SOLICIT_BASE_DPORT 256
 #define PENDING_SIG 0xUL
 #define CMD_TIMEOUT 2
 
+struct gphdr {
+   uint16_t param0;
+   uint16_t param1;
+   uint16_t param2;
+   uint16_t param3;
+};
+
 union pkt_instr_hdr {
uint64_t value;
struct {
@@ -105,12 +120,46 @@ struct resp_hdr {
uint64_t completion;
 };
 
+struct nitrox_sglist {
+   uint16_t len;
+   uint16_t raz0;
+   uint32_t raz1;
+   rte_iova_t iova;
+   void *virt;
+};
+
+struct nitrox_sgcomp {
+   uint16_t len[4];
+   uint64_t iova[4];
+};
+
+struct nitrox_sgtable {
+   uint8_t map_bufs_cnt;
+   uint8_t nr_sgcomp;
+   uint16_t total_bytes;
+
+   struct nitrox_sglist sglist[MAX_SGBUF_CNT];
+   struct nitrox_sgcomp sgcomp[MAX_SGCOMP_CNT];
+};
+
+struct iv {
+   uint8_t *virt;
+   rte_iova_t iova;
+   uint16_t len;
+};
+
 struct nitrox_softreq {
struct nitrox_crypto_ctx *ctx;
struct rte_crypto_op *op;
+   struct gphdr gph;
struct nps_pkt_instr instr;
struct resp_hdr resp;
+   struct nitrox_sgtable in;
+   struct nitrox_sgtable out;
+   struct iv iv;
uint64_t timeout;
+   rte_iova_t dptr;
+   rte_iova_t rptr;
rte_iova_t iova;
 };
 
@@ -121,10 +170,383 @@ softreq_init(struct nitrox_softreq *sr, rte_iova_t iova)
sr->iova = iova;
 }
 
+/*
+ * 64-Byte Instruction Format
+ *
+ *  --
+ *  |  DPTR0 | 8 bytes
+ *  --
+ *  |  PKT_IN_INSTR_HDR  | 8 bytes
+ *  --
+ *  |PKT_IN_HDR  | 16 bytes
+ *  --
+ *  |SLC_INFO| 16 bytes
+ *  --
+ *  |   Front data   | 16 bytes
+ *  --
+ */
+static void
+create_se_instr(struct nitrox_softreq *sr, uint8_t qno)
+{
+   struct nitrox_crypto_ctx *ctx = sr->ctx;
+   rte_iova_t ctx_handle;
+
+   /* fill the packet instruction */
+   /* word 0 */
+   sr->instr.dptr0 = rte_cpu_to_be_64(sr->dptr);
+
+   /* word 1 */
+   sr->instr.ih.value = 0;
+   sr->instr.ih.s.g = 1;
+   sr->instr.ih.s.gsz = sr->in.map_bufs_cnt;
+   sr->instr.ih.s.ssz = sr->out.map_bufs_cnt;
+   sr->instr.ih.s.fsz = FDATA_SIZE + sizeof(struct gphdr);
+   sr->instr.ih.s.tlen = sr->instr.ih.s.fsz + sr->in.total_bytes;
+   sr->instr.ih.value = rte_cpu_to_be_64(sr->instr.ih.value);
+
+   /* word 2 */
+   sr->instr.irh.value[0] = 0;
+   sr->instr.irh.s.uddl = MIN_UDD_LEN;
+   /* context length in 64-bit words */
+   sr->instr.irh.s.ctxl = RTE_ALIGN_MUL_CEIL(sizeof(ctx->fctx), 8) / 8;
+   /* offset from solicit base port 256 */
+   sr->instr.irh.s.destport = SOLICIT_BASE_DPORT + qno;
+   /* Invalid context cache */
+   sr->instr.irh.s.ctxc = 0x3;
+   sr->instr.irh.s.arg = ctx->req_op;
+   sr->instr.irh.s.opcode = ctx->opcode;
+   sr->instr.irh.value[0] = rte_cpu_to_be_64(sr->instr.irh.value[0]);
+
+   /* word 3 */
+   ctx_handle = ctx->iova + offsetof(struct nitrox_crypto_ctx, fctx);
+   sr->instr.irh.s.ctxp = rte_cpu_to_be_64(ctx_handle);
+
+   /* word 4 */
+   sr->instr.slc.value[0] = 0;
+   sr->instr.slc.s.ssz = sr->out.map_bufs_cnt;
+   sr->instr.slc.value[0] = rte_cpu_to_be_64(sr->instr.slc.value[0]);
+
+   /* word 5 */
+   sr->instr.slc.s.rptr = rte_cpu_to_be_64(sr->rptr);
+   /*
+* No conversion for front data,
+* It goes into payload
+* put GP Header in front data
+*/
+   memcpy(&sr->instr.fdata[0], &sr->gph, sizeof(sr->instr.fdata[0]));
+   sr->instr.fdata[1] = 0;
+   /* flush the soft_req changes before posting the cmd */
+   rte_wmb();
+}
+
+static void
+softreq_copy_iv(struct nitrox_softreq *sr)
+{
+   sr->iv.virt = rte_crypto_op_ctod_offset(sr->op, uint8_t *,
+   sr->ctx->iv.offset);
+   sr->iv.iova = rte_crypto_op_ctophys_offset(sr->op, sr->ctx->iv.offset);
+   sr->iv.len = sr->ctx->iv.length;
+}
+
+static int
+extract_cipher_auth_digest(struct nitrox_softreq *sr,
+  struct nitrox_sglist *diges

[dpdk-dev] [PATCH v4 10/11] test/crypto: add tests for Nitrox PMD

[Nagadheeraj Rottela]

Add hmac(sha1), cbc(aes) authenc tests in the test mechanism.

Signed-off-by: Nagadheeraj Rottela 
---
 app/test/test_cryptodev.c  | 52 ++
 app/test/test_cryptodev.h  |  1 +
 app/test/test_cryptodev_aes_test_vectors.h | 30 +++--
 app/test/test_cryptodev_blockcipher.c  |  9 +-
 app/test/test_cryptodev_blockcipher.h  |  1 +
 5 files changed, 82 insertions(+), 11 deletions(-)

diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index 4197febb0..ed70c3f30 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -2331,6 +2331,25 @@ test_3DES_chain_octeontx_all(void)
 }
 
 static int
+test_AES_chain_nitrox_all(void)
+{
+   struct crypto_testsuite_params *ts_params = &testsuite_params;
+   int status;
+
+   status = test_blockcipher_all_tests(ts_params->mbuf_pool,
+   ts_params->op_mpool,
+   ts_params->session_mpool, ts_params->session_priv_mpool,
+   ts_params->valid_devs[0],
+   rte_cryptodev_driver_id_get(
+   RTE_STR(CRYPTODEV_NAME_NITROX_PMD)),
+   BLKCIPHER_AES_CHAIN_TYPE);
+
+   TEST_ASSERT_EQUAL(status, 0, "Test failed");
+
+   return TEST_SUCCESS;
+}
+
+static int
 test_3DES_cipheronly_octeontx_all(void)
 {
struct crypto_testsuite_params *ts_params = &testsuite_params;
@@ -11969,6 +11988,22 @@ static struct unit_test_suite 
cryptodev_octeontx_testsuite  = {
}
 };
 
+static struct unit_test_suite cryptodev_nitrox_testsuite  = {
+   .suite_name = "Crypto NITROX Unit Test Suite",
+   .setup = testsuite_setup,
+   .teardown = testsuite_teardown,
+   .unit_test_cases = {
+   TEST_CASE_ST(ut_setup, ut_teardown,
+test_device_configure_invalid_dev_id),
+   TEST_CASE_ST(ut_setup, ut_teardown,
+   test_device_configure_invalid_queue_pair_ids),
+   TEST_CASE_ST(ut_setup, ut_teardown,
+test_AES_chain_nitrox_all),
+
+   TEST_CASES_END() /**< NULL terminate unit test array */
+   }
+};
+
 static int
 test_cryptodev_qat(void /*argv __rte_unused, int argc __rte_unused*/)
 {
@@ -12252,6 +12287,22 @@ test_cryptodev_caam_jr(void /*argv __rte_unused, int 
argc __rte_unused*/)
return unit_test_suite_runner(&cryptodev_caam_jr_testsuite);
 }
 
+static int
+test_cryptodev_nitrox(void)
+{
+   gbl_driver_id = rte_cryptodev_driver_id_get(
+   RTE_STR(CRYPTODEV_NAME_NITROX_PMD));
+
+   if (gbl_driver_id == -1) {
+   RTE_LOG(ERR, USER1, "NITROX PMD must be loaded. Check if "
+   "CONFIG_RTE_LIBRTE_PMD_NITROX is enabled "
+   "in config file to run this testsuite.\n");
+   return TEST_FAILED;
+   }
+
+   return unit_test_suite_runner(&cryptodev_nitrox_testsuite);
+}
+
 REGISTER_TEST_COMMAND(cryptodev_qat_autotest, test_cryptodev_qat);
 REGISTER_TEST_COMMAND(cryptodev_aesni_mb_autotest, test_cryptodev_aesni_mb);
 REGISTER_TEST_COMMAND(cryptodev_openssl_autotest, test_cryptodev_openssl);
@@ -12268,3 +12319,4 @@ REGISTER_TEST_COMMAND(cryptodev_ccp_autotest, 
test_cryptodev_ccp);
 REGISTER_TEST_COMMAND(cryptodev_virtio_autotest, test_cryptodev_virtio);
 REGISTER_TEST_COMMAND(cryptodev_octeontx_autotest, test_cryptodev_octeontx);
 REGISTER_TEST_COMMAND(cryptodev_caam_jr_autotest, test_cryptodev_caam_jr);
+REGISTER_TEST_COMMAND(cryptodev_nitrox_autotest, test_cryptodev_nitrox);
diff --git a/app/test/test_cryptodev.h b/app/test/test_cryptodev.h
index 14b54dcb6..afcdaf03f 100644
--- a/app/test/test_cryptodev.h
+++ b/app/test/test_cryptodev.h
@@ -67,6 +67,7 @@
 #define CRYPTODEV_NAME_VIRTIO_PMD  crypto_virtio
 #define CRYPTODEV_NAME_OCTEONTX_SYM_PMDcrypto_octeontx
 #define CRYPTODEV_NAME_CAAM_JR_PMD crypto_caam_jr
+#define CRYPTODEV_NAME_NITROX_PMD  crypto_nitrox
 
 /**
  * Write (spread) data from buffer to mbuf data
diff --git a/app/test/test_cryptodev_aes_test_vectors.h 
b/app/test/test_cryptodev_aes_test_vectors.h
index ee4fdc9a7..476459b66 100644
--- a/app/test/test_cryptodev_aes_test_vectors.h
+++ b/app/test/test_cryptodev_aes_test_vectors.h
@@ -1537,7 +1537,8 @@ static const struct blockcipher_test_case 
aes_chain_test_cases[] = {
.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY_DEC,
.feature_mask = BLOCKCIPHER_TEST_FEATURE_OOP,
.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
-   BLOCKCIPHER_TEST_TARGET_PMD_QAT
+   BLOCKCIPHER_TEST_TARGET_PMD_QAT |
+   BLOCKCIPHER_TEST_TARGET_PMD_NITROX
},
{
.test_descr = "AES-128-CTR HMAC-SHA1 Encryption Digest",
@@ -1638,7 +1639,8 @@ static const struct blockcipher_test_case 
aes_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD

[dpdk-dev] [PATCH v4 11/11] crypto/nitrox: add SHA224 and SHA256 HMAC algorithms

[Nagadheeraj Rottela]

Add SHA224 and SHA256 HMAC algorithms and it's corresponding tests.

Signed-off-by: Nagadheeraj Rottela 
---
 app/test/test_cryptodev_aes_test_vectors.h  | 18 +++
 doc/guides/cryptodevs/features/nitrox.ini   |  2 ++
 drivers/crypto/nitrox/nitrox_sym.c  |  6 
 drivers/crypto/nitrox/nitrox_sym_capabilities.c | 42 +
 4 files changed, 62 insertions(+), 6 deletions(-)

diff --git a/app/test/test_cryptodev_aes_test_vectors.h 
b/app/test/test_cryptodev_aes_test_vectors.h
index 476459b66..46239efb7 100644
--- a/app/test/test_cryptodev_aes_test_vectors.h
+++ b/app/test/test_cryptodev_aes_test_vectors.h
@@ -1723,7 +1723,8 @@ static const struct blockcipher_test_case 
aes_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-   BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+   BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+   BLOCKCIPHER_TEST_TARGET_PMD_NITROX
},
{
.test_descr = "AES-128-CBC HMAC-SHA256 Encryption Digest "
@@ -1732,7 +1733,8 @@ static const struct blockcipher_test_case 
aes_chain_test_cases[] = {
.op_mask = BLOCKCIPHER_TEST_OP_ENC_AUTH_GEN,
.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-   BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+   BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+   BLOCKCIPHER_TEST_TARGET_PMD_NITROX
},
{
.test_descr = "AES-128-CBC HMAC-SHA256 Decryption Digest "
@@ -1748,7 +1750,8 @@ static const struct blockcipher_test_case 
aes_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-   BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+   BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+   BLOCKCIPHER_TEST_TARGET_PMD_NITROX
},
{
.test_descr = "AES-128-CBC HMAC-SHA256 Decryption Digest "
@@ -1757,7 +1760,8 @@ static const struct blockcipher_test_case 
aes_chain_test_cases[] = {
.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY_DEC,
.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
-   BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+   BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+   BLOCKCIPHER_TEST_TARGET_PMD_NITROX
},
{
.test_descr = "AES-128-CBC HMAC-SHA512 Encryption Digest",
@@ -1898,7 +1902,8 @@ static const struct blockcipher_test_case 
aes_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-   BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+   BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+   BLOCKCIPHER_TEST_TARGET_PMD_NITROX
},
{
.test_descr = "AES-128-CBC HMAC-SHA224 Decryption Digest "
@@ -1913,7 +1918,8 @@ static const struct blockcipher_test_case 
aes_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
-   BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+   BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+   BLOCKCIPHER_TEST_TARGET_PMD_NITROX
},
{
.test_descr = "AES-128-CBC HMAC-SHA384 Encryption Digest",
diff --git a/doc/guides/cryptodevs/features/nitrox.ini 
b/doc/guides/cryptodevs/features/nitrox.ini
index 9f9e2619c..ddc3c05f4 100644
--- a/doc/guides/cryptodevs/features/nitrox.ini
+++ b/doc/guides/cryptodevs/features/nitrox.ini
@@ -26,6 +26,8 @@ AES CBC (256)  = Y
 ;
 [Auth]
 SHA1 HMAC= Y
+SHA224 HMAC  = Y
+SHA256 HMAC  = Y
 
 ;
 ; Supported AEAD algorithms of the 'nitrox' crypto driver.
diff --git a/drivers/crypto/nitrox/nitrox_sym.c 
b/drivers/crypto/nitrox/nitrox_sym.c
index 2056e1aae..bba9dbc5b 100644
--- a/drivers/crypto/nitrox/nitrox_sym.c
+++ b/drivers/crypto/nitrox/nitrox_sym.c
@@ -399,6 +399,12 @@ get_flexi_auth_type(enum rte_crypto_auth_algorithm algo)
case RTE_CRYPTO_AUTH_SHA1_HMAC:
type = AUTH_SHA1;
break;
+   case RTE_CRYPTO_AUTH_SHA224_HMAC:
+   type = AUTH_SHA2_SHA224;
+   break;
+   case RTE_CRYPTO_AUTH_SHA256_HMAC:
+   type = AUTH_SHA2_SHA256;
+   break;
default: