[clang] [llvm] [MIPS] Add MIPS i6400 and i6500 processors (PR #130587)

2025-03-15 Thread Mallikarjuna Gouda via cfe-commits 


@@ -43,7 +43,7 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
 Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
   };
 
-  enum class CPU { P5600 };
+  enum class CPU { P5600, I6400 };

mgoudar wrote:

Thanks for quick review!
yes. i6500 is multi-cluster version of i6400 and both are based on MIPS64 
Release 6 ISA.
Hence I kept single subtarget I6400 and reused it in Mips.td for both i6400 and 
i6500.
I have added comments in the changed file Mips.td and MipsSubTarget.h

https://github.com/llvm/llvm-project/pull/130587
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[clang] [llvm] [MIPS] Add MIPS i6400 and i6500 processors (PR #130587)

2025-03-20 Thread Mallikarjuna Gouda via cfe-commits 

mgoudar wrote:

thank you.

https://github.com/llvm/llvm-project/pull/130587
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[clang] [llvm] [MIPS] Define SubTargetFeature for i6500 cpu (PR #132907)

2025-03-25 Thread Mallikarjuna Gouda via cfe-commits 

https://github.com/mgoudar created 
https://github.com/llvm/llvm-project/pull/132907

PR #130587 defined same SubTargetFeature for CPUs i6400 and i6500 which 
resulted into following warning when -mcpu=i6500 was used:

+i6500' is not a recognized feature for this target (ignoring feature)

This PR fixes above issue by defining separate SubTargetFeature for i6500.

>From 752aaecc52b78a86a36d84af4ca42d166bcdc28e Mon Sep 17 00:00:00 2001
From: Mallikarjuna Gouda 
Date: Tue, 25 Mar 2025 15:18:52 +0530
Subject: [PATCH] [MIPS] Define SubTargetFeature for i6500 cpu

PR #130587 defined same SubTargetFeature for CPUs i6400 and i6500
which resulted into following warning when -mcpu=i6500 was used:

+i6500' is not a recognized feature for this target (ignoring feature)

This PR fixes above issue by defining separate SubTargetFeature for
i6500.
---
 clang/test/CodeGen/Mips/subtarget-feature-test.c | 6 ++
 llvm/lib/Target/Mips/Mips.td | 8 ++--
 llvm/lib/Target/Mips/MipsSubtarget.h | 2 +-
 3 files changed, 13 insertions(+), 3 deletions(-)
 create mode 100644 clang/test/CodeGen/Mips/subtarget-feature-test.c

diff --git a/clang/test/CodeGen/Mips/subtarget-feature-test.c 
b/clang/test/CodeGen/Mips/subtarget-feature-test.c
new file mode 100644
index 0..d6a3f08a82de7
--- /dev/null
+++ b/clang/test/CodeGen/Mips/subtarget-feature-test.c
@@ -0,0 +1,6 @@
+// RUN: %clang --target=mips64-linux-gnu -mcpu=i6400 -o %t -c %s 2>&1 | 
FileCheck --allow-empty %s
+// CHECK-NOT: {{.*}} is not a recognized feature for this target
+
+
+// RUN: %clang --target=mips64-linux-gnu -mcpu=i6500 -o %t -c %s 2>&1 | 
FileCheck --allow-empty %s
+// CHECK-NOT: {{.*}} is not a recognized feature for this target
diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td
index 9159d11fd486f..43a5ae8133d83 100644
--- a/llvm/lib/Target/Mips/Mips.td
+++ b/llvm/lib/Target/Mips/Mips.td
@@ -242,7 +242,11 @@ def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
 // same CPU architecture.
 def ImplI6400
 : SubtargetFeature<"i6400", "ProcImpl", "MipsSubtarget::CPU::I6400",
-   "MIPS I6400/I6500 Processors", [FeatureMips64r6]>;
+   "MIPS I6400 Processor", [FeatureMips64r6]>;
+
+def ImplI6500
+: SubtargetFeature<"i6500", "ProcImpl", "MipsSubtarget::CPU::I6500",
+   "MIPS I6500 Processor", [FeatureMips64r6]>;
 
 class Proc Features>
  : ProcessorModel;
@@ -268,7 +272,7 @@ def : Proc<"octeon", [FeatureMips64r2, FeatureCnMips]>;
 def : Proc<"octeon+", [FeatureMips64r2, FeatureCnMips, FeatureCnMipsP]>;
 def : ProcessorModel<"p5600", MipsP5600Model, [ImplP5600]>;
 def : ProcessorModel<"i6400", NoSchedModel, [ImplI6400]>;
-def : ProcessorModel<"i6500", NoSchedModel, [ImplI6400]>;
+def : ProcessorModel<"i6500", NoSchedModel, [ImplI6500]>;
 
 def MipsAsmParser : AsmParser {
   let ShouldEmitMatchRegisterName = 0;
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.h 
b/llvm/lib/Target/Mips/MipsSubtarget.h
index 0c75597d3decf..15127b11d5cdd 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.h
+++ b/llvm/lib/Target/Mips/MipsSubtarget.h
@@ -43,7 +43,7 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
 Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
   };
 
-  enum class CPU { P5600, I6400 };
+  enum class CPU { P5600, I6400, I6500 };
 
   // Used to avoid printing dsp warnings multiple times.
   static bool DspWarningPrinted;

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[clang] [llvm] [MIPS] Define SubTargetFeature for i6500 cpu (PR #132907)

2025-03-25 Thread Mallikarjuna Gouda via cfe-commits 

https://github.com/mgoudar updated 
https://github.com/llvm/llvm-project/pull/132907

>From 752aaecc52b78a86a36d84af4ca42d166bcdc28e Mon Sep 17 00:00:00 2001
From: Mallikarjuna Gouda 
Date: Tue, 25 Mar 2025 15:18:52 +0530
Subject: [PATCH 1/2] [MIPS] Define SubTargetFeature for i6500 cpu

PR #130587 defined same SubTargetFeature for CPUs i6400 and i6500
which resulted into following warning when -mcpu=i6500 was used:

+i6500' is not a recognized feature for this target (ignoring feature)

This PR fixes above issue by defining separate SubTargetFeature for
i6500.
---
 clang/test/CodeGen/Mips/subtarget-feature-test.c | 6 ++
 llvm/lib/Target/Mips/Mips.td | 8 ++--
 llvm/lib/Target/Mips/MipsSubtarget.h | 2 +-
 3 files changed, 13 insertions(+), 3 deletions(-)
 create mode 100644 clang/test/CodeGen/Mips/subtarget-feature-test.c

diff --git a/clang/test/CodeGen/Mips/subtarget-feature-test.c 
b/clang/test/CodeGen/Mips/subtarget-feature-test.c
new file mode 100644
index 0..d6a3f08a82de7
--- /dev/null
+++ b/clang/test/CodeGen/Mips/subtarget-feature-test.c
@@ -0,0 +1,6 @@
+// RUN: %clang --target=mips64-linux-gnu -mcpu=i6400 -o %t -c %s 2>&1 | 
FileCheck --allow-empty %s
+// CHECK-NOT: {{.*}} is not a recognized feature for this target
+
+
+// RUN: %clang --target=mips64-linux-gnu -mcpu=i6500 -o %t -c %s 2>&1 | 
FileCheck --allow-empty %s
+// CHECK-NOT: {{.*}} is not a recognized feature for this target
diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td
index 9159d11fd486f..43a5ae8133d83 100644
--- a/llvm/lib/Target/Mips/Mips.td
+++ b/llvm/lib/Target/Mips/Mips.td
@@ -242,7 +242,11 @@ def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
 // same CPU architecture.
 def ImplI6400
 : SubtargetFeature<"i6400", "ProcImpl", "MipsSubtarget::CPU::I6400",
-   "MIPS I6400/I6500 Processors", [FeatureMips64r6]>;
+   "MIPS I6400 Processor", [FeatureMips64r6]>;
+
+def ImplI6500
+: SubtargetFeature<"i6500", "ProcImpl", "MipsSubtarget::CPU::I6500",
+   "MIPS I6500 Processor", [FeatureMips64r6]>;
 
 class Proc Features>
  : ProcessorModel;
@@ -268,7 +272,7 @@ def : Proc<"octeon", [FeatureMips64r2, FeatureCnMips]>;
 def : Proc<"octeon+", [FeatureMips64r2, FeatureCnMips, FeatureCnMipsP]>;
 def : ProcessorModel<"p5600", MipsP5600Model, [ImplP5600]>;
 def : ProcessorModel<"i6400", NoSchedModel, [ImplI6400]>;
-def : ProcessorModel<"i6500", NoSchedModel, [ImplI6400]>;
+def : ProcessorModel<"i6500", NoSchedModel, [ImplI6500]>;
 
 def MipsAsmParser : AsmParser {
   let ShouldEmitMatchRegisterName = 0;
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.h 
b/llvm/lib/Target/Mips/MipsSubtarget.h
index 0c75597d3decf..15127b11d5cdd 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.h
+++ b/llvm/lib/Target/Mips/MipsSubtarget.h
@@ -43,7 +43,7 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
 Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
   };
 
-  enum class CPU { P5600, I6400 };
+  enum class CPU { P5600, I6400, I6500 };
 
   // Used to avoid printing dsp warnings multiple times.
   static bool DspWarningPrinted;

>From 7d59e510ec1a5e0475918c96cac68699e93a9d90 Mon Sep 17 00:00:00 2001
From: Mallikarjuna Gouda 
Date: Tue, 25 Mar 2025 15:33:00 +0530
Subject: [PATCH 2/2] [MIPS] remove extra line in the test case

---
 clang/test/CodeGen/Mips/subtarget-feature-test.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/clang/test/CodeGen/Mips/subtarget-feature-test.c 
b/clang/test/CodeGen/Mips/subtarget-feature-test.c
index d6a3f08a82de7..7f0b8e7e77135 100644
--- a/clang/test/CodeGen/Mips/subtarget-feature-test.c
+++ b/clang/test/CodeGen/Mips/subtarget-feature-test.c
@@ -1,6 +1,5 @@
 // RUN: %clang --target=mips64-linux-gnu -mcpu=i6400 -o %t -c %s 2>&1 | 
FileCheck --allow-empty %s
 // CHECK-NOT: {{.*}} is not a recognized feature for this target
 
-
 // RUN: %clang --target=mips64-linux-gnu -mcpu=i6500 -o %t -c %s 2>&1 | 
FileCheck --allow-empty %s
 // CHECK-NOT: {{.*}} is not a recognized feature for this target

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[clang] [llvm] [MIPS] Add MIPS i6400 and i6500 processors (PR #130587)

2025-03-19 Thread Mallikarjuna Gouda via cfe-commits 

https://github.com/mgoudar updated 
https://github.com/llvm/llvm-project/pull/130587

>From 4f9c5b5b844a61b760a3462994c7736542c14ca4 Mon Sep 17 00:00:00 2001
From: Mallikarjuna Gouda 
Date: Mon, 10 Mar 2025 15:42:39 +0530
Subject: [PATCH 1/5] [MIPS] Add MIPS i6400 and i6500 processors

The i6400 and i6500 are high performance multi-core microprocessors
from MIPS that provide best in class power efficiency for use in
system-on-chip  (SoC) applications. i6400 and i6500 implements
Release 6 of the MIPS64 Instruction Set Architecture with full
hardware multithreading and hardware virtualization support.

Scheduling model shall be added in separate commit/PR.
---
 clang/lib/Basic/Targets/Mips.cpp  |  4 +++-
 clang/lib/Driver/ToolChains/Arch/Mips.cpp |  4 
 clang/lib/Driver/ToolChains/Gnu.cpp   |  4 +++-
 clang/test/Driver/mips-abi.c  | 24 +++
 llvm/docs/ReleaseNotes.md |  2 ++
 llvm/lib/Target/Mips/Mips.td  | 10 ++
 llvm/lib/Target/Mips/MipsSubtarget.h  |  2 +-
 7 files changed, 47 insertions(+), 3 deletions(-)

diff --git a/clang/lib/Basic/Targets/Mips.cpp b/clang/lib/Basic/Targets/Mips.cpp
index 866be53c8a363..08f9e3c29d1ed 100644
--- a/clang/lib/Basic/Targets/Mips.cpp
+++ b/clang/lib/Basic/Targets/Mips.cpp
@@ -47,6 +47,8 @@ bool MipsTargetInfo::processorSupportsGPR64() const {
   .Case("mips64r6", true)
   .Case("octeon", true)
   .Case("octeon+", true)
+  .Case("i6400", true)
+  .Case("i6500", true)
   .Default(false);
 }
 
@@ -54,7 +56,7 @@ static constexpr llvm::StringLiteral ValidCPUNames[] = {
 {"mips1"},  {"mips2"},{"mips3"},{"mips4"},{"mips5"},
 {"mips32"}, {"mips32r2"}, {"mips32r3"}, {"mips32r5"}, {"mips32r6"},
 {"mips64"}, {"mips64r2"}, {"mips64r3"}, {"mips64r5"}, {"mips64r6"},
-{"octeon"}, {"octeon+"}, {"p5600"}};
+{"octeon"}, {"octeon+"},  {"p5600"},{"i6400"},{"i6500"}};
 
 bool MipsTargetInfo::isValidCPUName(StringRef Name) const {
   return llvm::is_contained(ValidCPUNames, Name);
diff --git a/clang/lib/Driver/ToolChains/Arch/Mips.cpp 
b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
index ca0745fc2b32d..9c817f238524c 100644
--- a/clang/lib/Driver/ToolChains/Arch/Mips.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
@@ -104,6 +104,8 @@ void mips::getMipsCPUAndABI(const ArgList &Args, const 
llvm::Triple &Triple,
   .Case("mips64r6", "n64")
   .Case("octeon", "n64")
   .Case("p5600", "o32")
+  .Case("i6400", "n64")
+  .Case("i6500", "n64")
   .Default("");
   }
 
@@ -514,5 +516,7 @@ bool mips::supportsIndirectJumpHazardBarrier(StringRef 
&CPU) {
   .Case("mips64r6", true)
   .Case("octeon", true)
   .Case("p5600", true)
+  .Case("i6400", true)
+  .Case("i6500", true)
   .Default(false);
 }
diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp 
b/clang/lib/Driver/ToolChains/Gnu.cpp
index f56eeda3cb5f6..68c288f516fba 100644
--- a/clang/lib/Driver/ToolChains/Gnu.cpp
+++ b/clang/lib/Driver/ToolChains/Gnu.cpp
@@ -1501,7 +1501,9 @@ bool clang::driver::findMIPSMultilibs(const Driver &D,
   CPUName == "mips64r5" || CPUName == "octeon" ||
   CPUName == "octeon+",
   "-march=mips64r2", Flags);
-  addMultilibFlag(CPUName == "mips64r6", "-march=mips64r6", Flags);
+  addMultilibFlag(CPUName == "mips64r6" || CPUName == "i6400" ||
+  CPUName == "i6500",
+  "-march=mips64r6", Flags);
   addMultilibFlag(isMicroMips(Args), "-mmicromips", Flags);
   addMultilibFlag(tools::mips::isUCLibc(Args), "-muclibc", Flags);
   addMultilibFlag(tools::mips::isNaN2008(D, Args, TargetTriple), "-mnan=2008",
diff --git a/clang/test/Driver/mips-abi.c b/clang/test/Driver/mips-abi.c
index 06570b50928a1..9a2180c516a61 100644
--- a/clang/test/Driver/mips-abi.c
+++ b/clang/test/Driver/mips-abi.c
@@ -121,6 +121,30 @@
 // MIPS-ARCH-P5600-N64: error: ABI 'n64' is not supported on CPU 'p5600'
 //
 // RUN: %clang --target=mips-linux-gnu -### -c %s \
+// RUN:-march=i6400 2>&1 \
+// RUN:   | FileCheck -check-prefix=MIPS-ARCH-I6400 %s
+// MIPS-ARCH-I6400: "-target-cpu" "i6400"
+// MIPS-ARCH-I6400: "-target-abi" "o32"
+//
+// RUN: %clang --target=mips-linux-gnu -### -c %s \
+// RUN:-march=i6400 -mabi=64 2>&1 \
+// RUN:   | FileCheck -check-prefix=MIPS-ARCH-I6400-N64 %s
+// MIPS-ARCH-I6400-N64: "-target-cpu" "i6400"
+// MIPS-ARCH-I6400-N64: "-target-abi" "n64"
+//
+// RUN: %clang --target=mips-linux-gnu -### -c %s \
+// RUN:-march=i6500 2>&1 \
+// RUN:   | FileCheck -check-prefix=MIPS-ARCH-I6500 %s
+// MIPS-ARCH-I6500: "-target-cpu" "i6500"
+// MIPS-ARCH-I6500: "-target-abi" "o32"
+//
+// RUN: %clang --target=mips-linux-gnu -### -c %s \
+// RUN:-march=i6500 -mabi=64 2>&1 \
+// RUN:   | FileCheck -check-prefix=MIPS-ARCH-I6500-N64 %s
+// MIPS-ARCH-I6500-N64: "-target

[clang] [llvm] [MIPS] Add MIPS i6400 and i6500 processors (PR #130587)

2025-03-19 Thread Mallikarjuna Gouda via cfe-commits 


@@ -121,6 +121,30 @@
 // MIPS-ARCH-P5600-N64: error: ABI 'n64' is not supported on CPU 'p5600'
 //
 // RUN: %clang --target=mips-linux-gnu -### -c %s \
+// RUN:-march=i6400 2>&1 \
+// RUN:   | FileCheck -check-prefix=MIPS-ARCH-I6400 %s
+// MIPS-ARCH-I6400: "-target-cpu" "i6400"
+// MIPS-ARCH-I6400: "-target-abi" "o32"
+//
+// RUN: %clang --target=mips-linux-gnu -### -c %s \
+// RUN:-march=i6400 -mabi=64 2>&1 \
+// RUN:   | FileCheck -check-prefix=MIPS-ARCH-I6400-N64 %s
+// MIPS-ARCH-I6400-N64: "-target-cpu" "i6400"
+// MIPS-ARCH-I6400-N64: "-target-abi" "n64"
+//
+// RUN: %clang --target=mips-linux-gnu -### -c %s \
+// RUN:-march=i6500 2>&1 \
+// RUN:   | FileCheck -check-prefix=MIPS-ARCH-I6500 %s
+// MIPS-ARCH-I6500: "-target-cpu" "i6500"
+// MIPS-ARCH-I6500: "-target-abi" "o32"
+//
+// RUN: %clang --target=mips-linux-gnu -### -c %s \
+// RUN:-march=i6500 -mabi=64 2>&1 \
+// RUN:   | FileCheck -check-prefix=MIPS-ARCH-I6500-N64 %s
+// MIPS-ARCH-I6500-N64: "-target-cpu" "i6500"
+// MIPS-ARCH-I6500-N64: "-target-abi" "n64"
+//

mgoudar wrote:

yes right. in case of mips64, default abi is n64. I have added test case for 
this case. thanks for catching that.

https://github.com/llvm/llvm-project/pull/130587
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[clang] [llvm] [MIPS] Define SubTargetFeature for i6500 cpu (PR #132907)

2025-03-25 Thread Mallikarjuna Gouda via cfe-commits 


@@ -0,0 +1,6 @@
+// RUN: %clang --target=mips64-linux-gnu -mcpu=i6400 -o %t -c %s 2>&1 | 
FileCheck --allow-empty %s
+// CHECK-NOT: {{.*}} is not a recognized feature for this target
+

mgoudar wrote:

thank you for the review. I have removed extra line.

https://github.com/llvm/llvm-project/pull/132907
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[clang] [llvm] [MIPS] Add FeatureMSA to i6400 and i6500 cores (PR #134985)

2025-04-17 Thread Mallikarjuna Gouda via cfe-commits 


@@ -0,0 +1,69 @@
+; Test the MSA intrinsics that are encoded with the SPECIAL instruction format.

mgoudar wrote:

I have written driver test mips-cpus.c instead of codegen as you suggested.

https://github.com/llvm/llvm-project/pull/134985
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[clang] [llvm] [MIPS] Add FeatureMSA to i6400 and i6500 cores (PR #134985)

2025-04-17 Thread Mallikarjuna Gouda via cfe-commits 

https://github.com/mgoudar edited 
https://github.com/llvm/llvm-project/pull/134985
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[clang] [llvm] [MIPS] Add FeatureMSA to i6400 and i6500 cores (PR #134985)

2025-04-23 Thread Mallikarjuna Gouda via cfe-commits 

https://github.com/mgoudar updated 
https://github.com/llvm/llvm-project/pull/134985

>From 36a78bb9fe38781fa8ea126aeae5b7ed48140651 Mon Sep 17 00:00:00 2001
From: Mallikarjuna Gouda 
Date: Tue, 1 Apr 2025 12:35:27 +0530
Subject: [PATCH 1/6] [MIPS] Add FeatureMSA to i6400 and i6500 cores

i6400 and i6500 cores support MIPS SIMD Architecture (MSA) instructions
---
 llvm/lib/Target/Mips/Mips.td|  4 +-
 llvm/test/CodeGen/Mips/msa/i6500.ll | 69 +
 2 files changed, 71 insertions(+), 2 deletions(-)
 create mode 100644 llvm/test/CodeGen/Mips/msa/i6500.ll

diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td
index 43a5ae8133d83..ca3df1fd94144 100644
--- a/llvm/lib/Target/Mips/Mips.td
+++ b/llvm/lib/Target/Mips/Mips.td
@@ -242,11 +242,11 @@ def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
 // same CPU architecture.
 def ImplI6400
 : SubtargetFeature<"i6400", "ProcImpl", "MipsSubtarget::CPU::I6400",
-   "MIPS I6400 Processor", [FeatureMips64r6]>;
+   "MIPS I6400 Processor", [FeatureMips64r6, FeatureMSA]>;
 
 def ImplI6500
 : SubtargetFeature<"i6500", "ProcImpl", "MipsSubtarget::CPU::I6500",
-   "MIPS I6500 Processor", [FeatureMips64r6]>;
+   "MIPS I6500 Processor", [FeatureMips64r6, FeatureMSA]>;
 
 class Proc Features>
  : ProcessorModel;
diff --git a/llvm/test/CodeGen/Mips/msa/i6500.ll 
b/llvm/test/CodeGen/Mips/msa/i6500.ll
new file mode 100644
index 0..b8404ab72fea3
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/msa/i6500.ll
@@ -0,0 +1,69 @@
+; Test the MSA intrinsics that are encoded with the SPECIAL instruction format.
+
+; RUN: llc -mtriple=mips-elf -mcpu=i6500 < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mips64-elf -mcpu=i6500 < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS64
+; RUN: llc -mtriple=mips-elf -mcpu=i6500 < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mips64-elf -mcpu=i6500 < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS64
+; RUN: llc -mtriple=mips64-elf -mcpu=i6500 -mattr=-msa < %s | \
+; RUN:   FileCheck %s --check-prefix=NO-DSLA
+; RUN: llc -mtriple=mips-elf -mcpu=i6400 < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mips64-elf -mcpu=i6400 < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS64
+; RUN: llc -mtriple=mips-elf -mcpu=i6400 < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mips64-elf -mcpu=i6400 < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS64
+; RUN: llc -mtriple=mips64-elf -mcpu=i6400 -mattr=-msa < %s | \
+; RUN:   FileCheck %s --check-prefix=NO-DSLA
+
+define i32 @llvm_mips_lsa_test(i32 %a, i32 %b) nounwind {
+entry:
+  %0 = tail call i32 @llvm.mips.lsa(i32 %a, i32 %b, i32 2)
+  ret i32 %0
+}
+
+declare i32 @llvm.mips.lsa(i32, i32, i32) nounwind
+
+; MIPS32: llvm_mips_lsa_test:
+; MIPS32: lsa {{\$[0-9]+}}, $5, $4, 2
+; MIPS32: .size llvm_mips_lsa_test
+
+define i32 @lsa_test(i32 %a, i32 %b) nounwind {
+entry:
+  %0 = shl i32 %b, 2
+  %1 = add i32 %a, %0
+  ret i32 %1
+}
+
+; MIPS32: lsa_test:
+; MIPS32: lsa {{\$[0-9]+}}, $5, $4, 2
+; MIPS32: .size lsa_test
+
+define i64 @llvm_mips_dlsa_test(i64 %a, i64 %b) nounwind {
+entry:
+  %0 = tail call i64 @llvm.mips.dlsa(i64 %a, i64 %b, i32 2)
+  ret i64 %0
+}
+
+declare i64 @llvm.mips.dlsa(i64, i64, i32) nounwind
+
+; MIPS64: llvm_mips_dlsa_test:
+; MIPS64: dlsa {{\$[0-9]+}}, $5, $4, 2
+; MIPS64: .size llvm_mips_dlsa_test
+; NO-DSLA-NOT: dlsa {{\$[0-9]+}}, $5, $4, 2
+define i64 @dlsa_test(i64 %a, i64 %b) nounwind {
+entry:
+  %0 = shl i64 %b, 2
+  %1 = add i64 %a, %0
+  ret i64 %1
+}
+
+; MIPS64: dlsa_test:
+; MIPS64: dlsa {{\$[0-9]+}}, $5, $4, 2
+; MIPS64: .size dlsa_test
+; NO-DSLA-NOT: dlsa {{\$[0-9]+}}, $5, $4, 2

>From 4ed92eba68d556a0b2badbde1a39e35349a38d98 Mon Sep 17 00:00:00 2001
From: Mallikarjuna Gouda 
Date: Thu, 10 Apr 2025 10:47:30 +0530
Subject: [PATCH 2/6] Update test case with update_llc_test_checks.py

---
 llvm/test/CodeGen/Mips/msa/i6500.ll | 105 
 1 file changed, 62 insertions(+), 43 deletions(-)

diff --git a/llvm/test/CodeGen/Mips/msa/i6500.ll 
b/llvm/test/CodeGen/Mips/msa/i6500.ll
index b8404ab72fea3..779dbf1b1c165 100644
--- a/llvm/test/CodeGen/Mips/msa/i6500.ll
+++ b/llvm/test/CodeGen/Mips/msa/i6500.ll
@@ -1,69 +1,88 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 5
 ; Test the MSA intrinsics that are encoded with the SPECIAL instruction format.
 
 ; RUN: llc -mtriple=mips-elf -mcpu=i6500 < %s | \
 ; RUN:   FileCheck %s --check-prefix=MIPS32
-; RUN: llc -mtriple=mips64-elf -mcpu=i6500 < %s | \
-; RUN:   FileCheck %s --check-prefix=MIPS64
-; RUN: llc -mtriple=mips-elf -mcpu=i6500 < %s | \
-; RUN:   FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mips-elf -mcpu=i6500 -mattr=-msa < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS32-NO-LSA
+
 ; RUN: ll

[clang] [llvm] [MIPS] Add FeatureMSA to i6400 and i6500 cores (PR #134985)

2025-04-23 Thread Mallikarjuna Gouda via cfe-commits 


@@ -0,0 +1,69 @@
+; Test the MSA intrinsics that are encoded with the SPECIAL instruction format.

mgoudar wrote:

I have enabled MSA feature from driver also when -mcpu i6500/i6400 is 
specified. Also I have added codegen test to verify MSA instructions when 
i650/i6400 cpu is specified. please review

https://github.com/llvm/llvm-project/pull/134985
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[clang] [llvm] [MIPS] Add FeatureMSA to i6400 and i6500 cores (PR #134985)

2025-04-23 Thread Mallikarjuna Gouda via cfe-commits 


@@ -0,0 +1,9 @@
+// Check target CPUs are correctly passed.
+
+// RUN: %clang --target=mips64 -### -c %s 2>&1 -mcpu=i6400 -mmsa | FileCheck 
-check-prefix=MCPU-I6400 %s
+// MCPU-I6400: "-target-cpu" "i6400"

mgoudar wrote:

I modified test to verify abicalls feature as well. I see that mips-features.c 
test available to verify other features based on the options

https://github.com/llvm/llvm-project/pull/134985
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[clang] [llvm] [MIPS] Add FeatureMSA to i6400 and i6500 cores (PR #134985)

2025-04-17 Thread Mallikarjuna Gouda via cfe-commits 

https://github.com/mgoudar updated 
https://github.com/llvm/llvm-project/pull/134985

>From 36a78bb9fe38781fa8ea126aeae5b7ed48140651 Mon Sep 17 00:00:00 2001
From: Mallikarjuna Gouda 
Date: Tue, 1 Apr 2025 12:35:27 +0530
Subject: [PATCH 1/3] [MIPS] Add FeatureMSA to i6400 and i6500 cores

i6400 and i6500 cores support MIPS SIMD Architecture (MSA) instructions
---
 llvm/lib/Target/Mips/Mips.td|  4 +-
 llvm/test/CodeGen/Mips/msa/i6500.ll | 69 +
 2 files changed, 71 insertions(+), 2 deletions(-)
 create mode 100644 llvm/test/CodeGen/Mips/msa/i6500.ll

diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td
index 43a5ae8133d83..ca3df1fd94144 100644
--- a/llvm/lib/Target/Mips/Mips.td
+++ b/llvm/lib/Target/Mips/Mips.td
@@ -242,11 +242,11 @@ def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
 // same CPU architecture.
 def ImplI6400
 : SubtargetFeature<"i6400", "ProcImpl", "MipsSubtarget::CPU::I6400",
-   "MIPS I6400 Processor", [FeatureMips64r6]>;
+   "MIPS I6400 Processor", [FeatureMips64r6, FeatureMSA]>;
 
 def ImplI6500
 : SubtargetFeature<"i6500", "ProcImpl", "MipsSubtarget::CPU::I6500",
-   "MIPS I6500 Processor", [FeatureMips64r6]>;
+   "MIPS I6500 Processor", [FeatureMips64r6, FeatureMSA]>;
 
 class Proc Features>
  : ProcessorModel;
diff --git a/llvm/test/CodeGen/Mips/msa/i6500.ll 
b/llvm/test/CodeGen/Mips/msa/i6500.ll
new file mode 100644
index 0..b8404ab72fea3
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/msa/i6500.ll
@@ -0,0 +1,69 @@
+; Test the MSA intrinsics that are encoded with the SPECIAL instruction format.
+
+; RUN: llc -mtriple=mips-elf -mcpu=i6500 < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mips64-elf -mcpu=i6500 < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS64
+; RUN: llc -mtriple=mips-elf -mcpu=i6500 < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mips64-elf -mcpu=i6500 < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS64
+; RUN: llc -mtriple=mips64-elf -mcpu=i6500 -mattr=-msa < %s | \
+; RUN:   FileCheck %s --check-prefix=NO-DSLA
+; RUN: llc -mtriple=mips-elf -mcpu=i6400 < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mips64-elf -mcpu=i6400 < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS64
+; RUN: llc -mtriple=mips-elf -mcpu=i6400 < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mips64-elf -mcpu=i6400 < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS64
+; RUN: llc -mtriple=mips64-elf -mcpu=i6400 -mattr=-msa < %s | \
+; RUN:   FileCheck %s --check-prefix=NO-DSLA
+
+define i32 @llvm_mips_lsa_test(i32 %a, i32 %b) nounwind {
+entry:
+  %0 = tail call i32 @llvm.mips.lsa(i32 %a, i32 %b, i32 2)
+  ret i32 %0
+}
+
+declare i32 @llvm.mips.lsa(i32, i32, i32) nounwind
+
+; MIPS32: llvm_mips_lsa_test:
+; MIPS32: lsa {{\$[0-9]+}}, $5, $4, 2
+; MIPS32: .size llvm_mips_lsa_test
+
+define i32 @lsa_test(i32 %a, i32 %b) nounwind {
+entry:
+  %0 = shl i32 %b, 2
+  %1 = add i32 %a, %0
+  ret i32 %1
+}
+
+; MIPS32: lsa_test:
+; MIPS32: lsa {{\$[0-9]+}}, $5, $4, 2
+; MIPS32: .size lsa_test
+
+define i64 @llvm_mips_dlsa_test(i64 %a, i64 %b) nounwind {
+entry:
+  %0 = tail call i64 @llvm.mips.dlsa(i64 %a, i64 %b, i32 2)
+  ret i64 %0
+}
+
+declare i64 @llvm.mips.dlsa(i64, i64, i32) nounwind
+
+; MIPS64: llvm_mips_dlsa_test:
+; MIPS64: dlsa {{\$[0-9]+}}, $5, $4, 2
+; MIPS64: .size llvm_mips_dlsa_test
+; NO-DSLA-NOT: dlsa {{\$[0-9]+}}, $5, $4, 2
+define i64 @dlsa_test(i64 %a, i64 %b) nounwind {
+entry:
+  %0 = shl i64 %b, 2
+  %1 = add i64 %a, %0
+  ret i64 %1
+}
+
+; MIPS64: dlsa_test:
+; MIPS64: dlsa {{\$[0-9]+}}, $5, $4, 2
+; MIPS64: .size dlsa_test
+; NO-DSLA-NOT: dlsa {{\$[0-9]+}}, $5, $4, 2

>From 4ed92eba68d556a0b2badbde1a39e35349a38d98 Mon Sep 17 00:00:00 2001
From: Mallikarjuna Gouda 
Date: Thu, 10 Apr 2025 10:47:30 +0530
Subject: [PATCH 2/3] Update test case with update_llc_test_checks.py

---
 llvm/test/CodeGen/Mips/msa/i6500.ll | 105 
 1 file changed, 62 insertions(+), 43 deletions(-)

diff --git a/llvm/test/CodeGen/Mips/msa/i6500.ll 
b/llvm/test/CodeGen/Mips/msa/i6500.ll
index b8404ab72fea3..779dbf1b1c165 100644
--- a/llvm/test/CodeGen/Mips/msa/i6500.ll
+++ b/llvm/test/CodeGen/Mips/msa/i6500.ll
@@ -1,69 +1,88 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 5
 ; Test the MSA intrinsics that are encoded with the SPECIAL instruction format.
 
 ; RUN: llc -mtriple=mips-elf -mcpu=i6500 < %s | \
 ; RUN:   FileCheck %s --check-prefix=MIPS32
-; RUN: llc -mtriple=mips64-elf -mcpu=i6500 < %s | \
-; RUN:   FileCheck %s --check-prefix=MIPS64
-; RUN: llc -mtriple=mips-elf -mcpu=i6500 < %s | \
-; RUN:   FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mips-elf -mcpu=i6500 -mattr=-msa < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS32-NO-LSA
+
 ; RUN: ll

[clang] [llvm] [MIPS] Add FeatureMSA to i6400 and i6500 cores (PR #134985)

2025-05-06 Thread Mallikarjuna Gouda via cfe-commits 

https://github.com/mgoudar updated 
https://github.com/llvm/llvm-project/pull/134985



  



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[clang] [llvm] [MIPS] Add FeatureMSA to i6400 and i6500 cores (PR #134985)

2025-04-23 Thread Mallikarjuna Gouda via cfe-commits 

https://github.com/mgoudar updated 
https://github.com/llvm/llvm-project/pull/134985

>From 36a78bb9fe38781fa8ea126aeae5b7ed48140651 Mon Sep 17 00:00:00 2001
From: Mallikarjuna Gouda 
Date: Tue, 1 Apr 2025 12:35:27 +0530
Subject: [PATCH 1/5] [MIPS] Add FeatureMSA to i6400 and i6500 cores

i6400 and i6500 cores support MIPS SIMD Architecture (MSA) instructions
---
 llvm/lib/Target/Mips/Mips.td|  4 +-
 llvm/test/CodeGen/Mips/msa/i6500.ll | 69 +
 2 files changed, 71 insertions(+), 2 deletions(-)
 create mode 100644 llvm/test/CodeGen/Mips/msa/i6500.ll

diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td
index 43a5ae8133d83..ca3df1fd94144 100644
--- a/llvm/lib/Target/Mips/Mips.td
+++ b/llvm/lib/Target/Mips/Mips.td
@@ -242,11 +242,11 @@ def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
 // same CPU architecture.
 def ImplI6400
 : SubtargetFeature<"i6400", "ProcImpl", "MipsSubtarget::CPU::I6400",
-   "MIPS I6400 Processor", [FeatureMips64r6]>;
+   "MIPS I6400 Processor", [FeatureMips64r6, FeatureMSA]>;
 
 def ImplI6500
 : SubtargetFeature<"i6500", "ProcImpl", "MipsSubtarget::CPU::I6500",
-   "MIPS I6500 Processor", [FeatureMips64r6]>;
+   "MIPS I6500 Processor", [FeatureMips64r6, FeatureMSA]>;
 
 class Proc Features>
  : ProcessorModel;
diff --git a/llvm/test/CodeGen/Mips/msa/i6500.ll 
b/llvm/test/CodeGen/Mips/msa/i6500.ll
new file mode 100644
index 0..b8404ab72fea3
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/msa/i6500.ll
@@ -0,0 +1,69 @@
+; Test the MSA intrinsics that are encoded with the SPECIAL instruction format.
+
+; RUN: llc -mtriple=mips-elf -mcpu=i6500 < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mips64-elf -mcpu=i6500 < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS64
+; RUN: llc -mtriple=mips-elf -mcpu=i6500 < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mips64-elf -mcpu=i6500 < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS64
+; RUN: llc -mtriple=mips64-elf -mcpu=i6500 -mattr=-msa < %s | \
+; RUN:   FileCheck %s --check-prefix=NO-DSLA
+; RUN: llc -mtriple=mips-elf -mcpu=i6400 < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mips64-elf -mcpu=i6400 < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS64
+; RUN: llc -mtriple=mips-elf -mcpu=i6400 < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mips64-elf -mcpu=i6400 < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS64
+; RUN: llc -mtriple=mips64-elf -mcpu=i6400 -mattr=-msa < %s | \
+; RUN:   FileCheck %s --check-prefix=NO-DSLA
+
+define i32 @llvm_mips_lsa_test(i32 %a, i32 %b) nounwind {
+entry:
+  %0 = tail call i32 @llvm.mips.lsa(i32 %a, i32 %b, i32 2)
+  ret i32 %0
+}
+
+declare i32 @llvm.mips.lsa(i32, i32, i32) nounwind
+
+; MIPS32: llvm_mips_lsa_test:
+; MIPS32: lsa {{\$[0-9]+}}, $5, $4, 2
+; MIPS32: .size llvm_mips_lsa_test
+
+define i32 @lsa_test(i32 %a, i32 %b) nounwind {
+entry:
+  %0 = shl i32 %b, 2
+  %1 = add i32 %a, %0
+  ret i32 %1
+}
+
+; MIPS32: lsa_test:
+; MIPS32: lsa {{\$[0-9]+}}, $5, $4, 2
+; MIPS32: .size lsa_test
+
+define i64 @llvm_mips_dlsa_test(i64 %a, i64 %b) nounwind {
+entry:
+  %0 = tail call i64 @llvm.mips.dlsa(i64 %a, i64 %b, i32 2)
+  ret i64 %0
+}
+
+declare i64 @llvm.mips.dlsa(i64, i64, i32) nounwind
+
+; MIPS64: llvm_mips_dlsa_test:
+; MIPS64: dlsa {{\$[0-9]+}}, $5, $4, 2
+; MIPS64: .size llvm_mips_dlsa_test
+; NO-DSLA-NOT: dlsa {{\$[0-9]+}}, $5, $4, 2
+define i64 @dlsa_test(i64 %a, i64 %b) nounwind {
+entry:
+  %0 = shl i64 %b, 2
+  %1 = add i64 %a, %0
+  ret i64 %1
+}
+
+; MIPS64: dlsa_test:
+; MIPS64: dlsa {{\$[0-9]+}}, $5, $4, 2
+; MIPS64: .size dlsa_test
+; NO-DSLA-NOT: dlsa {{\$[0-9]+}}, $5, $4, 2

>From 4ed92eba68d556a0b2badbde1a39e35349a38d98 Mon Sep 17 00:00:00 2001
From: Mallikarjuna Gouda 
Date: Thu, 10 Apr 2025 10:47:30 +0530
Subject: [PATCH 2/5] Update test case with update_llc_test_checks.py

---
 llvm/test/CodeGen/Mips/msa/i6500.ll | 105 
 1 file changed, 62 insertions(+), 43 deletions(-)

diff --git a/llvm/test/CodeGen/Mips/msa/i6500.ll 
b/llvm/test/CodeGen/Mips/msa/i6500.ll
index b8404ab72fea3..779dbf1b1c165 100644
--- a/llvm/test/CodeGen/Mips/msa/i6500.ll
+++ b/llvm/test/CodeGen/Mips/msa/i6500.ll
@@ -1,69 +1,88 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 5
 ; Test the MSA intrinsics that are encoded with the SPECIAL instruction format.
 
 ; RUN: llc -mtriple=mips-elf -mcpu=i6500 < %s | \
 ; RUN:   FileCheck %s --check-prefix=MIPS32
-; RUN: llc -mtriple=mips64-elf -mcpu=i6500 < %s | \
-; RUN:   FileCheck %s --check-prefix=MIPS64
-; RUN: llc -mtriple=mips-elf -mcpu=i6500 < %s | \
-; RUN:   FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mips-elf -mcpu=i6500 -mattr=-msa < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS32-NO-LSA
+
 ; RUN: ll

[clang] [llvm] [MIPS] Add FeatureMSA to i6400 and i6500 cores (PR #134985)

2025-05-08 Thread Mallikarjuna Gouda via cfe-commits 

mgoudar wrote:

hi @brad0 I am seeing fails in https://lab.llvm.org/buildbot/#/builders/94 post 
this pr merge. 
test llvm/test/CodeGen/Mips/msa/arithmetic.ll fails with a crash. I am trying 
to reproduce at my side


https://github.com/llvm/llvm-project/pull/134985
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[clang] [llvm] [MIPS] Add MIPS i6400 and i6500 processors (PR #130587)

2025-03-11 Thread Mallikarjuna Gouda via cfe-commits 

https://github.com/mgoudar edited 
https://github.com/llvm/llvm-project/pull/130587
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[clang] [llvm] [MIPS] Add MIPS i6400 and i6500 processors (PR #130587)

2025-03-11 Thread Mallikarjuna Gouda via cfe-commits 

https://github.com/mgoudar updated 
https://github.com/llvm/llvm-project/pull/130587

>From 4f9c5b5b844a61b760a3462994c7736542c14ca4 Mon Sep 17 00:00:00 2001
From: Mallikarjuna Gouda 
Date: Mon, 10 Mar 2025 15:42:39 +0530
Subject: [PATCH 1/2] [MIPS] Add MIPS i6400 and i6500 processors

The i6400 and i6500 are high performance multi-core microprocessors
from MIPS that provide best in class power efficiency for use in
system-on-chip  (SoC) applications. i6400 and i6500 implements
Release 6 of the MIPS64 Instruction Set Architecture with full
hardware multithreading and hardware virtualization support.

Scheduling model shall be added in separate commit/PR.
---
 clang/lib/Basic/Targets/Mips.cpp  |  4 +++-
 clang/lib/Driver/ToolChains/Arch/Mips.cpp |  4 
 clang/lib/Driver/ToolChains/Gnu.cpp   |  4 +++-
 clang/test/Driver/mips-abi.c  | 24 +++
 llvm/docs/ReleaseNotes.md |  2 ++
 llvm/lib/Target/Mips/Mips.td  | 10 ++
 llvm/lib/Target/Mips/MipsSubtarget.h  |  2 +-
 7 files changed, 47 insertions(+), 3 deletions(-)

diff --git a/clang/lib/Basic/Targets/Mips.cpp b/clang/lib/Basic/Targets/Mips.cpp
index 866be53c8a363..08f9e3c29d1ed 100644
--- a/clang/lib/Basic/Targets/Mips.cpp
+++ b/clang/lib/Basic/Targets/Mips.cpp
@@ -47,6 +47,8 @@ bool MipsTargetInfo::processorSupportsGPR64() const {
   .Case("mips64r6", true)
   .Case("octeon", true)
   .Case("octeon+", true)
+  .Case("i6400", true)
+  .Case("i6500", true)
   .Default(false);
 }
 
@@ -54,7 +56,7 @@ static constexpr llvm::StringLiteral ValidCPUNames[] = {
 {"mips1"},  {"mips2"},{"mips3"},{"mips4"},{"mips5"},
 {"mips32"}, {"mips32r2"}, {"mips32r3"}, {"mips32r5"}, {"mips32r6"},
 {"mips64"}, {"mips64r2"}, {"mips64r3"}, {"mips64r5"}, {"mips64r6"},
-{"octeon"}, {"octeon+"}, {"p5600"}};
+{"octeon"}, {"octeon+"},  {"p5600"},{"i6400"},{"i6500"}};
 
 bool MipsTargetInfo::isValidCPUName(StringRef Name) const {
   return llvm::is_contained(ValidCPUNames, Name);
diff --git a/clang/lib/Driver/ToolChains/Arch/Mips.cpp 
b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
index ca0745fc2b32d..9c817f238524c 100644
--- a/clang/lib/Driver/ToolChains/Arch/Mips.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
@@ -104,6 +104,8 @@ void mips::getMipsCPUAndABI(const ArgList &Args, const 
llvm::Triple &Triple,
   .Case("mips64r6", "n64")
   .Case("octeon", "n64")
   .Case("p5600", "o32")
+  .Case("i6400", "n64")
+  .Case("i6500", "n64")
   .Default("");
   }
 
@@ -514,5 +516,7 @@ bool mips::supportsIndirectJumpHazardBarrier(StringRef 
&CPU) {
   .Case("mips64r6", true)
   .Case("octeon", true)
   .Case("p5600", true)
+  .Case("i6400", true)
+  .Case("i6500", true)
   .Default(false);
 }
diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp 
b/clang/lib/Driver/ToolChains/Gnu.cpp
index f56eeda3cb5f6..68c288f516fba 100644
--- a/clang/lib/Driver/ToolChains/Gnu.cpp
+++ b/clang/lib/Driver/ToolChains/Gnu.cpp
@@ -1501,7 +1501,9 @@ bool clang::driver::findMIPSMultilibs(const Driver &D,
   CPUName == "mips64r5" || CPUName == "octeon" ||
   CPUName == "octeon+",
   "-march=mips64r2", Flags);
-  addMultilibFlag(CPUName == "mips64r6", "-march=mips64r6", Flags);
+  addMultilibFlag(CPUName == "mips64r6" || CPUName == "i6400" ||
+  CPUName == "i6500",
+  "-march=mips64r6", Flags);
   addMultilibFlag(isMicroMips(Args), "-mmicromips", Flags);
   addMultilibFlag(tools::mips::isUCLibc(Args), "-muclibc", Flags);
   addMultilibFlag(tools::mips::isNaN2008(D, Args, TargetTriple), "-mnan=2008",
diff --git a/clang/test/Driver/mips-abi.c b/clang/test/Driver/mips-abi.c
index 06570b50928a1..9a2180c516a61 100644
--- a/clang/test/Driver/mips-abi.c
+++ b/clang/test/Driver/mips-abi.c
@@ -121,6 +121,30 @@
 // MIPS-ARCH-P5600-N64: error: ABI 'n64' is not supported on CPU 'p5600'
 //
 // RUN: %clang --target=mips-linux-gnu -### -c %s \
+// RUN:-march=i6400 2>&1 \
+// RUN:   | FileCheck -check-prefix=MIPS-ARCH-I6400 %s
+// MIPS-ARCH-I6400: "-target-cpu" "i6400"
+// MIPS-ARCH-I6400: "-target-abi" "o32"
+//
+// RUN: %clang --target=mips-linux-gnu -### -c %s \
+// RUN:-march=i6400 -mabi=64 2>&1 \
+// RUN:   | FileCheck -check-prefix=MIPS-ARCH-I6400-N64 %s
+// MIPS-ARCH-I6400-N64: "-target-cpu" "i6400"
+// MIPS-ARCH-I6400-N64: "-target-abi" "n64"
+//
+// RUN: %clang --target=mips-linux-gnu -### -c %s \
+// RUN:-march=i6500 2>&1 \
+// RUN:   | FileCheck -check-prefix=MIPS-ARCH-I6500 %s
+// MIPS-ARCH-I6500: "-target-cpu" "i6500"
+// MIPS-ARCH-I6500: "-target-abi" "o32"
+//
+// RUN: %clang --target=mips-linux-gnu -### -c %s \
+// RUN:-march=i6500 -mabi=64 2>&1 \
+// RUN:   | FileCheck -check-prefix=MIPS-ARCH-I6500-N64 %s
+// MIPS-ARCH-I6500-N64: "-target

[clang] [llvm] [MIPS] Add MIPS i6400 and i6500 processors (PR #130587)

2025-03-11 Thread Mallikarjuna Gouda via cfe-commits 

https://github.com/mgoudar created 
https://github.com/llvm/llvm-project/pull/130587

The i6400 and i6500 are high performance multi-core microprocessors from MIPS 
that provide best in class power efficiency for use in system-on-chip  (SoC) 
applications. i6400 and i6500 implements Release 6 of the MIPS64 Instruction 
Set Architecture with full hardware multithreading and hardware virtualization 
support.

Scheduling model shall be added in separate commit/PR.

>From d3657462dfed03ac5f7699193ebc02e978576215 Mon Sep 17 00:00:00 2001
From: Mallikarjuna Gouda 
Date: Mon, 10 Mar 2025 15:42:39 +0530
Subject: [PATCH] [MIPS] Add MIPS i6400 and i6500 processors

The i6400 and i6500 are high performance multi-core microprocessors
from MIPS that provide best in class power efficiency for use in
system-on-chip  (SoC) applications. i6400 and i6500 implements
Release 6 of the MIPS64 Instruction Set Architecture with full
hardware multithreading and hardware virtualization support.

Scheduling model shall be added in separate commit/PR.
---
 clang/lib/Basic/Targets/Mips.cpp  |  4 +++-
 clang/lib/Driver/ToolChains/Arch/Mips.cpp |  4 
 clang/lib/Driver/ToolChains/Gnu.cpp   |  4 +++-
 clang/test/Driver/mips-abi.c  | 24 +++
 llvm/docs/ReleaseNotes.md |  2 ++
 llvm/lib/Target/Mips/Mips.td  | 10 ++
 llvm/lib/Target/Mips/MipsSubtarget.h  |  2 +-
 7 files changed, 47 insertions(+), 3 deletions(-)

diff --git a/clang/lib/Basic/Targets/Mips.cpp b/clang/lib/Basic/Targets/Mips.cpp
index 866be53c8a363..08f9e3c29d1ed 100644
--- a/clang/lib/Basic/Targets/Mips.cpp
+++ b/clang/lib/Basic/Targets/Mips.cpp
@@ -47,6 +47,8 @@ bool MipsTargetInfo::processorSupportsGPR64() const {
   .Case("mips64r6", true)
   .Case("octeon", true)
   .Case("octeon+", true)
+  .Case("i6400", true)
+  .Case("i6500", true)
   .Default(false);
 }
 
@@ -54,7 +56,7 @@ static constexpr llvm::StringLiteral ValidCPUNames[] = {
 {"mips1"},  {"mips2"},{"mips3"},{"mips4"},{"mips5"},
 {"mips32"}, {"mips32r2"}, {"mips32r3"}, {"mips32r5"}, {"mips32r6"},
 {"mips64"}, {"mips64r2"}, {"mips64r3"}, {"mips64r5"}, {"mips64r6"},
-{"octeon"}, {"octeon+"}, {"p5600"}};
+{"octeon"}, {"octeon+"},  {"p5600"},{"i6400"},{"i6500"}};
 
 bool MipsTargetInfo::isValidCPUName(StringRef Name) const {
   return llvm::is_contained(ValidCPUNames, Name);
diff --git a/clang/lib/Driver/ToolChains/Arch/Mips.cpp 
b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
index ca0745fc2b32d..9c817f238524c 100644
--- a/clang/lib/Driver/ToolChains/Arch/Mips.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
@@ -104,6 +104,8 @@ void mips::getMipsCPUAndABI(const ArgList &Args, const 
llvm::Triple &Triple,
   .Case("mips64r6", "n64")
   .Case("octeon", "n64")
   .Case("p5600", "o32")
+  .Case("i6400", "n64")
+  .Case("i6500", "n64")
   .Default("");
   }
 
@@ -514,5 +516,7 @@ bool mips::supportsIndirectJumpHazardBarrier(StringRef 
&CPU) {
   .Case("mips64r6", true)
   .Case("octeon", true)
   .Case("p5600", true)
+  .Case("i6400", true)
+  .Case("i6500", true)
   .Default(false);
 }
diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp 
b/clang/lib/Driver/ToolChains/Gnu.cpp
index f56eeda3cb5f6..68c288f516fba 100644
--- a/clang/lib/Driver/ToolChains/Gnu.cpp
+++ b/clang/lib/Driver/ToolChains/Gnu.cpp
@@ -1501,7 +1501,9 @@ bool clang::driver::findMIPSMultilibs(const Driver &D,
   CPUName == "mips64r5" || CPUName == "octeon" ||
   CPUName == "octeon+",
   "-march=mips64r2", Flags);
-  addMultilibFlag(CPUName == "mips64r6", "-march=mips64r6", Flags);
+  addMultilibFlag(CPUName == "mips64r6" || CPUName == "i6400" ||
+  CPUName == "i6500",
+  "-march=mips64r6", Flags);
   addMultilibFlag(isMicroMips(Args), "-mmicromips", Flags);
   addMultilibFlag(tools::mips::isUCLibc(Args), "-muclibc", Flags);
   addMultilibFlag(tools::mips::isNaN2008(D, Args, TargetTriple), "-mnan=2008",
diff --git a/clang/test/Driver/mips-abi.c b/clang/test/Driver/mips-abi.c
index 06570b50928a1..9a2180c516a61 100644
--- a/clang/test/Driver/mips-abi.c
+++ b/clang/test/Driver/mips-abi.c
@@ -121,6 +121,30 @@
 // MIPS-ARCH-P5600-N64: error: ABI 'n64' is not supported on CPU 'p5600'
 //
 // RUN: %clang --target=mips-linux-gnu -### -c %s \
+// RUN:-march=i6400 2>&1 \
+// RUN:   | FileCheck -check-prefix=MIPS-ARCH-I6400 %s
+// MIPS-ARCH-I6400: "-target-cpu" "i6400"
+// MIPS-ARCH-I6400: "-target-abi" "o32"
+//
+// RUN: %clang --target=mips-linux-gnu -### -c %s \
+// RUN:-march=i6400 -mabi=64 2>&1 \
+// RUN:   | FileCheck -check-prefix=MIPS-ARCH-I6400-N64 %s
+// MIPS-ARCH-I6400-N64: "-target-cpu" "i6400"
+// MIPS-ARCH-I6400-N64: "-target-abi" "n64"
+//
+// RUN: %clang --target=mips-linux-gnu -### -c

[clang] [llvm] [MIPS] Add MIPS i6400 and i6500 processors (PR #130587)

2025-03-12 Thread Mallikarjuna Gouda via cfe-commits 

https://github.com/mgoudar updated 
https://github.com/llvm/llvm-project/pull/130587

>From 4f9c5b5b844a61b760a3462994c7736542c14ca4 Mon Sep 17 00:00:00 2001
From: Mallikarjuna Gouda 
Date: Mon, 10 Mar 2025 15:42:39 +0530
Subject: [PATCH 1/4] [MIPS] Add MIPS i6400 and i6500 processors

The i6400 and i6500 are high performance multi-core microprocessors
from MIPS that provide best in class power efficiency for use in
system-on-chip  (SoC) applications. i6400 and i6500 implements
Release 6 of the MIPS64 Instruction Set Architecture with full
hardware multithreading and hardware virtualization support.

Scheduling model shall be added in separate commit/PR.
---
 clang/lib/Basic/Targets/Mips.cpp  |  4 +++-
 clang/lib/Driver/ToolChains/Arch/Mips.cpp |  4 
 clang/lib/Driver/ToolChains/Gnu.cpp   |  4 +++-
 clang/test/Driver/mips-abi.c  | 24 +++
 llvm/docs/ReleaseNotes.md |  2 ++
 llvm/lib/Target/Mips/Mips.td  | 10 ++
 llvm/lib/Target/Mips/MipsSubtarget.h  |  2 +-
 7 files changed, 47 insertions(+), 3 deletions(-)

diff --git a/clang/lib/Basic/Targets/Mips.cpp b/clang/lib/Basic/Targets/Mips.cpp
index 866be53c8a363..08f9e3c29d1ed 100644
--- a/clang/lib/Basic/Targets/Mips.cpp
+++ b/clang/lib/Basic/Targets/Mips.cpp
@@ -47,6 +47,8 @@ bool MipsTargetInfo::processorSupportsGPR64() const {
   .Case("mips64r6", true)
   .Case("octeon", true)
   .Case("octeon+", true)
+  .Case("i6400", true)
+  .Case("i6500", true)
   .Default(false);
 }
 
@@ -54,7 +56,7 @@ static constexpr llvm::StringLiteral ValidCPUNames[] = {
 {"mips1"},  {"mips2"},{"mips3"},{"mips4"},{"mips5"},
 {"mips32"}, {"mips32r2"}, {"mips32r3"}, {"mips32r5"}, {"mips32r6"},
 {"mips64"}, {"mips64r2"}, {"mips64r3"}, {"mips64r5"}, {"mips64r6"},
-{"octeon"}, {"octeon+"}, {"p5600"}};
+{"octeon"}, {"octeon+"},  {"p5600"},{"i6400"},{"i6500"}};
 
 bool MipsTargetInfo::isValidCPUName(StringRef Name) const {
   return llvm::is_contained(ValidCPUNames, Name);
diff --git a/clang/lib/Driver/ToolChains/Arch/Mips.cpp 
b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
index ca0745fc2b32d..9c817f238524c 100644
--- a/clang/lib/Driver/ToolChains/Arch/Mips.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
@@ -104,6 +104,8 @@ void mips::getMipsCPUAndABI(const ArgList &Args, const 
llvm::Triple &Triple,
   .Case("mips64r6", "n64")
   .Case("octeon", "n64")
   .Case("p5600", "o32")
+  .Case("i6400", "n64")
+  .Case("i6500", "n64")
   .Default("");
   }
 
@@ -514,5 +516,7 @@ bool mips::supportsIndirectJumpHazardBarrier(StringRef 
&CPU) {
   .Case("mips64r6", true)
   .Case("octeon", true)
   .Case("p5600", true)
+  .Case("i6400", true)
+  .Case("i6500", true)
   .Default(false);
 }
diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp 
b/clang/lib/Driver/ToolChains/Gnu.cpp
index f56eeda3cb5f6..68c288f516fba 100644
--- a/clang/lib/Driver/ToolChains/Gnu.cpp
+++ b/clang/lib/Driver/ToolChains/Gnu.cpp
@@ -1501,7 +1501,9 @@ bool clang::driver::findMIPSMultilibs(const Driver &D,
   CPUName == "mips64r5" || CPUName == "octeon" ||
   CPUName == "octeon+",
   "-march=mips64r2", Flags);
-  addMultilibFlag(CPUName == "mips64r6", "-march=mips64r6", Flags);
+  addMultilibFlag(CPUName == "mips64r6" || CPUName == "i6400" ||
+  CPUName == "i6500",
+  "-march=mips64r6", Flags);
   addMultilibFlag(isMicroMips(Args), "-mmicromips", Flags);
   addMultilibFlag(tools::mips::isUCLibc(Args), "-muclibc", Flags);
   addMultilibFlag(tools::mips::isNaN2008(D, Args, TargetTriple), "-mnan=2008",
diff --git a/clang/test/Driver/mips-abi.c b/clang/test/Driver/mips-abi.c
index 06570b50928a1..9a2180c516a61 100644
--- a/clang/test/Driver/mips-abi.c
+++ b/clang/test/Driver/mips-abi.c
@@ -121,6 +121,30 @@
 // MIPS-ARCH-P5600-N64: error: ABI 'n64' is not supported on CPU 'p5600'
 //
 // RUN: %clang --target=mips-linux-gnu -### -c %s \
+// RUN:-march=i6400 2>&1 \
+// RUN:   | FileCheck -check-prefix=MIPS-ARCH-I6400 %s
+// MIPS-ARCH-I6400: "-target-cpu" "i6400"
+// MIPS-ARCH-I6400: "-target-abi" "o32"
+//
+// RUN: %clang --target=mips-linux-gnu -### -c %s \
+// RUN:-march=i6400 -mabi=64 2>&1 \
+// RUN:   | FileCheck -check-prefix=MIPS-ARCH-I6400-N64 %s
+// MIPS-ARCH-I6400-N64: "-target-cpu" "i6400"
+// MIPS-ARCH-I6400-N64: "-target-abi" "n64"
+//
+// RUN: %clang --target=mips-linux-gnu -### -c %s \
+// RUN:-march=i6500 2>&1 \
+// RUN:   | FileCheck -check-prefix=MIPS-ARCH-I6500 %s
+// MIPS-ARCH-I6500: "-target-cpu" "i6500"
+// MIPS-ARCH-I6500: "-target-abi" "o32"
+//
+// RUN: %clang --target=mips-linux-gnu -### -c %s \
+// RUN:-march=i6500 -mabi=64 2>&1 \
+// RUN:   | FileCheck -check-prefix=MIPS-ARCH-I6500-N64 %s
+// MIPS-ARCH-I6500-N64: "-target

[clang] [llvm] [MIPS] Add MIPS i6400 and i6500 processors (PR #130587)

2025-03-12 Thread Mallikarjuna Gouda via cfe-commits 


@@ -238,13 +238,10 @@ def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
  "MipsSubtarget::CPU::P5600",
  "The P5600 Processor", [FeatureMips32r5]>;
 
+// I6500 is multicluster version of I6400. Both are based on same CPU.

mgoudar wrote:

updated the comments

https://github.com/llvm/llvm-project/pull/130587
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[clang] [llvm] Reland [MIPS] Define SubTargetFeature for i6500 cpu (#132907) (PR #133366)

2025-03-27 Thread Mallikarjuna Gouda via cfe-commits 

https://github.com/mgoudar created 
https://github.com/llvm/llvm-project/pull/133366

Relands #132907 with a fix in the testcase:
clang/test/CodeGen/Mips/subtarget-feature-test.c
enable this test for only mips64 target

PR #130587 defined same SubTargetFeature for CPUs i6400 and i6500 which 
resulted into following warning when -mcpu=i6500 was used:

+i6500' is not a recognized feature for this target (ignoring feature)

This PR fixes above issue by defining separate SubTargetFeature for i6500.

>From 1c4b804013f4fb3bb4ed6fa8323c64596fb01229 Mon Sep 17 00:00:00 2001
From: Mallikarjuna Gouda 
Date: Fri, 28 Mar 2025 10:27:02 +0530
Subject: [PATCH] Reland [MIPS] Define SubTargetFeature for i6500 cpu (#132907)

Relands #132907 with a fix in the testcase:
clang/test/CodeGen/Mips/subtarget-feature-test.c
enable this test for only mips64 target

PR #130587 defined same SubTargetFeature for CPUs i6400 and i6500 which
resulted into following warning when -mcpu=i6500 was used:

+i6500' is not a recognized feature for this target (ignoring feature)

This PR fixes above issue by defining separate SubTargetFeature for i6500.
---
 clang/test/CodeGen/Mips/subtarget-feature-test.c | 6 ++
 llvm/lib/Target/Mips/Mips.td | 8 ++--
 llvm/lib/Target/Mips/MipsSubtarget.h | 2 +-
 3 files changed, 13 insertions(+), 3 deletions(-)
 create mode 100644 clang/test/CodeGen/Mips/subtarget-feature-test.c

diff --git a/clang/test/CodeGen/Mips/subtarget-feature-test.c 
b/clang/test/CodeGen/Mips/subtarget-feature-test.c
new file mode 100644
index 0..4923e2d1fbfd4
--- /dev/null
+++ b/clang/test/CodeGen/Mips/subtarget-feature-test.c
@@ -0,0 +1,6 @@
+// REQUIRES: mips64-registered-target
+// RUN: %clang --target=mips64-linux-gnu -mcpu=i6400 -o %t -c %s 2>&1 | 
FileCheck --allow-empty %s
+// CHECK-NOT: {{.*}} is not a recognized feature for this target
+
+// RUN: %clang --target=mips64-linux-gnu -mcpu=i6500 -o %t -c %s 2>&1 | 
FileCheck --allow-empty %s
+// CHECK-NOT: {{.*}} is not a recognized feature for this target
diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td
index 9159d11fd486f..43a5ae8133d83 100644
--- a/llvm/lib/Target/Mips/Mips.td
+++ b/llvm/lib/Target/Mips/Mips.td
@@ -242,7 +242,11 @@ def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
 // same CPU architecture.
 def ImplI6400
 : SubtargetFeature<"i6400", "ProcImpl", "MipsSubtarget::CPU::I6400",
-   "MIPS I6400/I6500 Processors", [FeatureMips64r6]>;
+   "MIPS I6400 Processor", [FeatureMips64r6]>;
+
+def ImplI6500
+: SubtargetFeature<"i6500", "ProcImpl", "MipsSubtarget::CPU::I6500",
+   "MIPS I6500 Processor", [FeatureMips64r6]>;
 
 class Proc Features>
  : ProcessorModel;
@@ -268,7 +272,7 @@ def : Proc<"octeon", [FeatureMips64r2, FeatureCnMips]>;
 def : Proc<"octeon+", [FeatureMips64r2, FeatureCnMips, FeatureCnMipsP]>;
 def : ProcessorModel<"p5600", MipsP5600Model, [ImplP5600]>;
 def : ProcessorModel<"i6400", NoSchedModel, [ImplI6400]>;
-def : ProcessorModel<"i6500", NoSchedModel, [ImplI6400]>;
+def : ProcessorModel<"i6500", NoSchedModel, [ImplI6500]>;
 
 def MipsAsmParser : AsmParser {
   let ShouldEmitMatchRegisterName = 0;
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.h 
b/llvm/lib/Target/Mips/MipsSubtarget.h
index 0c75597d3decf..15127b11d5cdd 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.h
+++ b/llvm/lib/Target/Mips/MipsSubtarget.h
@@ -43,7 +43,7 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
 Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
   };
 
-  enum class CPU { P5600, I6400 };
+  enum class CPU { P5600, I6400, I6500 };
 
   // Used to avoid printing dsp warnings multiple times.
   static bool DspWarningPrinted;

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[clang] [llvm] [MIPS] Add MIPS i6400 and i6500 processors (PR #130587)

2025-04-04 Thread Mallikarjuna Gouda via cfe-commits 

mgoudar wrote:

> Lets wait another day or two, since someone may have additional comments. 
> Thanks @mgoudar!

sure. thank you.

https://github.com/llvm/llvm-project/pull/130587
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[clang] [llvm] [MIPS] Add FeatureMSA to i6400 and i6500 cores (PR #134985)

2025-05-07 Thread Mallikarjuna Gouda via cfe-commits 


@@ -0,0 +1,724 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=mips64 -mcpu=i6500 < %s | FileCheck %s --check-prefixes=ALL
+; RUN: llc -mtriple=mips64 -mcpu=i6400 < %s | FileCheck %s --check-prefixes=ALL

mgoudar wrote:

used test/CodeGen/Mips/msa/arithmetic.ll as per your suggestion and added RUN 
command for i6400/i6500 msa

https://github.com/llvm/llvm-project/pull/134985
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[clang] [llvm] [MIPS] Add FeatureMSA to i6400 and i6500 cores (PR #134985)

2025-05-07 Thread Mallikarjuna Gouda via cfe-commits 




mgoudar wrote:

I added RUN commands for i6500/i6400 msa test to the existing test 
test/CodeGen/Mips/msa/arithmetic.ll and deleted new test that was added in the 
prev commit.

https://github.com/llvm/llvm-project/pull/134985
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[clang] [llvm] [MIPS] Add FeatureMSA to i6400 and i6500 cores (PR #134985)

2025-05-07 Thread Mallikarjuna Gouda via cfe-commits 

https://github.com/mgoudar edited 
https://github.com/llvm/llvm-project/pull/134985
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