https://github.com/mgoudar updated
https://github.com/llvm/llvm-project/pull/134985
>From 36a78bb9fe38781fa8ea126aeae5b7ed48140651 Mon Sep 17 00:00:00 2001
From: Mallikarjuna Gouda <mgo...@mips.com>
Date: Tue, 1 Apr 2025 12:35:27 +0530
Subject: [PATCH 1/5] [MIPS] Add FeatureMSA to i6400 and i6500 cores
i6400 and i6500 cores support MIPS SIMD Architecture (MSA) instructions
---
llvm/lib/Target/Mips/Mips.td | 4 +-
llvm/test/CodeGen/Mips/msa/i6500.ll | 69 +++++++++++++++++++++++++++++
2 files changed, 71 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/Mips/msa/i6500.ll
diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td
index 43a5ae8133d83..ca3df1fd94144 100644
--- a/llvm/lib/Target/Mips/Mips.td
+++ b/llvm/lib/Target/Mips/Mips.td
@@ -242,11 +242,11 @@ def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
// same CPU architecture.
def ImplI6400
: SubtargetFeature<"i6400", "ProcImpl", "MipsSubtarget::CPU::I6400",
- "MIPS I6400 Processor", [FeatureMips64r6]>;
+ "MIPS I6400 Processor", [FeatureMips64r6, FeatureMSA]>;
def ImplI6500
: SubtargetFeature<"i6500", "ProcImpl", "MipsSubtarget::CPU::I6500",
- "MIPS I6500 Processor", [FeatureMips64r6]>;
+ "MIPS I6500 Processor", [FeatureMips64r6, FeatureMSA]>;
class Proc<string Name, list<SubtargetFeature> Features>
: ProcessorModel<Name, MipsGenericModel, Features>;
diff --git a/llvm/test/CodeGen/Mips/msa/i6500.ll
b/llvm/test/CodeGen/Mips/msa/i6500.ll
new file mode 100644
index 0000000000000..b8404ab72fea3
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/msa/i6500.ll
@@ -0,0 +1,69 @@
+; Test the MSA intrinsics that are encoded with the SPECIAL instruction format.
+
+; RUN: llc -mtriple=mips-elf -mcpu=i6500 < %s | \
+; RUN: FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mips64-elf -mcpu=i6500 < %s | \
+; RUN: FileCheck %s --check-prefix=MIPS64
+; RUN: llc -mtriple=mips-elf -mcpu=i6500 < %s | \
+; RUN: FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mips64-elf -mcpu=i6500 < %s | \
+; RUN: FileCheck %s --check-prefix=MIPS64
+; RUN: llc -mtriple=mips64-elf -mcpu=i6500 -mattr=-msa < %s | \
+; RUN: FileCheck %s --check-prefix=NO-DSLA
+; RUN: llc -mtriple=mips-elf -mcpu=i6400 < %s | \
+; RUN: FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mips64-elf -mcpu=i6400 < %s | \
+; RUN: FileCheck %s --check-prefix=MIPS64
+; RUN: llc -mtriple=mips-elf -mcpu=i6400 < %s | \
+; RUN: FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mips64-elf -mcpu=i6400 < %s | \
+; RUN: FileCheck %s --check-prefix=MIPS64
+; RUN: llc -mtriple=mips64-elf -mcpu=i6400 -mattr=-msa < %s | \
+; RUN: FileCheck %s --check-prefix=NO-DSLA
+
+define i32 @llvm_mips_lsa_test(i32 %a, i32 %b) nounwind {
+entry:
+ %0 = tail call i32 @llvm.mips.lsa(i32 %a, i32 %b, i32 2)
+ ret i32 %0
+}
+
+declare i32 @llvm.mips.lsa(i32, i32, i32) nounwind
+
+; MIPS32: llvm_mips_lsa_test:
+; MIPS32: lsa {{\$[0-9]+}}, $5, $4, 2
+; MIPS32: .size llvm_mips_lsa_test
+
+define i32 @lsa_test(i32 %a, i32 %b) nounwind {
+entry:
+ %0 = shl i32 %b, 2
+ %1 = add i32 %a, %0
+ ret i32 %1
+}
+
+; MIPS32: lsa_test:
+; MIPS32: lsa {{\$[0-9]+}}, $5, $4, 2
+; MIPS32: .size lsa_test
+
+define i64 @llvm_mips_dlsa_test(i64 %a, i64 %b) nounwind {
+entry:
+ %0 = tail call i64 @llvm.mips.dlsa(i64 %a, i64 %b, i32 2)
+ ret i64 %0
+}
+
+declare i64 @llvm.mips.dlsa(i64, i64, i32) nounwind
+
+; MIPS64: llvm_mips_dlsa_test:
+; MIPS64: dlsa {{\$[0-9]+}}, $5, $4, 2
+; MIPS64: .size llvm_mips_dlsa_test
+; NO-DSLA-NOT: dlsa {{\$[0-9]+}}, $5, $4, 2
+define i64 @dlsa_test(i64 %a, i64 %b) nounwind {
+entry:
+ %0 = shl i64 %b, 2
+ %1 = add i64 %a, %0
+ ret i64 %1
+}
+
+; MIPS64: dlsa_test:
+; MIPS64: dlsa {{\$[0-9]+}}, $5, $4, 2
+; MIPS64: .size dlsa_test
+; NO-DSLA-NOT: dlsa {{\$[0-9]+}}, $5, $4, 2
>From 4ed92eba68d556a0b2badbde1a39e35349a38d98 Mon Sep 17 00:00:00 2001
From: Mallikarjuna Gouda <mgo...@mips.com>
Date: Thu, 10 Apr 2025 10:47:30 +0530
Subject: [PATCH 2/5] Update test case with update_llc_test_checks.py
---
llvm/test/CodeGen/Mips/msa/i6500.ll | 105 ++++++++++++++++------------
1 file changed, 62 insertions(+), 43 deletions(-)
diff --git a/llvm/test/CodeGen/Mips/msa/i6500.ll
b/llvm/test/CodeGen/Mips/msa/i6500.ll
index b8404ab72fea3..779dbf1b1c165 100644
--- a/llvm/test/CodeGen/Mips/msa/i6500.ll
+++ b/llvm/test/CodeGen/Mips/msa/i6500.ll
@@ -1,69 +1,88 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
; Test the MSA intrinsics that are encoded with the SPECIAL instruction format.
; RUN: llc -mtriple=mips-elf -mcpu=i6500 < %s | \
; RUN: FileCheck %s --check-prefix=MIPS32
-; RUN: llc -mtriple=mips64-elf -mcpu=i6500 < %s | \
-; RUN: FileCheck %s --check-prefix=MIPS64
-; RUN: llc -mtriple=mips-elf -mcpu=i6500 < %s | \
-; RUN: FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mips-elf -mcpu=i6500 -mattr=-msa < %s | \
+; RUN: FileCheck %s --check-prefix=MIPS32-NO-LSA
+
; RUN: llc -mtriple=mips64-elf -mcpu=i6500 < %s | \
; RUN: FileCheck %s --check-prefix=MIPS64
; RUN: llc -mtriple=mips64-elf -mcpu=i6500 -mattr=-msa < %s | \
-; RUN: FileCheck %s --check-prefix=NO-DSLA
-; RUN: llc -mtriple=mips-elf -mcpu=i6400 < %s | \
-; RUN: FileCheck %s --check-prefix=MIPS32
-; RUN: llc -mtriple=mips64-elf -mcpu=i6400 < %s | \
-; RUN: FileCheck %s --check-prefix=MIPS64
+; RUN: FileCheck %s --check-prefix=MIPS64-NO-DLSA
+
; RUN: llc -mtriple=mips-elf -mcpu=i6400 < %s | \
; RUN: FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mips-elf -mcpu=i6400 -mattr=-msa < %s | \
+; RUN: FileCheck %s --check-prefix=MIPS32-NO-LSA
+
; RUN: llc -mtriple=mips64-elf -mcpu=i6400 < %s | \
; RUN: FileCheck %s --check-prefix=MIPS64
; RUN: llc -mtriple=mips64-elf -mcpu=i6400 -mattr=-msa < %s | \
-; RUN: FileCheck %s --check-prefix=NO-DSLA
+; RUN: FileCheck %s --check-prefix=MIPS64-NO-DLSA
define i32 @llvm_mips_lsa_test(i32 %a, i32 %b) nounwind {
+; MIPS32-LABEL: llvm_mips_lsa_test:
+; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: lsa $2, $5, $4, 2
+;
+; MIPS32-NO-LSA-LABEL: llvm_mips_lsa_test:
+; MIPS32-NO-LSA: # %bb.0: # %entry
+; MIPS32-NO-LSA-NEXT: sll $1, $5, 2
+; MIPS32-NO-LSA-NEXT: jr $ra
+; MIPS32-NO-LSA-NEXT: addu $2, $4, $1
+;
+; MIPS64-LABEL: llvm_mips_lsa_test:
+; MIPS64: # %bb.0: # %entry
+; MIPS64-NEXT: sll $1, $4, 0
+; MIPS64-NEXT: sll $2, $5, 0
+; MIPS64-NEXT: jr $ra
+; MIPS64-NEXT: lsa $2, $2, $1, 2
+;
+; MIPS64-NO-DLSA-LABEL: llvm_mips_lsa_test:
+; MIPS64-NO-DLSA: # %bb.0: # %entry
+; MIPS64-NO-DLSA-NEXT: sll $1, $4, 0
+; MIPS64-NO-DLSA-NEXT: sll $2, $5, 0
+; MIPS64-NO-DLSA-NEXT: sll $2, $2, 2
+; MIPS64-NO-DLSA-NEXT: jr $ra
+; MIPS64-NO-DLSA-NEXT: addu $2, $1, $2
entry:
%0 = tail call i32 @llvm.mips.lsa(i32 %a, i32 %b, i32 2)
ret i32 %0
}
-
declare i32 @llvm.mips.lsa(i32, i32, i32) nounwind
-; MIPS32: llvm_mips_lsa_test:
-; MIPS32: lsa {{\$[0-9]+}}, $5, $4, 2
-; MIPS32: .size llvm_mips_lsa_test
-
-define i32 @lsa_test(i32 %a, i32 %b) nounwind {
-entry:
- %0 = shl i32 %b, 2
- %1 = add i32 %a, %0
- ret i32 %1
-}
-
-; MIPS32: lsa_test:
-; MIPS32: lsa {{\$[0-9]+}}, $5, $4, 2
-; MIPS32: .size lsa_test
-
define i64 @llvm_mips_dlsa_test(i64 %a, i64 %b) nounwind {
+; MIPS32-LABEL: llvm_mips_dlsa_test:
+; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: dmfc1 $1, $f14
+; MIPS32-NEXT: dmfc1 $2, $f12
+; MIPS32-NEXT: dlsa $1, $1, $2, 2
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: sd $1, 0($4)
+;
+; MIPS32-NO-LSA-LABEL: llvm_mips_dlsa_test:
+; MIPS32-NO-LSA: # %bb.0: # %entry
+; MIPS32-NO-LSA-NEXT: dmfc1 $1, $f14
+; MIPS32-NO-LSA-NEXT: dmfc1 $2, $f12
+; MIPS32-NO-LSA-NEXT: dsll $1, $1, 2
+; MIPS32-NO-LSA-NEXT: daddu $1, $2, $1
+; MIPS32-NO-LSA-NEXT: jr $ra
+; MIPS32-NO-LSA-NEXT: sd $1, 0($4)
+;
+; MIPS64-LABEL: llvm_mips_dlsa_test:
+; MIPS64: # %bb.0: # %entry
+; MIPS64-NEXT: jr $ra
+; MIPS64-NEXT: dlsa $2, $5, $4, 2
+;
+; MIPS64-NO-DLSA-LABEL: llvm_mips_dlsa_test:
+; MIPS64-NO-DLSA: # %bb.0: # %entry
+; MIPS64-NO-DLSA-NEXT: dsll $1, $5, 2
+; MIPS64-NO-DLSA-NEXT: jr $ra
+; MIPS64-NO-DLSA-NEXT: daddu $2, $4, $1
entry:
%0 = tail call i64 @llvm.mips.dlsa(i64 %a, i64 %b, i32 2)
ret i64 %0
}
-
declare i64 @llvm.mips.dlsa(i64, i64, i32) nounwind
-
-; MIPS64: llvm_mips_dlsa_test:
-; MIPS64: dlsa {{\$[0-9]+}}, $5, $4, 2
-; MIPS64: .size llvm_mips_dlsa_test
-; NO-DSLA-NOT: dlsa {{\$[0-9]+}}, $5, $4, 2
-define i64 @dlsa_test(i64 %a, i64 %b) nounwind {
-entry:
- %0 = shl i64 %b, 2
- %1 = add i64 %a, %0
- ret i64 %1
-}
-
-; MIPS64: dlsa_test:
-; MIPS64: dlsa {{\$[0-9]+}}, $5, $4, 2
-; MIPS64: .size dlsa_test
-; NO-DSLA-NOT: dlsa {{\$[0-9]+}}, $5, $4, 2
>From 8f2d8503ec62332fb3056a1d30f647d5b395d4f4 Mon Sep 17 00:00:00 2001
From: Mallikarjuna Gouda <mgo...@mips.com>
Date: Thu, 17 Apr 2025 01:58:12 -0700
Subject: [PATCH 3/5] Add test case to test MSA feature for i6400 and i6500
MIPS cpus
Also remove codegen test i6500.ll
---
clang/test/Driver/mips-cpus.c | 9 +++
llvm/test/CodeGen/Mips/msa/i6500.ll | 88 -----------------------------
2 files changed, 9 insertions(+), 88 deletions(-)
create mode 100644 clang/test/Driver/mips-cpus.c
delete mode 100644 llvm/test/CodeGen/Mips/msa/i6500.ll
diff --git a/clang/test/Driver/mips-cpus.c b/clang/test/Driver/mips-cpus.c
new file mode 100644
index 0000000000000..effb5ef60166a
--- /dev/null
+++ b/clang/test/Driver/mips-cpus.c
@@ -0,0 +1,9 @@
+// Check target CPUs are correctly passed.
+
+// RUN: %clang --target=mips64 -### -c %s 2>&1 -mcpu=i6400 -mmsa | FileCheck
-check-prefix=MCPU-I6400 %s
+// MCPU-I6400: "-target-cpu" "i6400"
+// MCPU-I6400-SAME: "-target-feature" "+msa"
+
+// RUN: %clang --target=mips64 -### -c %s 2>&1 -mcpu=i6500 -mmsa | FileCheck
-check-prefix=MCPU-I6500 %s
+// MCPU-I6500: "-target-cpu" "i6500"
+// MCPU-I6500-SAME: "-target-feature" "+msa"
diff --git a/llvm/test/CodeGen/Mips/msa/i6500.ll
b/llvm/test/CodeGen/Mips/msa/i6500.ll
deleted file mode 100644
index 779dbf1b1c165..0000000000000
--- a/llvm/test/CodeGen/Mips/msa/i6500.ll
+++ /dev/null
@@ -1,88 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
-; Test the MSA intrinsics that are encoded with the SPECIAL instruction format.
-
-; RUN: llc -mtriple=mips-elf -mcpu=i6500 < %s | \
-; RUN: FileCheck %s --check-prefix=MIPS32
-; RUN: llc -mtriple=mips-elf -mcpu=i6500 -mattr=-msa < %s | \
-; RUN: FileCheck %s --check-prefix=MIPS32-NO-LSA
-
-; RUN: llc -mtriple=mips64-elf -mcpu=i6500 < %s | \
-; RUN: FileCheck %s --check-prefix=MIPS64
-; RUN: llc -mtriple=mips64-elf -mcpu=i6500 -mattr=-msa < %s | \
-; RUN: FileCheck %s --check-prefix=MIPS64-NO-DLSA
-
-; RUN: llc -mtriple=mips-elf -mcpu=i6400 < %s | \
-; RUN: FileCheck %s --check-prefix=MIPS32
-; RUN: llc -mtriple=mips-elf -mcpu=i6400 -mattr=-msa < %s | \
-; RUN: FileCheck %s --check-prefix=MIPS32-NO-LSA
-
-; RUN: llc -mtriple=mips64-elf -mcpu=i6400 < %s | \
-; RUN: FileCheck %s --check-prefix=MIPS64
-; RUN: llc -mtriple=mips64-elf -mcpu=i6400 -mattr=-msa < %s | \
-; RUN: FileCheck %s --check-prefix=MIPS64-NO-DLSA
-
-define i32 @llvm_mips_lsa_test(i32 %a, i32 %b) nounwind {
-; MIPS32-LABEL: llvm_mips_lsa_test:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: lsa $2, $5, $4, 2
-;
-; MIPS32-NO-LSA-LABEL: llvm_mips_lsa_test:
-; MIPS32-NO-LSA: # %bb.0: # %entry
-; MIPS32-NO-LSA-NEXT: sll $1, $5, 2
-; MIPS32-NO-LSA-NEXT: jr $ra
-; MIPS32-NO-LSA-NEXT: addu $2, $4, $1
-;
-; MIPS64-LABEL: llvm_mips_lsa_test:
-; MIPS64: # %bb.0: # %entry
-; MIPS64-NEXT: sll $1, $4, 0
-; MIPS64-NEXT: sll $2, $5, 0
-; MIPS64-NEXT: jr $ra
-; MIPS64-NEXT: lsa $2, $2, $1, 2
-;
-; MIPS64-NO-DLSA-LABEL: llvm_mips_lsa_test:
-; MIPS64-NO-DLSA: # %bb.0: # %entry
-; MIPS64-NO-DLSA-NEXT: sll $1, $4, 0
-; MIPS64-NO-DLSA-NEXT: sll $2, $5, 0
-; MIPS64-NO-DLSA-NEXT: sll $2, $2, 2
-; MIPS64-NO-DLSA-NEXT: jr $ra
-; MIPS64-NO-DLSA-NEXT: addu $2, $1, $2
-entry:
- %0 = tail call i32 @llvm.mips.lsa(i32 %a, i32 %b, i32 2)
- ret i32 %0
-}
-declare i32 @llvm.mips.lsa(i32, i32, i32) nounwind
-
-define i64 @llvm_mips_dlsa_test(i64 %a, i64 %b) nounwind {
-; MIPS32-LABEL: llvm_mips_dlsa_test:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: dmfc1 $1, $f14
-; MIPS32-NEXT: dmfc1 $2, $f12
-; MIPS32-NEXT: dlsa $1, $1, $2, 2
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: sd $1, 0($4)
-;
-; MIPS32-NO-LSA-LABEL: llvm_mips_dlsa_test:
-; MIPS32-NO-LSA: # %bb.0: # %entry
-; MIPS32-NO-LSA-NEXT: dmfc1 $1, $f14
-; MIPS32-NO-LSA-NEXT: dmfc1 $2, $f12
-; MIPS32-NO-LSA-NEXT: dsll $1, $1, 2
-; MIPS32-NO-LSA-NEXT: daddu $1, $2, $1
-; MIPS32-NO-LSA-NEXT: jr $ra
-; MIPS32-NO-LSA-NEXT: sd $1, 0($4)
-;
-; MIPS64-LABEL: llvm_mips_dlsa_test:
-; MIPS64: # %bb.0: # %entry
-; MIPS64-NEXT: jr $ra
-; MIPS64-NEXT: dlsa $2, $5, $4, 2
-;
-; MIPS64-NO-DLSA-LABEL: llvm_mips_dlsa_test:
-; MIPS64-NO-DLSA: # %bb.0: # %entry
-; MIPS64-NO-DLSA-NEXT: dsll $1, $5, 2
-; MIPS64-NO-DLSA-NEXT: jr $ra
-; MIPS64-NO-DLSA-NEXT: daddu $2, $4, $1
-entry:
- %0 = tail call i64 @llvm.mips.dlsa(i64 %a, i64 %b, i32 2)
- ret i64 %0
-}
-declare i64 @llvm.mips.dlsa(i64, i64, i32) nounwind
>From f1b35e8ff093acaa3e41c5c9cba23b2b5346c19e Mon Sep 17 00:00:00 2001
From: Mallikarjuna Gouda <mgo...@mips.com>
Date: Wed, 23 Apr 2025 01:40:16 -0700
Subject: [PATCH 4/5] Enable MSA feature by default for MIPS cpus i6400 and
i6500
MIPS cpus support MSA by default. So enable this feature
for cpus i6400 and i6500.
Also test msa feature in mips-cpus.c driver test case
---
clang/lib/Driver/ToolChains/Arch/Mips.cpp | 6 ++++++
clang/test/Driver/mips-cpus.c | 8 ++++----
2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/clang/lib/Driver/ToolChains/Arch/Mips.cpp
b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
index 9c817f238524c..960ee7fd179e1 100644
--- a/clang/lib/Driver/ToolChains/Arch/Mips.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
@@ -255,6 +255,12 @@ void mips::getMIPSTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
D.Diag(diag::err_drv_unsupported_noabicalls_pic);
}
+ if (CPUName == "i6500" || CPUName == "i6400") {
+ // MIPS cpu i6400 and i6500 support MSA (Mips SIMD Architecture)
+ // by default.
+ Features.push_back("+msa");
+ }
+
if (!UseAbiCalls)
Features.push_back("+noabicalls");
else
diff --git a/clang/test/Driver/mips-cpus.c b/clang/test/Driver/mips-cpus.c
index effb5ef60166a..2e988e58f04fb 100644
--- a/clang/test/Driver/mips-cpus.c
+++ b/clang/test/Driver/mips-cpus.c
@@ -1,9 +1,9 @@
// Check target CPUs are correctly passed.
-// RUN: %clang --target=mips64 -### -c %s 2>&1 -mcpu=i6400 -mmsa | FileCheck
-check-prefix=MCPU-I6400 %s
+// RUN: %clang --target=mips64 -### -c %s 2>&1 -mcpu=i6400 | FileCheck
-check-prefix=MCPU-I6400 %s
// MCPU-I6400: "-target-cpu" "i6400"
-// MCPU-I6400-SAME: "-target-feature" "+msa"
+// MCPU-I6400: "-target-feature" "+msa" "-target-feature" "-noabicalls"
-// RUN: %clang --target=mips64 -### -c %s 2>&1 -mcpu=i6500 -mmsa | FileCheck
-check-prefix=MCPU-I6500 %s
+// RUN: %clang --target=mips64 -### -c %s 2>&1 -mcpu=i6500 | FileCheck
-check-prefix=MCPU-I6500 %s
// MCPU-I6500: "-target-cpu" "i6500"
-// MCPU-I6500-SAME: "-target-feature" "+msa"
+// MCPU-I6500: "-target-feature" "+msa" "-target-feature" "-noabicalls"
>From dad133765b97bc0a1de53e0817ec4af5278202c1 Mon Sep 17 00:00:00 2001
From: Mallikarjuna Gouda <mgo...@mips.com>
Date: Wed, 23 Apr 2025 01:54:21 -0700
Subject: [PATCH 5/5] Revert "Enable MSA feature by default for MIPS cpus i6400
and i6500"
This reverts commit f1b35e8ff093acaa3e41c5c9cba23b2b5346c19e.
---
clang/lib/Driver/ToolChains/Arch/Mips.cpp | 6 ------
clang/test/Driver/mips-cpus.c | 8 ++++----
2 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/clang/lib/Driver/ToolChains/Arch/Mips.cpp
b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
index 960ee7fd179e1..9c817f238524c 100644
--- a/clang/lib/Driver/ToolChains/Arch/Mips.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
@@ -255,12 +255,6 @@ void mips::getMIPSTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
D.Diag(diag::err_drv_unsupported_noabicalls_pic);
}
- if (CPUName == "i6500" || CPUName == "i6400") {
- // MIPS cpu i6400 and i6500 support MSA (Mips SIMD Architecture)
- // by default.
- Features.push_back("+msa");
- }
-
if (!UseAbiCalls)
Features.push_back("+noabicalls");
else
diff --git a/clang/test/Driver/mips-cpus.c b/clang/test/Driver/mips-cpus.c
index 2e988e58f04fb..effb5ef60166a 100644
--- a/clang/test/Driver/mips-cpus.c
+++ b/clang/test/Driver/mips-cpus.c
@@ -1,9 +1,9 @@
// Check target CPUs are correctly passed.
-// RUN: %clang --target=mips64 -### -c %s 2>&1 -mcpu=i6400 | FileCheck
-check-prefix=MCPU-I6400 %s
+// RUN: %clang --target=mips64 -### -c %s 2>&1 -mcpu=i6400 -mmsa | FileCheck
-check-prefix=MCPU-I6400 %s
// MCPU-I6400: "-target-cpu" "i6400"
-// MCPU-I6400: "-target-feature" "+msa" "-target-feature" "-noabicalls"
+// MCPU-I6400-SAME: "-target-feature" "+msa"
-// RUN: %clang --target=mips64 -### -c %s 2>&1 -mcpu=i6500 | FileCheck
-check-prefix=MCPU-I6500 %s
+// RUN: %clang --target=mips64 -### -c %s 2>&1 -mcpu=i6500 -mmsa | FileCheck
-check-prefix=MCPU-I6500 %s
// MCPU-I6500: "-target-cpu" "i6500"
-// MCPU-I6500: "-target-feature" "+msa" "-target-feature" "-noabicalls"
+// MCPU-I6500-SAME: "-target-feature" "+msa"
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