[llvm] [clang] [AIX] Enable tests relating to 64-bit XCOFF object files (PR #71814)
@@ -332,43 +332,6 @@ def calculate_arch_features(arch_string):
config.available_features.add("llvm-driver")
-def exclude_unsupported_files_for_aix(dirname):
-for filename in os.listdir(dirname):
-source_path = os.path.join(dirname, filename)
-if os.path.isdir(source_path):
-continue
-f = open(source_path, "r", encoding="ISO-8859-1")
-try:
-data = f.read()
-# 64-bit object files are not supported on AIX, so exclude the
tests.
-if (
-any(
-option in data
-for option in (
-"-emit-obj",
-"-fmodule-format=obj",
-"-fintegrated-as",
-)
-)
-and "64" in config.target_triple
-):
-config.excludes += [filename]
-finally:
-f.close()
-
-
-if "aix" in config.target_triple:
-for directory in (
-"/CodeGenCXX",
-"/Misc",
-"/Modules",
-"/PCH",
-"/Driver",
-"/ASTMerge/anonymous-fields",
-"/ASTMerge/injected-class-name-decl",
chenzheng1030 wrote:
Just to confirm, so this removal does not have any impact on clang tests? I
think some PCH/Modules cases would have some expected failures in AIX object
mode, like `Objective-C support is unimplemented`?
https://github.com/llvm/llvm-project/pull/71814
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[clang] [llvm] [AIX] Enable tests relating to 64-bit XCOFF object files (PR #71814)
https://github.com/chenzheng1030 edited https://github.com/llvm/llvm-project/pull/71814 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [AIX] Enable tests relating to 64-bit XCOFF object files (PR #71814)
@@ -332,43 +332,6 @@ def calculate_arch_features(arch_string):
config.available_features.add("llvm-driver")
-def exclude_unsupported_files_for_aix(dirname):
-for filename in os.listdir(dirname):
-source_path = os.path.join(dirname, filename)
-if os.path.isdir(source_path):
-continue
-f = open(source_path, "r", encoding="ISO-8859-1")
-try:
-data = f.read()
-# 64-bit object files are not supported on AIX, so exclude the
tests.
-if (
-any(
-option in data
-for option in (
-"-emit-obj",
-"-fmodule-format=obj",
-"-fintegrated-as",
-)
-)
-and "64" in config.target_triple
-):
-config.excludes += [filename]
-finally:
-f.close()
-
-
-if "aix" in config.target_triple:
-for directory in (
-"/CodeGenCXX",
-"/Misc",
-"/Modules",
-"/PCH",
-"/Driver",
-"/ASTMerge/anonymous-fields",
-"/ASTMerge/injected-class-name-decl",
chenzheng1030 wrote:
OK
https://github.com/llvm/llvm-project/pull/71814
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[clang] [llvm] [AIX] Enable tests relating to 64-bit XCOFF object files (PR #71814)
https://github.com/chenzheng1030 approved this pull request. LGTM. Thanks! https://github.com/llvm/llvm-project/pull/71814 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [PowerPC] Support local-dynamic TLS relocation on AIX (PR #66316)
@@ -3412,13 +3416,23 @@ SDValue
PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TLSReg, VariableOffset);
}
- // Only Local-Exec, Initial-Exec and General-Dynamic TLS models are currently
- // supported models. If Local- or Initial-exec are not possible or specified,
- // all GlobalTLSAddress nodes are lowered using the general-dynamic model.
- // We need to generate two TOC entries, one for the variable offset, one for
- // the region handle. The global address for the TOC entry of the region
- // handle is created with the MO_TLSGDM_FLAG flag and the global address
- // for the TOC entry of the variable offset is created with MO_TLSGD_FLAG.
+ if (Model == TLSModel::LocalDynamic) {
+// For local-dynamic on AIX, we need to generate two TOC entries, one for
+// the variable offset, the other for the module handle. The module handle
+// is encapsulated inside the TLSLD_AIX pseudo node, and will be expanded
by
+// PPCTLSDynamicCall.
+SDValue VariableOffsetTGA =
+DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TLSLD_FLAG);
+SDValue VariableOffset = getTOCEntry(DAG, dl, VariableOffsetTGA);
chenzheng1030 wrote:
4b932d84f48e0f3f42c769a5ca7ce6623ab62f2e is committed to redesign the target
flags of machine operand on PPC. Now we should be able to add new flags.
https://github.com/llvm/llvm-project/pull/66316
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[clang-tools-extra] [flang] [compiler-rt] [llvm] [clang] [PowerPC][CodeGen] Exploit STMW and LMW in 32-bit big-endian mode. (PR #74415)
@@ -2399,6 +2405,29 @@ bool PPCFrameLowering::assignCalleeSavedSpillSlots(
return AllSpilledToReg;
}
+static void findContinuousLoadStore(ArrayRef CSI,
+Register &MergeFrom) {
+ unsigned I = 1, E = CSI.size(), BeginI = 0;
+ for (; I < E; ++I) {
+// Find continuous store/load.
+int RegDiff = CSI[I].getReg() - CSI[I - 1].getReg();
+int FrameIdxDiff = CSI[I - 1].getFrameIdx() - CSI[I].getFrameIdx();
+Register BeginReg = CSI[BeginI].getReg();
+if (BeginReg < PPC::R0 || BeginReg > PPC::R31 ||
+CSI[BeginI].isSpilledToReg() || RegDiff != 1 || FrameIdxDiff != 1)
+ BeginI = I;
+if (CSI[I].getReg() == PPC::R31)
+ break;
+ }
+
+ if (I == E || CSI[BeginI].getReg() >= PPC::R31)
+return;
+
+ // Record the first reg that STMW/LMW are going to merge since STMW/LMW save
+ // from rN to r31.
+ MergeFrom = CSI[BeginI].getReg();
chenzheng1030 wrote:
This is unnecessary complicating. LMW/STMW only applies for AIX 32-bit. For
AIX, we just need to find the first GPR(assume the CSI is sorted on ascending
ordering), that would be the MergeFrom. On AIX, CSRs always contain the lowest
GPR till R31.
https://github.com/llvm/llvm-project/pull/74415
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[clang-tools-extra] [clang] [llvm] [compiler-rt] [flang] [PowerPC][CodeGen] Exploit STMW and LMW in 32-bit big-endian mode. (PR #74415)
@@ -0,0 +1,138 @@
+; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -verify-machineinstrs \
+; RUN: -mcpu=pwr4 -mattr=-altivec --ppc-enable-load-store-multiple < %s \
+; RUN: | FileCheck %s
+
+; CHECK: # %bb.0:# %entry
+; CHECK-NEXT: mflr 0
+; CHECK-NEXT: stwu 1, -128(1)
+; CHECK-NEXT: cmpwi 5, 0
+; CHECK-NEXT: stw 0, 136(1)
+; CHECK-NEXT: stmw 16, 64(1) # 4-byte Folded Spill
+; CHECK-NEXT: ble 0, L..BB0_11
+
+; CHECK: L..BB0_12: # %for.cond.cleanup
+; CHECK-NEXT: lwz 3, L..C0(2) # @a
+; CHECK-NEXT: lwz 4, L..C1(2) # @b
+; CHECK-NEXT: lwz 5, L..C4(2) # @c
+; CHECK-NEXT: lwz 6, L..C7(2) # @d
+; CHECK-NEXT: lwz 7, L..C6(2) # @e
+; CHECK-NEXT: lmw 16, 64(1) # 4-byte Folded Reload
+; CHECK-NEXT: lwz 3, 0(3)
+; CHECK-NEXT: lwz 4, 0(4)
+; CHECK-NEXT: add 3, 3, 28
+; CHECK-NEXT: lwz 5, 0(5)
+; CHECK-NEXT: add 3, 3, 4
+; CHECK-NEXT: lwz 6, 0(6)
+; CHECK-NEXT: add 3, 3, 5
+; CHECK-NEXT: lwz 4, 0(7)
+; CHECK-NEXT: add 3, 3, 6
+; CHECK-NEXT: add 3, 3, 4
+; CHECK-NEXT: lwz 31, 124(1) # 4-byte Folded Reload
+; CHECK-NEXT: addi 1, 1, 128
+; CHECK-NEXT: lwz 0, 8(1)
+; CHECK-NEXT: mtlr 0
+; CHECK-NEXT: bl
+
+@a = external local_unnamed_addr global i32, align 4
chenzheng1030 wrote:
case is too complicated. Please use below one
```
define dso_local void @test_simple() #0 {
entry:
call void asm sideeffect "nop", "~{r13}"()
ret void
}
```
https://github.com/llvm/llvm-project/pull/74415
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[clang-tools-extra] [clang] [llvm] [compiler-rt] [flang] [PowerPC][CodeGen] Exploit STMW and LMW in 32-bit big-endian mode. (PR #74415)
https://github.com/chenzheng1030 edited https://github.com/llvm/llvm-project/pull/74415 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang-tools-extra] [compiler-rt] [flang] [clang] [PowerPC][CodeGen] Exploit STMW and LMW in 32-bit big-endian mode. (PR #74415)
@@ -40,6 +40,12 @@ EnablePEVectorSpills("ppc-enable-pe-vector-spills",
cl::desc("Enable spills in prologue to vector
registers."),
cl::init(false), cl::Hidden);
+static cl::opt
+EnableLoadStoreMultiple("ppc-enable-load-store-multiple",
+cl::desc("Enable load/store multiple (only "
+ "support in 32-bit big-endian mode)."),
chenzheng1030 wrote:
Instead of 32-bit big-endian, maybe it is better to limit this under AIX-32 bit.
https://github.com/llvm/llvm-project/pull/74415
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[clang] [PowerPC] Support mcmodel=large for AIX (PR #70652)
@@ -5723,7 +5723,7 @@ void Clang::ConstructJob(Compilation &C, const JobAction
&JA,
if (Arg *A = Args.getLastArg(options::OPT_mcmodel_EQ)) {
StringRef CM = A->getValue();
bool Ok = false;
-if (Triple.isOSAIX() && CM == "medium") {
+if (Triple.isOSAIX() && (CM == "medium" || CM == "large")) {
chenzheng1030 wrote:
I think `-mcmodel=small` will cause same error?
https://github.com/llvm/llvm-project/pull/70652
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[compiler-rt] [libcxx] [llvm] [lldb] [flang] [clang] [clang-tools-extra] [libc] [PowerPC] Support mcmodel=large for AIX (PR #70652)
@@ -5723,16 +5723,14 @@ void Clang::ConstructJob(Compilation &C, const
JobAction &JA,
if (Arg *A = Args.getLastArg(options::OPT_mcmodel_EQ)) {
StringRef CM = A->getValue();
bool Ok = false;
-if (Triple.isOSAIX() && CM == "medium") {
+if (Triple.isOSAIX() && CM == "medium")
CM = "large";
- Ok = true;
-}
if (Triple.isAArch64(64)) {
Ok = CM == "tiny" || CM == "small" || CM == "large";
if (CM == "large" && RelocationModel != llvm::Reloc::Static)
D.Diag(diag::err_drv_argument_only_allowed_with)
<< A->getAsString(Args) << "-fno-pic";
-} else if (Triple.isPPC64()) {
+} else if (Triple.isPPC64() || Triple.isOSAIX()) {
chenzheng1030 wrote:
AIX seems good now.
However I think we still have one active ppc32 target like SPE working on PPC.
So now clang can not accept any code model for target `-target powerpcspe`.
>From simple testing, this target supports all these three models.
https://github.com/llvm/llvm-project/pull/70652
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[llvm] [clang] [PowerPC] Add an alias for -mregnames so that full register names used in assembly. (PR #70255)
https://github.com/chenzheng1030 approved this pull request. Thanks for adding this. LGTM https://github.com/llvm/llvm-project/pull/70255 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PowerPC] Add an alias for -mregnames so that full register names used in assembly. (PR #70255)
https://github.com/chenzheng1030 edited https://github.com/llvm/llvm-project/pull/70255 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [PowerPC] Add an alias for -mregnames so that full register names used in assembly. (PR #70255)
@@ -197,6 +197,7 @@ CODEGENOPT(HIPCorrectlyRoundedDivSqrt, 1, 1) ///< -fno-hip-fp32-correctly-rounde CODEGENOPT(HIPSaveKernelArgName, 1, 0) ///< Set when -fhip-kernel-arg-name is enabled. CODEGENOPT(UniqueInternalLinkageNames, 1, 0) ///< Internal Linkage symbols get unique names. CODEGENOPT(SplitMachineFunctions, 1, 0) ///< Split machine functions using profile information. +CODEGENOPT(PPCUseFullRegisterNames, 1, 0) ///< Print full register names in assembly -mregnames chenzheng1030 wrote: Nit: the last `-mregnames` seems unnecessary? https://github.com/llvm/llvm-project/pull/70255 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[compiler-rt] [flang] [libcxx] [libc] [lldb] [clang-tools-extra] [clang] [llvm] [PowerPC] Support mcmodel=large for AIX (PR #70652)
@@ -5723,16 +5723,14 @@ void Clang::ConstructJob(Compilation &C, const
JobAction &JA,
if (Arg *A = Args.getLastArg(options::OPT_mcmodel_EQ)) {
StringRef CM = A->getValue();
bool Ok = false;
-if (Triple.isOSAIX() && CM == "medium") {
+if (Triple.isOSAIX() && CM == "medium")
CM = "large";
- Ok = true;
-}
if (Triple.isAArch64(64)) {
Ok = CM == "tiny" || CM == "small" || CM == "large";
if (CM == "large" && RelocationModel != llvm::Reloc::Static)
D.Diag(diag::err_drv_argument_only_allowed_with)
<< A->getAsString(Args) << "-fno-pic";
-} else if (Triple.isPPC64()) {
+} else if (Triple.isPPC64() || Triple.isOSAIX()) {
chenzheng1030 wrote:
```
int b = 20;
int foo()
{
return b;
}
```
- Small code model:
```
.foo:
# %bb.0:# %entry
lwz 3, L..C0(2) # @b ;; Use one instruction to
load b's address in the TOC. So only 2^16 bytes TOC range can be accessed
because of encoding limitation of `lwz` instruction.
lwz 3, 0(3)
blr
```
- large code model
```
.foo:
# %bb.0:# %entry
addis 3, L..C0@u(2)
lwz 3, L..C0@l(3) ;; Use two instructions to load b's address.
So that bigger TOC range can be accessed.
lwz 3, 0(3)
blr
```
https://github.com/llvm/llvm-project/pull/70652
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[compiler-rt] [flang] [libcxx] [libc] [lldb] [clang-tools-extra] [clang] [llvm] [PowerPC] Support mcmodel=large for AIX (PR #70652)
https://github.com/chenzheng1030 approved this pull request. @ecnelises Let's first fix this for AIX. Could you please help to create a github issue for the SPE? Thanks. https://github.com/llvm/llvm-project/pull/70652 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [PowerPC] Implement fence builtin (PR #76495)
@@ -944,6 +944,9 @@ TARGET_BUILTIN(__builtin_pack_vector_int128, "V1LLLiULLiULLi", "", "vsx") // Set the floating point rounding mode BUILTIN(__builtin_setrnd, "di", "") +// Barrier for instruction motion chenzheng1030 wrote: Can we add some comments here to emphasize that `__fence` will stop code motion for register based instructions? https://github.com/llvm/llvm-project/pull/76495 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PowerPC] Implement fence builtin (PR #76495)
https://github.com/chenzheng1030 edited https://github.com/llvm/llvm-project/pull/76495 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [PowerPC] Implement fence builtin (PR #76495)
@@ -944,6 +944,9 @@ TARGET_BUILTIN(__builtin_pack_vector_int128, "V1LLLiULLiULLi", "", "vsx") // Set the floating point rounding mode BUILTIN(__builtin_setrnd, "di", "") +// Barrier for instruction motion +BUILTIN(__builtin_ppc_fence, "v", "") chenzheng1030 wrote: nit: maybe we can put this builtin around line 100, together with other XL Compatibility built-ins. https://github.com/llvm/llvm-project/pull/76495 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [PowerPC] Implement fence builtin (PR #76495)
https://github.com/chenzheng1030 approved this pull request. LGTM with nits. https://github.com/llvm/llvm-project/pull/76495 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [clang-tools-extra] [PowerPC] Implement llvm.set.rounding intrinsic (PR #67302)
https://github.com/chenzheng1030 commented: Maybe we can do some perf test between this expansion for set rounding mode and the system library's version for `fesetround()`. On AIX, I saw some improvements were introduced in the system library's implementation. https://github.com/llvm/llvm-project/pull/67302 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang-tools-extra] [clang] [PowerPC] Implement llvm.set.rounding intrinsic (PR #67302)
https://github.com/chenzheng1030 edited https://github.com/llvm/llvm-project/pull/67302 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang-tools-extra] [llvm] [PowerPC] Implement llvm.set.rounding intrinsic (PR #67302)
@@ -8900,6 +8900,82 @@ SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
return FP;
}
+SDValue PPCTargetLowering::LowerSET_ROUNDING(SDValue Op,
+ SelectionDAG &DAG) const {
+ SDLoc Dl(Op);
+ MachineFunction &MF = DAG.getMachineFunction();
+ EVT PtrVT = getPointerTy(MF.getDataLayout());
+ SDValue Chain = Op.getOperand(0);
+
+ // If requested mode is constant, just use simpler mtfsb.
+ if (auto *CVal = dyn_cast(Op.getOperand(1))) {
+uint64_t Mode = CVal->getZExtValue();
+assert(Mode < 4 && "Unsupported rounding mode!");
+unsigned InternalRnd = Mode ^ (~(Mode >> 1) & 1);
+SDNode *SetHi = DAG.getMachineNode(
+(InternalRnd & 2) ? PPC::MTFSB1 : PPC::MTFSB0, Dl, MVT::Other,
+{DAG.getConstant(30, Dl, MVT::i32, true), Chain});
+SDNode *SetLo = DAG.getMachineNode(
+(InternalRnd & 1) ? PPC::MTFSB1 : PPC::MTFSB0, Dl, MVT::Other,
+{DAG.getConstant(31, Dl, MVT::i32, true), SDValue(SetHi, 0)});
+return SDValue(SetLo, 0);
+ }
+
+ // Use x ^ (~(x >> 1) & 1) to transform LLVM rounding mode to Power format.
+ SDValue One = DAG.getConstant(1, Dl, MVT::i32);
+ SDValue SrcFlag = DAG.getNode(ISD::AND, Dl, MVT::i32, Op.getOperand(1),
+DAG.getConstant(3, Dl, MVT::i32));
chenzheng1030 wrote:
Can we add an assert here too if compiler can infer that the high 29 bits of
operand 1 is non-zero?
https://github.com/llvm/llvm-project/pull/67302
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[llvm] [clang-tools-extra] [clang] [PowerPC] Implement llvm.set.rounding intrinsic (PR #67302)
@@ -8900,6 +8900,82 @@ SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
return FP;
}
+SDValue PPCTargetLowering::LowerSET_ROUNDING(SDValue Op,
+ SelectionDAG &DAG) const {
+ SDLoc Dl(Op);
+ MachineFunction &MF = DAG.getMachineFunction();
+ EVT PtrVT = getPointerTy(MF.getDataLayout());
+ SDValue Chain = Op.getOperand(0);
+
+ // If requested mode is constant, just use simpler mtfsb.
+ if (auto *CVal = dyn_cast(Op.getOperand(1))) {
+uint64_t Mode = CVal->getZExtValue();
+assert(Mode < 4 && "Unsupported rounding mode!");
+unsigned InternalRnd = Mode ^ (~(Mode >> 1) & 1);
+SDNode *SetHi = DAG.getMachineNode(
+(InternalRnd & 2) ? PPC::MTFSB1 : PPC::MTFSB0, Dl, MVT::Other,
+{DAG.getConstant(30, Dl, MVT::i32, true), Chain});
+SDNode *SetLo = DAG.getMachineNode(
+(InternalRnd & 1) ? PPC::MTFSB1 : PPC::MTFSB0, Dl, MVT::Other,
+{DAG.getConstant(31, Dl, MVT::i32, true), SDValue(SetHi, 0)});
+return SDValue(SetLo, 0);
+ }
+
+ // Use x ^ (~(x >> 1) & 1) to transform LLVM rounding mode to Power format.
+ SDValue One = DAG.getConstant(1, Dl, MVT::i32);
+ SDValue SrcFlag = DAG.getNode(ISD::AND, Dl, MVT::i32, Op.getOperand(1),
+DAG.getConstant(3, Dl, MVT::i32));
+ SDValue DstFlag = DAG.getNode(
+ ISD::XOR, Dl, MVT::i32, SrcFlag,
+ DAG.getNode(ISD::AND, Dl, MVT::i32,
+ DAG.getNOT(Dl,
+ DAG.getNode(ISD::SRL, Dl, MVT::i32, SrcFlag, One),
+ MVT::i32),
+ One));
+ SDValue MFFS = DAG.getNode(PPCISD::MFFS, Dl, {MVT::f64, MVT::Other}, Chain);
+ Chain = MFFS.getValue(1);
+ SDValue NewFPSCR;
+ if (isTypeLegal(MVT::i64)) {
+// Set the last two bits (rounding mode) of bitcasted FPSCR.
+NewFPSCR = DAG.getNode(
+ISD::OR, Dl, MVT::i64,
+DAG.getNode(ISD::AND, Dl, MVT::i64,
+DAG.getNode(ISD::BITCAST, Dl, MVT::i64, MFFS),
+DAG.getNOT(Dl, DAG.getConstant(3, Dl, MVT::i64),
MVT::i64)),
+DAG.getNode(ISD::ZERO_EXTEND, Dl, MVT::i64, DstFlag));
+NewFPSCR = DAG.getNode(ISD::BITCAST, Dl, MVT::f64, NewFPSCR);
+ } else {
+// In 32-bit mode, store f64, load and update the lower half.
+int SSFI = MF.getFrameInfo().CreateStackObject(8, Align(8), false);
+SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
+Chain = DAG.getStore(Chain, Dl, MFFS, StackSlot, MachinePointerInfo());
+SDValue Addr;
+if (Subtarget.isLittleEndian())
+ Addr = StackSlot;
+else
+ Addr = DAG.getNode(ISD::ADD, Dl, PtrVT, StackSlot,
+ DAG.getConstant(4, Dl, PtrVT));
+SDValue Tmp = DAG.getLoad(MVT::i32, Dl, Chain, Addr, MachinePointerInfo());
+Chain = Tmp.getValue(1);
+
+Tmp = DAG.getNode(
+ISD::OR, Dl, MVT::i32,
+DAG.getNode(ISD::AND, Dl, MVT::i32, Tmp,
+DAG.getNOT(Dl, DAG.getConstant(3, Dl, MVT::i32),
MVT::i32)),
+DstFlag);
chenzheng1030 wrote:
Can we use a single `rlwimi` to update the lowest 2 bits of `tmp`?
https://github.com/llvm/llvm-project/pull/67302
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[clang-tools-extra] [llvm] [clang] [PowerPC] Implement llvm.set.rounding intrinsic (PR #67302)
@@ -77,4 +77,196 @@ return: ; preds = %entry
ret i32 %retval3
}
-declare i32 @llvm.get.rounding() nounwind
+define void @setrnd_tozero() {
+; PPC32-LABEL: setrnd_tozero:
+; PPC32: # %bb.0: # %entry
+; PPC32-NEXT:mtfsb0 30
+; PPC32-NEXT:mtfsb1 31
+; PPC32-NEXT:blr
+;
+; PPC64-LABEL: setrnd_tozero:
+; PPC64: # %bb.0: # %entry
+; PPC64-NEXT:mtfsb0 30
+; PPC64-NEXT:mtfsb1 31
+; PPC64-NEXT:blr
+;
+; PPC64LE-LABEL: setrnd_tozero:
+; PPC64LE: # %bb.0: # %entry
+; PPC64LE-NEXT:mtfsb0 30
+; PPC64LE-NEXT:mtfsb1 31
+; PPC64LE-NEXT:blr
+;
+; DM-LABEL: setrnd_tozero:
+; DM: # %bb.0: # %entry
+; DM-NEXT:mtfsb0 30
+; DM-NEXT:mtfsb1 31
+; DM-NEXT:blr
+entry:
+ call void @llvm.set.rounding(i32 0)
+ ret void
+}
+
+define void @setrnd_tonearest_tieeven() {
+; PPC32-LABEL: setrnd_tonearest_tieeven:
+; PPC32: # %bb.0: # %entry
+; PPC32-NEXT:mtfsb0 30
+; PPC32-NEXT:mtfsb0 31
+; PPC32-NEXT:blr
+;
+; PPC64-LABEL: setrnd_tonearest_tieeven:
+; PPC64: # %bb.0: # %entry
+; PPC64-NEXT:mtfsb0 30
+; PPC64-NEXT:mtfsb0 31
+; PPC64-NEXT:blr
+;
+; PPC64LE-LABEL: setrnd_tonearest_tieeven:
+; PPC64LE: # %bb.0: # %entry
+; PPC64LE-NEXT:mtfsb0 30
+; PPC64LE-NEXT:mtfsb0 31
+; PPC64LE-NEXT:blr
+;
+; DM-LABEL: setrnd_tonearest_tieeven:
+; DM: # %bb.0: # %entry
+; DM-NEXT:mtfsb0 30
+; DM-NEXT:mtfsb0 31
+; DM-NEXT:blr
+entry:
+ call void @llvm.set.rounding(i32 1)
+ ret void
+}
+
+define void @setrnd_toposinf() {
+; PPC32-LABEL: setrnd_toposinf:
+; PPC32: # %bb.0: # %entry
+; PPC32-NEXT:mtfsb1 30
+; PPC32-NEXT:mtfsb0 31
+; PPC32-NEXT:blr
+;
+; PPC64-LABEL: setrnd_toposinf:
+; PPC64: # %bb.0: # %entry
+; PPC64-NEXT:mtfsb1 30
+; PPC64-NEXT:mtfsb0 31
+; PPC64-NEXT:blr
+;
+; PPC64LE-LABEL: setrnd_toposinf:
+; PPC64LE: # %bb.0: # %entry
+; PPC64LE-NEXT:mtfsb1 30
+; PPC64LE-NEXT:mtfsb0 31
+; PPC64LE-NEXT:blr
+;
+; DM-LABEL: setrnd_toposinf:
+; DM: # %bb.0: # %entry
+; DM-NEXT:mtfsb1 30
+; DM-NEXT:mtfsb0 31
+; DM-NEXT:blr
+entry:
+ call void @llvm.set.rounding(i32 2)
+ ret void
+}
+
+define void @setrnd_toneginf() {
+; PPC32-LABEL: setrnd_toneginf:
+; PPC32: # %bb.0: # %entry
+; PPC32-NEXT:mtfsb1 30
+; PPC32-NEXT:mtfsb1 31
+; PPC32-NEXT:blr
+;
+; PPC64-LABEL: setrnd_toneginf:
+; PPC64: # %bb.0: # %entry
+; PPC64-NEXT:mtfsb1 30
+; PPC64-NEXT:mtfsb1 31
+; PPC64-NEXT:blr
+;
+; PPC64LE-LABEL: setrnd_toneginf:
+; PPC64LE: # %bb.0: # %entry
+; PPC64LE-NEXT:mtfsb1 30
+; PPC64LE-NEXT:mtfsb1 31
+; PPC64LE-NEXT:blr
+;
+; DM-LABEL: setrnd_toneginf:
+; DM: # %bb.0: # %entry
+; DM-NEXT:mtfsb1 30
+; DM-NEXT:mtfsb1 31
+; DM-NEXT:blr
+entry:
+ call void @llvm.set.rounding(i32 3)
+ ret void
+}
+
+define void @setrnd_var(i32 %x) {
+; PPC32-LABEL: setrnd_var:
+; PPC32: # %bb.0: # %entry
+; PPC32-NEXT:stwu 1, -16(1)
+; PPC32-NEXT:.cfi_def_cfa_offset 16
chenzheng1030 wrote:
nit: no need for the cfi pseudos.
https://github.com/llvm/llvm-project/pull/67302
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[llvm] [clang-tools-extra] [clang] [PowerPC] Implement llvm.set.rounding intrinsic (PR #67302)
@@ -8900,6 +8900,82 @@ SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
return FP;
}
+SDValue PPCTargetLowering::LowerSET_ROUNDING(SDValue Op,
+ SelectionDAG &DAG) const {
+ SDLoc Dl(Op);
+ MachineFunction &MF = DAG.getMachineFunction();
+ EVT PtrVT = getPointerTy(MF.getDataLayout());
+ SDValue Chain = Op.getOperand(0);
+
+ // If requested mode is constant, just use simpler mtfsb.
+ if (auto *CVal = dyn_cast(Op.getOperand(1))) {
+uint64_t Mode = CVal->getZExtValue();
+assert(Mode < 4 && "Unsupported rounding mode!");
+unsigned InternalRnd = Mode ^ (~(Mode >> 1) & 1);
+SDNode *SetHi = DAG.getMachineNode(
+(InternalRnd & 2) ? PPC::MTFSB1 : PPC::MTFSB0, Dl, MVT::Other,
+{DAG.getConstant(30, Dl, MVT::i32, true), Chain});
+SDNode *SetLo = DAG.getMachineNode(
+(InternalRnd & 1) ? PPC::MTFSB1 : PPC::MTFSB0, Dl, MVT::Other,
+{DAG.getConstant(31, Dl, MVT::i32, true), SDValue(SetHi, 0)});
+return SDValue(SetLo, 0);
+ }
+
+ // Use x ^ (~(x >> 1) & 1) to transform LLVM rounding mode to Power format.
chenzheng1030 wrote:
The comment does not match below logic. x should be (x & 3)?
And the LLVM mode 4(`4 - to nearest, ties away from zero`) is mapped to Power
mode 1(`1 - toward zero`)? I think LLVM mode 4 should map to Power mode 0(0-
Round to Nearest)?
https://github.com/llvm/llvm-project/pull/67302
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[llvm] [clang] [clang-tools-extra] [PowerPC] Implement llvm.set.rounding intrinsic (PR #67302)
@@ -8900,6 +8900,82 @@ SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
return FP;
}
+SDValue PPCTargetLowering::LowerSET_ROUNDING(SDValue Op,
+ SelectionDAG &DAG) const {
+ SDLoc Dl(Op);
+ MachineFunction &MF = DAG.getMachineFunction();
+ EVT PtrVT = getPointerTy(MF.getDataLayout());
+ SDValue Chain = Op.getOperand(0);
+
+ // If requested mode is constant, just use simpler mtfsb.
+ if (auto *CVal = dyn_cast(Op.getOperand(1))) {
chenzheng1030 wrote:
Can we use `DAG.computeKnownBits()` to handle more cases instead of just the
constant inputs?
https://github.com/llvm/llvm-project/pull/67302
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[clang-tools-extra] [llvm] [clang] [PowerPC] Implement llvm.set.rounding intrinsic (PR #67302)
@@ -8900,6 +8900,82 @@ SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
return FP;
}
+SDValue PPCTargetLowering::LowerSET_ROUNDING(SDValue Op,
+ SelectionDAG &DAG) const {
+ SDLoc Dl(Op);
+ MachineFunction &MF = DAG.getMachineFunction();
+ EVT PtrVT = getPointerTy(MF.getDataLayout());
+ SDValue Chain = Op.getOperand(0);
+
+ // If requested mode is constant, just use simpler mtfsb.
+ if (auto *CVal = dyn_cast(Op.getOperand(1))) {
+uint64_t Mode = CVal->getZExtValue();
+assert(Mode < 4 && "Unsupported rounding mode!");
+unsigned InternalRnd = Mode ^ (~(Mode >> 1) & 1);
+SDNode *SetHi = DAG.getMachineNode(
+(InternalRnd & 2) ? PPC::MTFSB1 : PPC::MTFSB0, Dl, MVT::Other,
+{DAG.getConstant(30, Dl, MVT::i32, true), Chain});
+SDNode *SetLo = DAG.getMachineNode(
+(InternalRnd & 1) ? PPC::MTFSB1 : PPC::MTFSB0, Dl, MVT::Other,
+{DAG.getConstant(31, Dl, MVT::i32, true), SDValue(SetHi, 0)});
+return SDValue(SetLo, 0);
+ }
+
+ // Use x ^ (~(x >> 1) & 1) to transform LLVM rounding mode to Power format.
+ SDValue One = DAG.getConstant(1, Dl, MVT::i32);
+ SDValue SrcFlag = DAG.getNode(ISD::AND, Dl, MVT::i32, Op.getOperand(1),
+DAG.getConstant(3, Dl, MVT::i32));
+ SDValue DstFlag = DAG.getNode(
+ ISD::XOR, Dl, MVT::i32, SrcFlag,
+ DAG.getNode(ISD::AND, Dl, MVT::i32,
+ DAG.getNOT(Dl,
+ DAG.getNode(ISD::SRL, Dl, MVT::i32, SrcFlag, One),
+ MVT::i32),
+ One));
+ SDValue MFFS = DAG.getNode(PPCISD::MFFS, Dl, {MVT::f64, MVT::Other}, Chain);
+ Chain = MFFS.getValue(1);
+ SDValue NewFPSCR;
+ if (isTypeLegal(MVT::i64)) {
chenzheng1030 wrote:
maybe `Subtarget.isPPC64()` is more clear.
https://github.com/llvm/llvm-project/pull/67302
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[clang] 3c776c7 - [PowerPC] add XLC compat builtin __abs
Author: Chen Zheng
Date: 2022-04-20T05:14:22-04:00
New Revision: 3c776c70a76e9fe51fd978595315e6cef8e7fbb0
URL:
https://github.com/llvm/llvm-project/commit/3c776c70a76e9fe51fd978595315e6cef8e7fbb0
DIFF:
https://github.com/llvm/llvm-project/commit/3c776c70a76e9fe51fd978595315e6cef8e7fbb0.diff
LOG: [PowerPC] add XLC compat builtin __abs
Reviewed By: jsji
Differential Revision: https://reviews.llvm.org/D123372
Added:
Modified:
clang/lib/Basic/Targets/PPC.cpp
clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-macros.c
Removed:
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 1f2f583b9462d..e3ee68cd1fa30 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -208,6 +208,7 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
Builder.defineMacro("__dcbf", "__builtin_dcbf");
Builder.defineMacro("__fmadd", "__builtin_fma");
Builder.defineMacro("__fmadds", "__builtin_fmaf");
+ Builder.defineMacro("__abs", "__builtin_abs");
Builder.defineMacro("__labs", "__builtin_labs");
Builder.defineMacro("__llabs", "__builtin_llabs");
Builder.defineMacro("__popcnt4", "__builtin_popcount");
diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-macros.c
b/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-macros.c
index 268dceaa06cb5..cec1ac6cd5655 100644
--- a/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-macros.c
+++ b/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-macros.c
@@ -12,6 +12,19 @@
// Required for size_t. Usually found in stddef.h.
typedef __SIZE_TYPE__ size_t;
+// BOTH-LABEL: @testabs(
+// BOTH-NEXT: entry:
+// BOTH-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// BOTH-NEXT:store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// BOTH-NEXT:[[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// BOTH-NEXT:[[NEG:%.*]] = sub nsw i32 0, [[TMP0]]
+// BOTH-NEXT:[[ABSCOND:%.*]] = icmp slt i32 [[TMP0]], 0
+// BOTH-NEXT:[[ABS:%.*]] = select i1 [[ABSCOND]], i32 [[NEG]], i32 [[TMP0]]
+// BOTH-NEXT:ret i32 [[ABS]]
+signed int testabs(signed int a) {
+ return __abs(a);
+}
+
// 64BIT-LABEL: @testlabs(
// 64BIT-NEXT: entry:
// 64BIT-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
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[clang] ecdeabe - enable P10 vector builtins test on AIX 64 bit; NFC
Author: Chen Zheng Date: 2022-07-21T03:51:30-04:00 New Revision: ecdeabef385d13bc0c3b935cc56b09883fd7b108 URL: https://github.com/llvm/llvm-project/commit/ecdeabef385d13bc0c3b935cc56b09883fd7b108 DIFF: https://github.com/llvm/llvm-project/commit/ecdeabef385d13bc0c3b935cc56b09883fd7b108.diff LOG: enable P10 vector builtins test on AIX 64 bit; NFC Verify that P10 vector builtins with type `vector signed __int128` and `vector unsigned __int128` work well on AIX 64 bit. Added: Modified: clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c Removed: diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c b/clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c index c76298a4f0f98..694d2795d335b 100644 --- a/clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c @@ -5,6 +5,9 @@ // RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +vsx \ // RUN: -target-cpu pwr10 -triple powerpc64le-unknown-unknown -emit-llvm %s \ // RUN: -o - | FileCheck %s -check-prefixes=CHECK-LE,CHECK +// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +vsx \ +// RUN: -target-cpu pwr10 -triple powerpc64-ibm-aix-xcoff -emit-llvm %s \ +// RUN: -o - | FileCheck %s -check-prefixes=CHECK-BE,CHECK #include ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PowerPC] Add restriction for rldimi builtin (PR #85040)
@@ -24,13 +24,17 @@ void test_trap(void) {
__tw(ia, ib, 0); //expected-error {{argument value 0 is outside the valid
range [1, 31]}}
}
+#ifdef __PPC64__
void test_builtin_ppc_rldimi() {
unsigned int shift;
unsigned long long mask;
unsigned long long res = __builtin_ppc_rldimi(ull, ull, shift, 7); //
expected-error {{argument to '__builtin_ppc_rldimi' must be a constant integer}}
res = __builtin_ppc_rldimi(ull, ull, 63, mask);//
expected-error {{argument to '__builtin_ppc_rldimi' must be a constant integer}}
res = __builtin_ppc_rldimi(ull, ull, 63, 0x0F00); //
expected-error {{argument 3 value should represent a contiguous bit field}}
+ res = __builtin_ppc_rldimi(ull, ull, 63, 0x0F00); //
expected-error {{argument 3 value should represent a contiguous bit field}}
chenzheng1030 wrote:
This case seems same with above one?
https://github.com/llvm/llvm-project/pull/85040
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[clang] [llvm] [PowerPC] Add restriction for rldimi builtin (PR #85040)
@@ -5093,9 +5094,33 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo
&TI, unsigned BuiltinID,
case PPC::BI__builtin_ppc_rlwnm:
return SemaValueIsRunOfOnes(TheCall, 2);
case PPC::BI__builtin_ppc_rlwimi:
- case PPC::BI__builtin_ppc_rldimi:
return SemaBuiltinConstantArg(TheCall, 2, Result) ||
SemaValueIsRunOfOnes(TheCall, 3);
+ case PPC::BI__builtin_ppc_rldimi: {
+llvm::APSInt SH;
+if (SemaBuiltinConstantArg(TheCall, 2, SH) ||
+SemaBuiltinConstantArg(TheCall, 3, Result))
+ return true;
+if (SH > 63)
+ return Diag(TheCall->getBeginLoc(), diag::err_argument_invalid_range)
+ << toString(Result, 10) << 0 << 63 << TheCall->getSourceRange();
+unsigned MB = 0, ML = 0;
+if (Result.isShiftedMask(MB, ML)) {
+ MB = 64 - MB - ML;
+} else if ((~Result).isShiftedMask(MB, ML)) {
+ MB = 64 - MB;
+ ML = 64 - ML;
+} else {
+ return Diag(TheCall->getBeginLoc(),
+ diag::err_argument_not_contiguous_bit_field)
+ << 3 << TheCall->getSourceRange();
+}
+if ((MB + ML - 1) % 64 != 63 - SH.getZExtValue())
chenzheng1030 wrote:
I am a little worried about this check. This adds more restriction on the
__rldimi builtin than IBM XLC does. And what do you expect the mask looks like
if the mask is wrapped? i.e., MB > 64 -SH.
How about we accept all continuous 1 masks, and in the backend while lowering
the intrinsic if the mask matches the `rlwinm` instruction encoding
requirement, we use only one rlwinm instructions. Otherwise we use two
instructions, like:
```
__rldimi(a, b, SH, mask)
```
->
```
rldicl rx,a,SH,0
rldimib,rx,0,mask
```
https://github.com/llvm/llvm-project/pull/85040
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[clang] [llvm] [PowerPC] Add restriction for rldimi builtin (PR #85040)
@@ -24,13 +24,17 @@ void test_trap(void) {
__tw(ia, ib, 0); //expected-error {{argument value 0 is outside the valid
range [1, 31]}}
}
+#ifdef __PPC64__
void test_builtin_ppc_rldimi() {
unsigned int shift;
unsigned long long mask;
unsigned long long res = __builtin_ppc_rldimi(ull, ull, shift, 7); //
expected-error {{argument to '__builtin_ppc_rldimi' must be a constant integer}}
res = __builtin_ppc_rldimi(ull, ull, 63, mask);//
expected-error {{argument to '__builtin_ppc_rldimi' must be a constant integer}}
res = __builtin_ppc_rldimi(ull, ull, 63, 0x0F00); //
expected-error {{argument 3 value should represent a contiguous bit field}}
+ res = __builtin_ppc_rldimi(ull, ull, 63, 0x0F00); //
expected-error {{argument 3 value should represent a contiguous bit field}}
chenzheng1030 wrote:
Miss a case for shift value > 63?
https://github.com/llvm/llvm-project/pull/85040
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[clang] [llvm] [PowerPC] Fix behavior of rldimi/rlwimi/rlwnm builtins (PR #85040)
https://github.com/chenzheng1030 commented: Looks almost good to me though I have a comment for the all one mask case. https://github.com/llvm/llvm-project/pull/85040 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PowerPC] Fix behavior of rldimi/rlwimi/rlwnm builtins (PR #85040)
https://github.com/chenzheng1030 edited https://github.com/llvm/llvm-project/pull/85040 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PowerPC] Fix behavior of rldimi/rlwimi/rlwnm builtins (PR #85040)
@@ -10764,30 +10764,53 @@ SDValue
PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
return DAG.getRegister(PPC::R2, MVT::i32);
case Intrinsic::ppc_rldimi: {
+assert(Subtarget.isPPC64() && "rldimi is only available in 64-bit!");
+if (Op.getConstantOperandVal(4) == 0)
+ return Op.getOperand(2);
uint64_t SH = Op.getConstantOperandVal(3);
unsigned MB = 0, ME = 0;
-if (!isRunOfOnes64(Op.getConstantOperandVal(4), MB, ME) || ME != 63 - SH)
+if (!isRunOfOnes64(Op.getConstantOperandVal(4), MB, ME))
report_fatal_error("invalid rldimi mask!");
-return SDValue(DAG.getMachineNode(
- PPC::RLDIMI, dl, MVT::i64,
- {Op.getOperand(1), Op.getOperand(2), Op.getOperand(3),
-DAG.getTargetConstant(MB, dl, MVT::i32)}),
- 0);
+
+// For all-one mask, MB will be set to 0, adjust it next to 63-SH.
chenzheng1030 wrote:
For all-one mask, to improve the readability, is it better to just return the
`Intrinsic::ppc_rldimi` as `ISD::ROTL (Op.getOperand(1), Op.getOperand(3))`?
I think this would also benefit later optimizations as we are using a ISD node
here.
https://github.com/llvm/llvm-project/pull/85040
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[clang] [llvm] [PowerPC] Fix behavior of rldimi/rlwimi/rlwnm builtins (PR #85040)
@@ -72,4 +72,74 @@ define i64 @rldimi_intrinsic(i64 %a) {
ret i64 %r3
}
+define i64 @rldimi5(i64 %a, i64 %b) {
+; CHECK-LABEL: rldimi5:
+; CHECK: # %bb.0:
+; CHECK-NEXT:rldimi 4, 3, 8, 40
+; CHECK-NEXT:mr 3, 4
+; CHECK-NEXT:blr
+ %r = call i64 @llvm.ppc.rldimi(i64 %a, i64 %b, i32 8, i64 16776960) ; 0x
<< 8
+ ret i64 %r
+}
+
+define i64 @rldimi6(i64 %a, i64 %b) {
+; CHECK-LABEL: rldimi6:
+; CHECK: # %bb.0:
+; CHECK-NEXT:rotldi 3, 3, 1
+; CHECK-NEXT:rldimi 4, 3, 7, 41
+; CHECK-NEXT:mr 3, 4
+; CHECK-NEXT:blr
+ %r = call i64 @llvm.ppc.rldimi(i64 %a, i64 %b, i32 8, i64 8388480) ; 0x
<< 7
+ ret i64 %r
+}
+
+define i64 @rldimi7(i64 %a, i64 %b) {
+; CHECK-LABEL: rldimi7:
+; CHECK: # %bb.0:
+; CHECK-NEXT:rotldi 3, 3, 63
+; CHECK-NEXT:rldimi 4, 3, 9, 39
+; CHECK-NEXT:mr 3, 4
+; CHECK-NEXT:blr
+ %r = call i64 @llvm.ppc.rldimi(i64 %a, i64 %b, i32 8, i64 33553920) ; 0x
<< 9
+ ret i64 %r
+}
+
+define i64 @rldimi8(i64 %a, i64 %b) {
+; CHECK-LABEL: rldimi8:
+; CHECK: # %bb.0:
+; CHECK-NEXT:mr 3, 4
+; CHECK-NEXT:blr
+ %r = call i64 @llvm.ppc.rldimi(i64 %a, i64 %b, i32 0, i64 0)
+ ret i64 %r
+}
+
+define i64 @rldimi9(i64 %a, i64 %b) {
+; CHECK-LABEL: rldimi9:
+; CHECK: # %bb.0:
+; CHECK-NEXT:mr 3, 4
+; CHECK-NEXT:blr
+ %r = call i64 @llvm.ppc.rldimi(i64 %a, i64 %b, i32 63, i64 0)
+ ret i64 %r
+}
+
+define i64 @rldimi10(i64 %a, i64 %b) {
+; CHECK-LABEL: rldimi10:
+; CHECK: # %bb.0:
+; CHECK-NEXT:rldimi 4, 3, 0, 0
+; CHECK-NEXT:mr 3, 4
+; CHECK-NEXT:blr
+ %r = call i64 @llvm.ppc.rldimi(i64 %a, i64 %b, i32 0, i64 -1)
+ ret i64 %r
+}
+
+define i64 @rldimi11(i64 %a, i64 %b) {
+; CHECK-LABEL: rldimi11:
+; CHECK: # %bb.0:
+; CHECK-NEXT:rldimi 4, 3, 8, 56
+; CHECK-NEXT:mr 3, 4
+; CHECK-NEXT:blr
+ %r = call i64 @llvm.ppc.rldimi(i64 %a, i64 %b, i32 8, i64 -1)
chenzheng1030 wrote:
If we change to use `ISD::ROTL`, we will get `rotldi` as this place. Although
`rldimi 4, 3, 8, 56` is right, it uses a wrap full mask. `rotldi` may be more
friendly for optimizations like PPC peepholes.
https://github.com/llvm/llvm-project/pull/85040
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[clang] [llvm] [PowerPC] Fix behavior of rldimi/rlwimi/rlwnm builtins (PR #85040)
https://github.com/chenzheng1030 approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/85040 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PowerPC] Add intrinsics for rldimi/rlwimi/rlwnm (PR #82968)
@@ -10722,6 +10723,20 @@ static bool getVectorCompareInfo(SDValue Intrin, int &CompareOpc, return true; } +bool isContiguousMask(const APInt &Val, unsigned &MB, unsigned &ME, chenzheng1030 wrote: Is it possible to reuse `isRunOfOnes()`/`isRunOfOnes64()` in `llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h`? https://github.com/llvm/llvm-project/pull/82968 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PowerPC] Add intrinsics for rldimi/rlwimi/rlwnm (PR #82968)
@@ -641,6 +641,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, // We want to custom lower some of our intrinsics. setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); + // setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom); chenzheng1030 wrote: Is this needed? https://github.com/llvm/llvm-project/pull/82968 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PowerPC] Add intrinsics for rldimi/rlwimi/rlwnm (PR #82968)
chenzheng1030 wrote: > If you run into issues using normal integer ops, please file bugs. Most > people aren't going to hand-tune their code like this; builtins like this are > at best an ugly workaround. Yes, a user should not try to write source code(using compiler builtins) to just emit one "powerful" instruction. Instead, it is compiler's responsibility to generate these instructions according to user's source codes. I think the reason why these builtins were added is LLVM PowerPC target wants to keep its compatibility with XLC/C++ commercial compiler related to these builtins. https://github.com/llvm/llvm-project/pull/82968 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PowerPC] Add intrinsics for rldimi/rlwimi/rlwnm (PR #82968)
@@ -58,3 +58,18 @@ entry:
%8 = or i64 %6, %7
ret i64 %8
}
+
+define i64 @rldimi_intrinsic(i64 %a) {
+; CHECK-LABEL: rldimi_intrinsic:
+; CHECK: # %bb.0:
+; CHECK-NEXT:rldimi 3, 3, 8, 0
+; CHECK-NEXT:rldimi 3, 3, 16, 0
+; CHECK-NEXT:rldimi 3, 3, 32, 0
+; CHECK-NEXT:blr
+ %r1 = call i64 @llvm.ppc.rldimi(i64 %a, i64 %a, i32 8, i64 -256)
+ %r2 = call i64 @llvm.ppc.rldimi(i64 %r1, i64 %r1, i32 16, i64 -65536)
+ %r3 = call i64 @llvm.ppc.rldimi(i64 %r2, i64 %r2, i32 32, i64 -4294967296)
+ ret i64 %r3
+}
+
+declare i64 @llvm.ppc.rldimi(i64, i64, i32 immarg, i64 immarg)
chenzheng1030 wrote:
nit: missing % before immarg? Why not just remove them?
https://github.com/llvm/llvm-project/pull/82968
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[clang] [llvm] [PowerPC] Add intrinsics for rldimi/rlwimi/rlwnm (PR #82968)
https://github.com/chenzheng1030 edited https://github.com/llvm/llvm-project/pull/82968 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PowerPC] Add intrinsics for rldimi/rlwimi/rlwnm (PR #82968)
https://github.com/chenzheng1030 approved this pull request. LGTM except two comments in the case change. One is a nit and the other one should be other issue unrelated to this patch. Thanks for implementing this. https://github.com/llvm/llvm-project/pull/82968 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PowerPC] Add intrinsics for rldimi/rlwimi/rlwnm (PR #82968)
@@ -1,61 +1,111 @@
-; All of these ands and shifts should be folded into rlwimi's
-; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -o %t
-; RUN: not grep and %t
-; RUN: not grep srawi %t
-; RUN: not grep srwi %t
-; RUN: not grep slwi %t
-; RUN: grep rlwinm %t | count 8
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu |
FileCheck %s
define i32 @test1(i32 %a) {
+; CHECK-LABEL: test1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:rlwinm 3, 3, 0, 4, 19
+; CHECK-NEXT:blr
entry:
- %tmp.1 = and i32 %a, 268431360 ; [#uses=1]
- ret i32 %tmp.1
+ %tmp.1 = and i32 %a, 268431360
+ ret i32 %tmp.1
}
define i32 @test2(i32 %a) {
+; CHECK-LABEL: test2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:rldicl 3, 3, 36, 24
+; CHECK-NEXT:rldicl 3, 3, 28, 32
+; CHECK-NEXT:blr
entry:
- %tmp.1 = and i32 %a, -268435441 ; [#uses=1]
- ret i32 %tmp.1
+ %tmp.1 = and i32 %a, -268435441
+ ret i32 %tmp.1
}
define i32 @test3(i32 %a) {
+; CHECK-LABEL: test3:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:rlwinm 3, 3, 24, 24, 31
+; CHECK-NEXT:blr
entry:
- %tmp.2 = ashr i32 %a, 8 ; [#uses=1]
- %tmp.3 = and i32 %tmp.2, 255; [#uses=1]
- ret i32 %tmp.3
+ %tmp.2 = ashr i32 %a, 8
+ %tmp.3 = and i32 %tmp.2, 255
+ ret i32 %tmp.3
}
define i32 @test4(i32 %a) {
+; CHECK-LABEL: test4:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:rlwinm 3, 3, 24, 24, 31
+; CHECK-NEXT:blr
entry:
- %tmp.3 = lshr i32 %a, 8 ; [#uses=1]
- %tmp.4 = and i32 %tmp.3, 255; [#uses=1]
- ret i32 %tmp.4
+ %tmp.3 = lshr i32 %a, 8
+ %tmp.4 = and i32 %tmp.3, 255
+ ret i32 %tmp.4
}
define i32 @test5(i32 %a) {
+; CHECK-LABEL: test5:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:rlwinm 3, 3, 8, 0, 8
+; CHECK-NEXT:blr
entry:
- %tmp.2 = shl i32 %a, 8 ; [#uses=1]
- %tmp.3 = and i32 %tmp.2, -8388608 ; [#uses=1]
- ret i32 %tmp.3
+ %tmp.2 = shl i32 %a, 8
+ %tmp.3 = and i32 %tmp.2, -8388608
+ ret i32 %tmp.3
}
define i32 @test6(i32 %a) {
+; CHECK-LABEL: test6:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:rlwinm 3, 3, 24, 24, 31
+; CHECK-NEXT:blr
entry:
- %tmp.1 = and i32 %a, 65280 ; [#uses=1]
- %tmp.2 = ashr i32 %tmp.1, 8 ; [#uses=1]
- ret i32 %tmp.2
+ %tmp.1 = and i32 %a, 65280
+ %tmp.2 = ashr i32 %tmp.1, 8
+ ret i32 %tmp.2
}
define i32 @test7(i32 %a) {
+; CHECK-LABEL: test7:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:rlwinm 3, 3, 24, 24, 31
+; CHECK-NEXT:blr
entry:
- %tmp.1 = and i32 %a, 65280 ; [#uses=1]
- %tmp.2 = lshr i32 %tmp.1, 8 ; [#uses=1]
- ret i32 %tmp.2
+ %tmp.1 = and i32 %a, 65280
+ %tmp.2 = lshr i32 %tmp.1, 8
+ ret i32 %tmp.2
}
define i32 @test8(i32 %a) {
+; CHECK-LABEL: test8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:rlwinm 3, 3, 8, 0, 7
+; CHECK-NEXT:blr
entry:
- %tmp.1 = and i32 %a, 16711680 ; [#uses=1]
- %tmp.2 = shl i32 %tmp.1, 8 ; [#uses=1]
- ret i32 %tmp.2
+ %tmp.1 = and i32 %a, 16711680
+ %tmp.2 = shl i32 %tmp.1, 8
+ ret i32 %tmp.2
}
+
+define i32 @test9(i32 %a, i32 %s) {
+; CHECK-LABEL: test9:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:rlwnm 3, 3, 4, 23, 31
+; CHECK-NEXT:blr
+entry:
+ %r = call i32 @llvm.ppc.rlwnm(i32 %a, i32 %s, i32 511)
+ ret i32 %r
+}
+
+define i32 @test10(i32 %a) {
+; CHECK-LABEL: test10:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:rlwinm 3, 3, 31, 23, 31
+; CHECK-NEXT:blr
+entry:
+ %r = call i32 @llvm.ppc.rlwnm(i32 %a, i32 31, i32 511)
+ ret i32 %r
+}
+
+declare i32 @llvm.ppc.rlwnm(i32, i32, i32 immarg)
chenzheng1030 wrote:
nit: ditto
https://github.com/llvm/llvm-project/pull/82968
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[clang] [llvm] [PowerPC] Add intrinsics for rldimi/rlwimi/rlwnm (PR #82968)
@@ -1,61 +1,111 @@
-; All of these ands and shifts should be folded into rlwimi's
-; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -o %t
-; RUN: not grep and %t
-; RUN: not grep srawi %t
-; RUN: not grep srwi %t
-; RUN: not grep slwi %t
-; RUN: grep rlwinm %t | count 8
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu |
FileCheck %s
define i32 @test1(i32 %a) {
+; CHECK-LABEL: test1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:rlwinm 3, 3, 0, 4, 19
+; CHECK-NEXT:blr
entry:
- %tmp.1 = and i32 %a, 268431360 ; [#uses=1]
- ret i32 %tmp.1
+ %tmp.1 = and i32 %a, 268431360
+ ret i32 %tmp.1
}
define i32 @test2(i32 %a) {
+; CHECK-LABEL: test2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:rldicl 3, 3, 36, 24
+; CHECK-NEXT:rldicl 3, 3, 28, 32
chenzheng1030 wrote:
After the triple change, now two `rldicl` are emitted instead of a single
`rlwinm`. Would you please help to add a FIXME here? or create an issue in
github? Thanks.
https://github.com/llvm/llvm-project/pull/82968
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[clang] [llvm] [PowerPC] Add intrinsics for rldimi/rlwimi/rlwnm (PR #82968)
@@ -1,70 +1,117 @@
-; All of these ands and shifts should be folded into rlwimi's
-; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep and
-; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep rlwimi | count 8
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu |
FileCheck %s
define i32 @test1(i32 %x, i32 %y) {
+; CHECK-LABEL: test1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:rlwimi 4, 3, 16, 0, 15
+; CHECK-NEXT:mr 3, 4
+; CHECK-NEXT:blr
entry:
- %tmp.3 = shl i32 %x, 16 ; [#uses=1]
- %tmp.7 = and i32 %y, 65535 ; [#uses=1]
- %tmp.9 = or i32 %tmp.7, %tmp.3 ; [#uses=1]
- ret i32 %tmp.9
+ %tmp.3 = shl i32 %x, 16
+ %tmp.7 = and i32 %y, 65535
+ %tmp.9 = or i32 %tmp.7, %tmp.3
+ ret i32 %tmp.9
}
define i32 @test2(i32 %x, i32 %y) {
+; CHECK-LABEL: test2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:rlwimi 3, 4, 16, 0, 15
+; CHECK-NEXT:blr
entry:
- %tmp.7 = and i32 %x, 65535 ; [#uses=1]
- %tmp.3 = shl i32 %y, 16 ; [#uses=1]
- %tmp.9 = or i32 %tmp.7, %tmp.3 ; [#uses=1]
- ret i32 %tmp.9
+ %tmp.7 = and i32 %x, 65535
+ %tmp.3 = shl i32 %y, 16
+ %tmp.9 = or i32 %tmp.7, %tmp.3
+ ret i32 %tmp.9
}
define i32 @test3(i32 %x, i32 %y) {
+; CHECK-LABEL: test3:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:rlwimi 4, 3, 16, 16, 31
+; CHECK-NEXT:mr 3, 4
+; CHECK-NEXT:blr
entry:
- %tmp.3 = lshr i32 %x, 16; [#uses=1]
- %tmp.6 = and i32 %y, -65536 ; [#uses=1]
- %tmp.7 = or i32 %tmp.6, %tmp.3 ; [#uses=1]
- ret i32 %tmp.7
+ %tmp.3 = lshr i32 %x, 16
+ %tmp.6 = and i32 %y, -65536
+ %tmp.7 = or i32 %tmp.6, %tmp.3
+ ret i32 %tmp.7
}
define i32 @test4(i32 %x, i32 %y) {
+; CHECK-LABEL: test4:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:rlwimi 3, 4, 16, 16, 31
+; CHECK-NEXT:blr
entry:
- %tmp.6 = and i32 %x, -65536 ; [#uses=1]
- %tmp.3 = lshr i32 %y, 16; [#uses=1]
- %tmp.7 = or i32 %tmp.6, %tmp.3 ; [#uses=1]
- ret i32 %tmp.7
+ %tmp.6 = and i32 %x, -65536
+ %tmp.3 = lshr i32 %y, 16
+ %tmp.7 = or i32 %tmp.6, %tmp.3
+ ret i32 %tmp.7
}
define i32 @test5(i32 %x, i32 %y) {
+; CHECK-LABEL: test5:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:rlwimi 4, 3, 1, 0, 15
+; CHECK-NEXT:mr 3, 4
+; CHECK-NEXT:blr
entry:
- %tmp.3 = shl i32 %x, 1 ; [#uses=1]
- %tmp.4 = and i32 %tmp.3, -65536 ; [#uses=1]
- %tmp.7 = and i32 %y, 65535 ; [#uses=1]
- %tmp.9 = or i32 %tmp.4, %tmp.7 ; [#uses=1]
- ret i32 %tmp.9
+ %tmp.3 = shl i32 %x, 1
+ %tmp.4 = and i32 %tmp.3, -65536
+ %tmp.7 = and i32 %y, 65535
+ %tmp.9 = or i32 %tmp.4, %tmp.7
+ ret i32 %tmp.9
}
define i32 @test6(i32 %x, i32 %y) {
+; CHECK-LABEL: test6:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:rlwimi 3, 4, 1, 0, 15
+; CHECK-NEXT:blr
entry:
- %tmp.7 = and i32 %x, 65535 ; [#uses=1]
- %tmp.3 = shl i32 %y, 1 ; [#uses=1]
- %tmp.4 = and i32 %tmp.3, -65536 ; [#uses=1]
- %tmp.9 = or i32 %tmp.4, %tmp.7 ; [#uses=1]
- ret i32 %tmp.9
+ %tmp.7 = and i32 %x, 65535
+ %tmp.3 = shl i32 %y, 1
+ %tmp.4 = and i32 %tmp.3, -65536
+ %tmp.9 = or i32 %tmp.4, %tmp.7
+ ret i32 %tmp.9
}
define i32 @test7(i32 %x, i32 %y) {
+; CHECK-LABEL: test7:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:andis. 3, 3, 65535
+; CHECK-NEXT:rldimi 3, 4, 0, 48
+; CHECK-NEXT:blr
entry:
- %tmp.2 = and i32 %x, -65536 ; [#uses=1]
- %tmp.5 = and i32 %y, 65535 ; [#uses=1]
- %tmp.7 = or i32 %tmp.5, %tmp.2 ; [#uses=1]
- ret i32 %tmp.7
+ %tmp.2 = and i32 %x, -65536
+ %tmp.5 = and i32 %y, 65535
+ %tmp.7 = or i32 %tmp.5, %tmp.2
+ ret i32 %tmp.7
}
define i32 @test8(i32 %bar) {
+; CHECK-LABEL: test8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:rlwimi 3, 3, 1, 30, 30
+; CHECK-NEXT:blr
entry:
- %tmp.3 = shl i32 %bar, 1; [#uses=1]
- %tmp.4 = and i32 %tmp.3, 2 ; [#uses=1]
- %tmp.6 = and i32 %bar, -3 ; [#uses=1]
- %tmp.7 = or i32 %tmp.4, %tmp.6 ; [#uses=1]
- ret i32 %tmp.7
+ %tmp.3 = shl i32 %bar, 1
+ %tmp.4 = and i32 %tmp.3, 2
+ %tmp.6 = and i32 %bar, -3
+ %tmp.7 = or i32 %tmp.4, %tmp.6
+ ret i32 %tmp.7
}
+
+define i32 @test9(i32 %a, i32 %b) {
+; CHECK-LABEL: test9:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:rlwimi 3, 4, 8, 20, 26
+; CHECK-NEXT:blr
+entry:
+ %r = call i32 @llvm.ppc.rlwimi(i32 %a, i32 %b, i32 8, i32 4064)
+ ret i32 %r
+}
+
+declare i32 @llvm.ppc.rlwimi(i32, i32, i32 immarg, i32 i
[clang] [llvm] [PowerPC] Add intrinsics for rldimi/rlwimi/rlwnm (PR #82968)
chenzheng1030 wrote: The failure in the buildkite should be unrelated. But would be better to double confirm. https://github.com/llvm/llvm-project/pull/82968 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PowerPC] Add intrinsics for rldimi/rlwimi/rlwnm (PR #82968)
@@ -1,61 +1,111 @@
-; All of these ands and shifts should be folded into rlwimi's
-; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -o %t
-; RUN: not grep and %t
-; RUN: not grep srawi %t
-; RUN: not grep srwi %t
-; RUN: not grep slwi %t
-; RUN: grep rlwinm %t | count 8
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu |
FileCheck %s
define i32 @test1(i32 %a) {
+; CHECK-LABEL: test1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:rlwinm 3, 3, 0, 4, 19
+; CHECK-NEXT:blr
entry:
- %tmp.1 = and i32 %a, 268431360 ; [#uses=1]
- ret i32 %tmp.1
+ %tmp.1 = and i32 %a, 268431360
+ ret i32 %tmp.1
}
define i32 @test2(i32 %a) {
+; CHECK-LABEL: test2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:rldicl 3, 3, 36, 24
+; CHECK-NEXT:rldicl 3, 3, 28, 32
chenzheng1030 wrote:
hmm, OK. The `rlwinm` does not match the 64-bit semantic here. Would you please
just remove this case. It would be strange to keep it in the rlwinm file now.
Please don't treat rlwinm as a 32-bit instruction. It alters and well defined
the high 32 bit of a GPR as well especially the MB/ME are wrapped.
https://github.com/llvm/llvm-project/pull/82968
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[clang] [llvm] [PowerPC] Add intrinsics for rldimi/rlwimi/rlwnm (PR #82968)
@@ -58,3 +58,18 @@ entry:
%8 = or i64 %6, %7
ret i64 %8
}
+
+define i64 @rldimi_intrinsic(i64 %a) {
+; CHECK-LABEL: rldimi_intrinsic:
+; CHECK: # %bb.0:
+; CHECK-NEXT:rldimi 3, 3, 8, 0
+; CHECK-NEXT:rldimi 3, 3, 16, 0
+; CHECK-NEXT:rldimi 3, 3, 32, 0
+; CHECK-NEXT:blr
+ %r1 = call i64 @llvm.ppc.rldimi(i64 %a, i64 %a, i32 8, i64 -256)
+ %r2 = call i64 @llvm.ppc.rldimi(i64 %r1, i64 %r1, i32 16, i64 -65536)
+ %r3 = call i64 @llvm.ppc.rldimi(i64 %r2, i64 %r2, i32 32, i64 -4294967296)
+ ret i64 %r3
+}
+
+declare i64 @llvm.ppc.rldimi(i64, i64, i32 immarg, i64 immarg)
chenzheng1030 wrote:
OK. Thanks. TIL : )
https://github.com/llvm/llvm-project/pull/82968
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[clang] [PowerPC] Diagnose invalid combination with Altivec, VSX and soft-float (PR #79109)
https://github.com/chenzheng1030 updated
https://github.com/llvm/llvm-project/pull/79109
>From 014b10f43e2d3f8564940e21033cee77c3c0c10e Mon Sep 17 00:00:00 2001
From: Nemanja Ivanovic
Date: Tue, 23 Jan 2024 03:25:01 -0500
Subject: [PATCH 1/2] [PowerPC] Diagnose invalid combination with Altivec, VSX
and soft-float
---
clang/lib/Basic/Targets/PPC.cpp | 43
clang/test/CodeGen/PowerPC/attr-target-ppc.c | 3 ++
clang/test/Driver/ppc-dependent-options.cpp | 15 +++
3 files changed, 52 insertions(+), 9 deletions(-)
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 41935abfb65d3b..1341bf8b99c506 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -442,19 +442,44 @@ void PPCTargetInfo::getTargetDefines(const LangOptions
&Opts,
// _CALL_DARWIN
}
-// Handle explicit options being passed to the compiler here: if we've
-// explicitly turned off vsx and turned on any of:
-// - power8-vector
-// - direct-move
-// - float128
-// - power9-vector
-// - paired-vector-memops
-// - mma
-// - power10-vector
+// Handle explicit options being passed to the compiler here:
+// - if we've explicitly turned off vsx and turned on any of:
+// - power8-vector
+// - direct-move
+// - float128
+// - power9-vector
+// - paired-vector-memops
+// - mma
+// - power10-vector
+// - if we've explicitly turned on vsx and turned off altivec.
+// - if we've explicitly turned on soft-float and altivec.
// then go ahead and error since the customer has expressed an incompatible
// set of options.
static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
const std::vector &FeaturesVec) {
+ // Cannot allow soft-float with Altivec.
+ if (llvm::is_contained(FeaturesVec, "-hard-float") &&
+ llvm::is_contained(FeaturesVec, "+altivec")) {
+Diags.Report(diag::err_opt_not_valid_with_opt) << "-msoft-float"
+ << "-maltivec";
+return false;
+ }
+
+ // Cannot allow soft-float with VSX.
+ if (llvm::is_contained(FeaturesVec, "-hard-float") &&
+ llvm::is_contained(FeaturesVec, "+vsx")) {
+Diags.Report(diag::err_opt_not_valid_with_opt) << "-msoft-float"
+ << "-mvsx";
+return false;
+ }
+
+ // Cannot allow VSX with no Altivec.
+ if (llvm::is_contained(FeaturesVec, "+vsx") &&
+ llvm::is_contained(FeaturesVec, "-altivec")) {
+Diags.Report(diag::err_opt_not_valid_with_opt) << "-mvsx"
+ << "-mno-altivec";
+return false;
+ }
// vsx was not explicitly turned off.
if (!llvm::is_contained(FeaturesVec, "-vsx"))
diff --git a/clang/test/CodeGen/PowerPC/attr-target-ppc.c
b/clang/test/CodeGen/PowerPC/attr-target-ppc.c
index d2901748b37cb9..f185a0e6f49a05 100644
--- a/clang/test/CodeGen/PowerPC/attr-target-ppc.c
+++ b/clang/test/CodeGen/PowerPC/attr-target-ppc.c
@@ -1,4 +1,7 @@
// RUN: not %clang_cc1 -triple powerpc64le-linux-gnu -emit-llvm %s -o -
long __attribute__((target("power8-vector,no-vsx"))) foo (void) { return 0; }
// expected-error {{option '-mpower8-vector' cannot be specified with
'-mno-vsx'}}
+long __attribute__((target("no-altivec,vsx"))) foo2(void) { return 0; }
// expected-error {{option '-mvsx' cannot be specified with '-mno-altivec'}}
+long __attribute__((target("no-hard-float,altivec"))) foo3(void) { return 0; }
// expected-error {{option '-msoft-float' cannot be specified with '-maltivec'}}
+long __attribute__((target("no-hard-float,vsx"))) foo3(void) { return 0; } //
expected-error {{option '-msoft-float' cannot be specified with '-mvsx'}}
diff --git a/clang/test/Driver/ppc-dependent-options.cpp
b/clang/test/Driver/ppc-dependent-options.cpp
index 65c40e9ce70f65..8286422185cad6 100644
--- a/clang/test/Driver/ppc-dependent-options.cpp
+++ b/clang/test/Driver/ppc-dependent-options.cpp
@@ -78,6 +78,18 @@
// RUN: -mcpu=power10 -std=c++11 -mno-vsx -mpower10-vector %s 2>&1 | \
// RUN: FileCheck %s -check-prefix=CHECK-NVSX-P10V
+// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \
+// RUN: -std=c++11 -mvsx -mno-altivec %s 2>&1 | \
+// RUN: FileCheck %s -check-prefix=CHECK-NALTI-VSX
+
+// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \
+// RUN: -std=c++11 -msoft-float -maltivec %s 2>&1 | \
+// RUN: FileCheck %s -check-prefix=CHECK-SOFTFLT-ALTI
+
+// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \
+// RUN: -std=c++11 -msoft-float -mvsx %s 2>&1 | \
+// RUN: FileCheck %s -check-prefix=CHECK-SOFTFLT-VSX
+
#ifdef __VSX__
static_assert(false, "VSX enabled");
#endif
@@ -114,3 +126,6 @@ static_assert(false, "Neither enabled");
// CHECK-NVSX-MMA: error: option '-mmma' cannot be specified with '-mno-vsx'
// CHECK-NVSX: Neither enabled
// CHECK-VSX: VSX enabled
+// CHECK-NALTI-VSX: error: option '-mvsx' cannot be sp
[clang] [PowerPC] Diagnose invalid combination with Altivec, VSX and soft-float (PR #79109)
chenzheng1030 wrote: Patch updated. https://github.com/llvm/llvm-project/pull/79109 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [PowerPC] Diagnose invalid combination with Altivec, VSX and soft-float (PR #79109)
chenzheng1030 wrote: > I don't have any further comments, so I think LGTM. Thanks Amy. https://github.com/llvm/llvm-project/pull/79109 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [PowerPC] Diagnose invalid combination with Altivec, VSX and soft-float (PR #79109)
https://github.com/chenzheng1030 closed https://github.com/llvm/llvm-project/pull/79109 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [PowerPC] Diagnose invalid combination with Altivec, VSX and soft-float (PR #79109)
https://github.com/chenzheng1030 created
https://github.com/llvm/llvm-project/pull/79109
Moved from https://reviews.llvm.org/D126302
The current behaviour with these three options is quite undesirable:
-mno-altivec -mvsx allows VSX to override no Altivec, thereby turning on both
-msoft-float -maltivec causes a crash if an actual Altivec instruction is
required because soft float turns of Altivec
-msoft-float -mvsx is also accepted with both Altivec and VSX turned off
(potentially causing crashes as above)
This patch diagnoses these impossible combinations in the driver so the user
does not end up with surprises in terms of their options being ignored or
silently overridden.
Fixes https://github.com/llvm/llvm-project/issues/6
>From 014b10f43e2d3f8564940e21033cee77c3c0c10e Mon Sep 17 00:00:00 2001
From: Nemanja Ivanovic
Date: Tue, 23 Jan 2024 03:25:01 -0500
Subject: [PATCH] [PowerPC] Diagnose invalid combination with Altivec, VSX and
soft-float
---
clang/lib/Basic/Targets/PPC.cpp | 43
clang/test/CodeGen/PowerPC/attr-target-ppc.c | 3 ++
clang/test/Driver/ppc-dependent-options.cpp | 15 +++
3 files changed, 52 insertions(+), 9 deletions(-)
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 41935abfb65d3b..1341bf8b99c506 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -442,19 +442,44 @@ void PPCTargetInfo::getTargetDefines(const LangOptions
&Opts,
// _CALL_DARWIN
}
-// Handle explicit options being passed to the compiler here: if we've
-// explicitly turned off vsx and turned on any of:
-// - power8-vector
-// - direct-move
-// - float128
-// - power9-vector
-// - paired-vector-memops
-// - mma
-// - power10-vector
+// Handle explicit options being passed to the compiler here:
+// - if we've explicitly turned off vsx and turned on any of:
+// - power8-vector
+// - direct-move
+// - float128
+// - power9-vector
+// - paired-vector-memops
+// - mma
+// - power10-vector
+// - if we've explicitly turned on vsx and turned off altivec.
+// - if we've explicitly turned on soft-float and altivec.
// then go ahead and error since the customer has expressed an incompatible
// set of options.
static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
const std::vector &FeaturesVec) {
+ // Cannot allow soft-float with Altivec.
+ if (llvm::is_contained(FeaturesVec, "-hard-float") &&
+ llvm::is_contained(FeaturesVec, "+altivec")) {
+Diags.Report(diag::err_opt_not_valid_with_opt) << "-msoft-float"
+ << "-maltivec";
+return false;
+ }
+
+ // Cannot allow soft-float with VSX.
+ if (llvm::is_contained(FeaturesVec, "-hard-float") &&
+ llvm::is_contained(FeaturesVec, "+vsx")) {
+Diags.Report(diag::err_opt_not_valid_with_opt) << "-msoft-float"
+ << "-mvsx";
+return false;
+ }
+
+ // Cannot allow VSX with no Altivec.
+ if (llvm::is_contained(FeaturesVec, "+vsx") &&
+ llvm::is_contained(FeaturesVec, "-altivec")) {
+Diags.Report(diag::err_opt_not_valid_with_opt) << "-mvsx"
+ << "-mno-altivec";
+return false;
+ }
// vsx was not explicitly turned off.
if (!llvm::is_contained(FeaturesVec, "-vsx"))
diff --git a/clang/test/CodeGen/PowerPC/attr-target-ppc.c
b/clang/test/CodeGen/PowerPC/attr-target-ppc.c
index d2901748b37cb9..f185a0e6f49a05 100644
--- a/clang/test/CodeGen/PowerPC/attr-target-ppc.c
+++ b/clang/test/CodeGen/PowerPC/attr-target-ppc.c
@@ -1,4 +1,7 @@
// RUN: not %clang_cc1 -triple powerpc64le-linux-gnu -emit-llvm %s -o -
long __attribute__((target("power8-vector,no-vsx"))) foo (void) { return 0; }
// expected-error {{option '-mpower8-vector' cannot be specified with
'-mno-vsx'}}
+long __attribute__((target("no-altivec,vsx"))) foo2(void) { return 0; }
// expected-error {{option '-mvsx' cannot be specified with '-mno-altivec'}}
+long __attribute__((target("no-hard-float,altivec"))) foo3(void) { return 0; }
// expected-error {{option '-msoft-float' cannot be specified with '-maltivec'}}
+long __attribute__((target("no-hard-float,vsx"))) foo3(void) { return 0; } //
expected-error {{option '-msoft-float' cannot be specified with '-mvsx'}}
diff --git a/clang/test/Driver/ppc-dependent-options.cpp
b/clang/test/Driver/ppc-dependent-options.cpp
index 65c40e9ce70f65..8286422185cad6 100644
--- a/clang/test/Driver/ppc-dependent-options.cpp
+++ b/clang/test/Driver/ppc-dependent-options.cpp
@@ -78,6 +78,18 @@
// RUN: -mcpu=power10 -std=c++11 -mno-vsx -mpower10-vector %s 2>&1 | \
// RUN: FileCheck %s -check-prefix=CHECK-NVSX-P10V
+// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \
+// RUN: -std=c++11 -mvsx -mno-altivec %s 2>&1 | \
+// RUN: FileCheck %s -check-prefix=CHECK-NALTI-VSX
+
+// RUN: not %clang -tar
[clang] [PowerPC] Add an alias for -mregnames so that full register names used in assembly. (PR #70255)
@@ -80,6 +80,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public
TargetInfo {
bool IsISA3_0 = false;
bool IsISA3_1 = false;
bool HasQuadwordAtomics = false;
+ bool FullRegisterNames = false;
chenzheng1030 wrote:
Using a target feature bit for assembly printing seems not match other bits.
IIUC, all the bits here should control the available instructions on a
subtarget.
Could we use an option in `TargetMachine::Options::MCOptions`? this looks like
the way where clang can accept an option and control the code generation in the
backend. The current option `Options.MCOptions.PreserveAsmComments` seems a
little similar with this functionality.
https://github.com/llvm/llvm-project/pull/70255
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[clang] a0ca4c4 - [Debug-Info] add -gstrict-dwarf support in backend
Author: Chen Zheng
Date: 2021-05-12T23:00:52-04:00
New Revision: a0ca4c46ca35957a38a6023fa84afda2fc9ba0ec
URL:
https://github.com/llvm/llvm-project/commit/a0ca4c46ca35957a38a6023fa84afda2fc9ba0ec
DIFF:
https://github.com/llvm/llvm-project/commit/a0ca4c46ca35957a38a6023fa84afda2fc9ba0ec.diff
LOG: [Debug-Info] add -gstrict-dwarf support in backend
Reviewed By: dblaikie, probinson
Differential Revision: https://reviews.llvm.org/D100826
Added:
llvm/test/DebugInfo/PowerPC/strict-dwarf.ll
Modified:
clang/lib/CodeGen/BackendUtil.cpp
llvm/include/llvm/CodeGen/CommandFlags.h
llvm/include/llvm/Target/TargetOptions.h
llvm/lib/CodeGen/CommandFlags.cpp
Removed:
diff --git a/clang/lib/CodeGen/BackendUtil.cpp
b/clang/lib/CodeGen/BackendUtil.cpp
index 2be0b1a3280d..e2799f6aba4c 100644
--- a/clang/lib/CodeGen/BackendUtil.cpp
+++ b/clang/lib/CodeGen/BackendUtil.cpp
@@ -598,6 +598,7 @@ static bool initTargetOptions(DiagnosticsEngine &Diags,
Entry.IgnoreSysRoot ? Entry.Path : HSOpts.Sysroot + Entry.Path);
Options.MCOptions.Argv0 = CodeGenOpts.Argv0;
Options.MCOptions.CommandLineArgs = CodeGenOpts.CommandLineArgs;
+ Options.DebugStrictDwarf = CodeGenOpts.DebugStrictDwarf;
return true;
}
diff --git a/llvm/include/llvm/CodeGen/CommandFlags.h
b/llvm/include/llvm/CodeGen/CommandFlags.h
index a12733801213..f4555c34585e 100644
--- a/llvm/include/llvm/CodeGen/CommandFlags.h
+++ b/llvm/include/llvm/CodeGen/CommandFlags.h
@@ -140,6 +140,8 @@ bool getForceDwarfFrameSection();
bool getXRayOmitFunctionIndex();
+bool getDebugStrictDwarf();
+
/// Create this object with static storage to register codegen-related command
/// line options.
struct RegisterCodeGenFlags {
diff --git a/llvm/include/llvm/Target/TargetOptions.h
b/llvm/include/llvm/Target/TargetOptions.h
index cad356edacec..09c8cf59f4ab 100644
--- a/llvm/include/llvm/Target/TargetOptions.h
+++ b/llvm/include/llvm/Target/TargetOptions.h
@@ -137,6 +137,7 @@ namespace llvm {
SupportsDebugEntryValues(false), EnableDebugEntryValues(false),
PseudoProbeForProfiling(false),
ValueTrackingVariableLocations(false),
ForceDwarfFrameSection(false), XRayOmitFunctionIndex(false),
+ DebugStrictDwarf(false),
FPDenormalMode(DenormalMode::IEEE, DenormalMode::IEEE) {}
/// DisableFramePointerElim - This returns true if frame pointer
elimination
@@ -327,6 +328,10 @@ namespace llvm {
/// Emit XRay Function Index section
unsigned XRayOmitFunctionIndex : 1;
+/// When set to true, don't use DWARF extensions in later DWARF versions.
+/// By default, it is set to false.
+unsigned DebugStrictDwarf : 1;
+
/// Stack protector guard offset to use.
int StackProtectorGuardOffset = INT_MAX;
diff --git a/llvm/lib/CodeGen/CommandFlags.cpp
b/llvm/lib/CodeGen/CommandFlags.cpp
index 4c6c5950117f..b8f1ca154f6c 100644
--- a/llvm/lib/CodeGen/CommandFlags.cpp
+++ b/llvm/lib/CodeGen/CommandFlags.cpp
@@ -97,6 +97,7 @@ CGOPT(bool, PseudoProbeForProfiling)
CGOPT(bool, ValueTrackingVariableLocations)
CGOPT(bool, ForceDwarfFrameSection)
CGOPT(bool, XRayOmitFunctionIndex)
+CGOPT(bool, DebugStrictDwarf)
codegen::RegisterCodeGenFlags::RegisterCodeGenFlags() {
#define CGBINDOPT(NAME)
\
@@ -471,6 +472,10 @@ codegen::RegisterCodeGenFlags::RegisterCodeGenFlags() {
cl::init(false));
CGBINDOPT(XRayOmitFunctionIndex);
+ static cl::opt DebugStrictDwarf(
+ "strict-dwarf", cl::desc("use strict dwarf"), cl::init(false));
+ CGBINDOPT(DebugStrictDwarf);
+
#undef CGBINDOPT
mc::RegisterMCTargetOptionsFlags();
@@ -567,6 +572,7 @@ codegen::InitTargetOptionsFromCodeGenFlags(const Triple
&TheTriple) {
Options.ValueTrackingVariableLocations = getValueTrackingVariableLocations();
Options.ForceDwarfFrameSection = getForceDwarfFrameSection();
Options.XRayOmitFunctionIndex = getXRayOmitFunctionIndex();
+ Options.DebugStrictDwarf = getDebugStrictDwarf();
Options.MCOptions = mc::InitMCTargetOptionsFromFlags();
diff --git a/llvm/test/DebugInfo/PowerPC/strict-dwarf.ll
b/llvm/test/DebugInfo/PowerPC/strict-dwarf.ll
new file mode 100644
index ..b64fd426e8ea
--- /dev/null
+++ b/llvm/test/DebugInfo/PowerPC/strict-dwarf.ll
@@ -0,0 +1,60 @@
+; RUN: llc -filetype=obj -mtriple=powerpc64le-unknown-linux-gnu < %s | \
+; RUN: llvm-dwarfdump -debug-info - | FileCheck %s
+; RUN: llc -filetype=obj -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -strict-dwarf=true < %s | llvm-dwarfdump -debug-info - | \
+; RUN: FileCheck %s
+
+; FIXME: when -strict-dwarf=true is specified, we should check "STRICT" to tell
+; that with DWARF 4, we should not generate DWARF 5 attribute DW_AT_noreturn
and
+; DW_AT_alignment.
+
+; CHECK: DW_AT_alignment
+; CHECK: DW_AT_noreturn
+; STRICT-NOT: DW_AT_noreturn
+; STRIC
[clang] 99d45ed - [Debug-Info] handle DW_TAG_rvalue_reference_type at strict DWARF.
Author: Chen Zheng
Date: 2021-05-23T21:24:13-04:00
New Revision: 99d45ed22fd9c08ae81110956a817ac0eacded2e
URL:
https://github.com/llvm/llvm-project/commit/99d45ed22fd9c08ae81110956a817ac0eacded2e
DIFF:
https://github.com/llvm/llvm-project/commit/99d45ed22fd9c08ae81110956a817ac0eacded2e.diff
LOG: [Debug-Info] handle DW_TAG_rvalue_reference_type at strict DWARF.
When -gstrict-dwarf is specified, generate DW_TAG_rvalue_reference_type
at DWARF 4 or above
Reviewed By: dblaikie, aprantl
Differential Revision: https://reviews.llvm.org/D100630
Added:
Modified:
clang/lib/CodeGen/CGDebugInfo.cpp
clang/test/CodeGenCXX/debug-info-rvalue-ref.cpp
Removed:
diff --git a/clang/lib/CodeGen/CGDebugInfo.cpp
b/clang/lib/CodeGen/CGDebugInfo.cpp
index fefcf7a4e973..e8c310e0c060 100644
--- a/clang/lib/CodeGen/CGDebugInfo.cpp
+++ b/clang/lib/CodeGen/CGDebugInfo.cpp
@@ -2989,8 +2989,13 @@ llvm::DIType *CGDebugInfo::CreateType(const
LValueReferenceType *Ty,
llvm::DIType *CGDebugInfo::CreateType(const RValueReferenceType *Ty,
llvm::DIFile *Unit) {
- return CreatePointerLikeType(llvm::dwarf::DW_TAG_rvalue_reference_type, Ty,
- Ty->getPointeeType(), Unit);
+ llvm::dwarf::Tag Tag = llvm::dwarf::DW_TAG_rvalue_reference_type;
+ // DW_TAG_rvalue_reference_type was introduced in DWARF 4.
+ if (CGM.getCodeGenOpts().DebugStrictDwarf &&
+ CGM.getCodeGenOpts().DwarfVersion < 4)
+Tag = llvm::dwarf::DW_TAG_reference_type;
+
+ return CreatePointerLikeType(Tag, Ty, Ty->getPointeeType(), Unit);
}
llvm::DIType *CGDebugInfo::CreateType(const MemberPointerType *Ty,
diff --git a/clang/test/CodeGenCXX/debug-info-rvalue-ref.cpp
b/clang/test/CodeGenCXX/debug-info-rvalue-ref.cpp
index de0f65ad9a02..c9500ee59b7f 100644
--- a/clang/test/CodeGenCXX/debug-info-rvalue-ref.cpp
+++ b/clang/test/CodeGenCXX/debug-info-rvalue-ref.cpp
@@ -1,4 +1,8 @@
// RUN: %clang_cc1 -std=c++11 -emit-llvm -debug-info-kind=limited -triple
x86_64-apple-darwin %s -o - | FileCheck %s
+// RUN: %clang_cc1 -std=c++11 -dwarf-version=4 -gstrict-dwarf -emit-llvm
-debug-info-kind=limited \
+// RUN: -triple x86_64-apple-darwin %s -o - | FileCheck %s
+// RUN: %clang_cc1 -std=c++11 -dwarf-version=3 -gstrict-dwarf -emit-llvm
-debug-info-kind=limited \
+// RUN: -triple x86_64-apple-darwin %s -o - | FileCheck %s
--check-prefix=NORVALUE
extern "C" {
extern int printf(const char * format, ...);
@@ -10,3 +14,4 @@ void foo (int &&i)
// CHECK: !DIDerivedType(tag: DW_TAG_rvalue_reference_type, baseType:
![[INT:[0-9]+]], size: 64)
// CHECK: ![[INT]] = !DIBasicType(name: "int"
+// NORVALUE: !DIDerivedType(tag: DW_TAG_reference_type, baseType:
![[INT:[0-9]+]], size: 64)
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[clang] 4590b40 - [Debug-Info] guard DW_LANG_C_plus_plus_14 under strict dwarf
Author: Chen Zheng
Date: 2021-06-16T03:17:56Z
New Revision: 4590b406c02e4e6803d2644195dbb78bc09c25c7
URL:
https://github.com/llvm/llvm-project/commit/4590b406c02e4e6803d2644195dbb78bc09c25c7
DIFF:
https://github.com/llvm/llvm-project/commit/4590b406c02e4e6803d2644195dbb78bc09c25c7.diff
LOG: [Debug-Info] guard DW_LANG_C_plus_plus_14 under strict dwarf
Reviewed By: stuart
Differential Revision: https://reviews.llvm.org/D104291
Added:
Modified:
clang/lib/CodeGen/CGDebugInfo.cpp
clang/test/CodeGenCXX/debug-info-programming-language.cpp
Removed:
diff --git a/clang/lib/CodeGen/CGDebugInfo.cpp
b/clang/lib/CodeGen/CGDebugInfo.cpp
index 080d494a28306..08d15bef93800 100644
--- a/clang/lib/CodeGen/CGDebugInfo.cpp
+++ b/clang/lib/CodeGen/CGDebugInfo.cpp
@@ -568,9 +568,11 @@ void CGDebugInfo::CreateCompileUnit() {
if (LO.CPlusPlus) {
if (LO.ObjC)
LangTag = llvm::dwarf::DW_LANG_ObjC_plus_plus;
-else if (LO.CPlusPlus14 && CGM.getCodeGenOpts().DwarfVersion >= 5)
+else if (LO.CPlusPlus14 && (!CGM.getCodeGenOpts().DebugStrictDwarf ||
+CGM.getCodeGenOpts().DwarfVersion >= 5))
LangTag = llvm::dwarf::DW_LANG_C_plus_plus_14;
-else if (LO.CPlusPlus11 && CGM.getCodeGenOpts().DwarfVersion >= 5)
+else if (LO.CPlusPlus11 && (!CGM.getCodeGenOpts().DebugStrictDwarf ||
+CGM.getCodeGenOpts().DwarfVersion >= 5))
LangTag = llvm::dwarf::DW_LANG_C_plus_plus_11;
else
LangTag = llvm::dwarf::DW_LANG_C_plus_plus;
diff --git a/clang/test/CodeGenCXX/debug-info-programming-language.cpp
b/clang/test/CodeGenCXX/debug-info-programming-language.cpp
index 82a6db6445f36..06873a7b5752a 100644
--- a/clang/test/CodeGenCXX/debug-info-programming-language.cpp
+++ b/clang/test/CodeGenCXX/debug-info-programming-language.cpp
@@ -1,13 +1,18 @@
-// RUN: %clang_cc1 -dwarf-version=5 -emit-llvm -triple %itanium_abi_triple %s
-o - \
+// RUN: %clang_cc1 -dwarf-version=5 -emit-llvm -triple %itanium_abi_triple %s
-o - \
// RUN: -x c++ -std=c++14 -O0 -disable-llvm-passes -debug-info-kind=limited \
-// RUN: | FileCheck --check-prefix=CHECK-DWARF5 %s
-// RUN: %clang_cc1 -dwarf-version=3 -emit-llvm -triple %itanium_abi_triple %s
-o - \
+// RUN: | FileCheck --check-prefix=CHECK-CPP14 %s
+// RUN: %clang_cc1 -dwarf-version=3 -emit-llvm -triple %itanium_abi_triple %s
-o - \
// RUN: -x c++ -std=c++14 -O0 -disable-llvm-passes -debug-info-kind=limited \
-// RUN: | FileCheck --check-prefix=CHECK-DWARF3 %s
+// RUN: | FileCheck --check-prefix=CHECK-CPP14 %s
+// RUN: %clang_cc1 -dwarf-version=3 -gstrict-dwarf -emit-llvm -triple
%itanium_abi_triple %s -o - \
+// RUN: -x c++ -std=c++14 -O0 -disable-llvm-passes -debug-info-kind=limited
| FileCheck %s
+// RUN: %clang_cc1 -dwarf-version=5 -gstrict-dwarf -emit-llvm -triple
%itanium_abi_triple %s -o - \
+// RUN: -x c++ -std=c++14 -O0 -disable-llvm-passes -debug-info-kind=limited \
+// RUN: | FileCheck --check-prefix=CHECK-CPP14 %s
int main() {
return 0;
}
-// CHECK-DWARF5: distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14,
-// CHECK-DWARF3: distinct !DICompileUnit(language: DW_LANG_C_plus_plus,
+// CHECK-CPP14: distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14,
+// CHECK: distinct !DICompileUnit(language: DW_LANG_C_plus_plus,
___
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[clang] afa76fe - [XCOFF][DWARF] set default DWARF version to 3.
Author: Chen Zheng
Date: 2021-03-05T09:21:57-05:00
New Revision: afa76fe67a42f6d40d83a4f7d0cb03373045f3f4
URL:
https://github.com/llvm/llvm-project/commit/afa76fe67a42f6d40d83a4f7d0cb03373045f3f4
DIFF:
https://github.com/llvm/llvm-project/commit/afa76fe67a42f6d40d83a4f7d0cb03373045f3f4.diff
LOG: [XCOFF][DWARF] set default DWARF version to 3.
Reviewed By: jsji
Differential Revision: https://reviews.llvm.org/D98010
Added:
Modified:
clang/lib/Driver/ToolChains/AIX.h
clang/test/CodeGen/dwarf-version.c
Removed:
diff --git a/clang/lib/Driver/ToolChains/AIX.h
b/clang/lib/Driver/ToolChains/AIX.h
index d4e593255736..c6aac09ddfac 100644
--- a/clang/lib/Driver/ToolChains/AIX.h
+++ b/clang/lib/Driver/ToolChains/AIX.h
@@ -74,6 +74,9 @@ class LLVM_LIBRARY_VISIBILITY AIX : public ToolChain {
RuntimeLibType GetDefaultRuntimeLibType() const override;
+ // Set default DWARF version to 3 for now as latest AIX OS supports version
3.
+ unsigned GetDefaultDwarfVersion() const override { return 3; }
+
protected:
Tool *buildAssembler() const override;
Tool *buildLinker() const override;
diff --git a/clang/test/CodeGen/dwarf-version.c
b/clang/test/CodeGen/dwarf-version.c
index 87143ee13118..6d131c470d5b 100644
--- a/clang/test/CodeGen/dwarf-version.c
+++ b/clang/test/CodeGen/dwarf-version.c
@@ -32,6 +32,17 @@
// Explicitly request both.
// RUN: %clang -target i686-pc-windows-msvc -gdwarf -gcodeview -S -emit-llvm
-o - %s \
// RUN: | FileCheck %s --check-prefixes=VER4,CODEVIEW
+// RUN: %clang -target powerpc-ibm-aix-xcoff -g -S -emit-llvm -o - %s | \
+// RUN: FileCheck %s --check-prefix=VER3
+// RUN: %clang -target powerpc-ibm-aix-xcoff -gdwarf-2 -S -emit-llvm -o - %s |
\
+// RUN: FileCheck %s --check-prefix=VER2
+// RUN: %clang -target powerpc-ibm-aix-xcoff -gdwarf-3 -S -emit-llvm -o - %s |
\
+// RUN: FileCheck %s --check-prefix=VER3
+// RUN: %clang -target powerpc-ibm-aix-xcoff -gdwarf-4 -S -emit-llvm -o - %s |
\
+// RUN: FileCheck %s --check-prefix=VER4
+// RUN: %clang -target powerpc-ibm-aix-xcoff -gdwarf-5 -S -emit-llvm -o - %s |
\
+// RUN: FileCheck %s --check-prefix=VER5
+
int main (void) {
return 0;
}
___
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[clang] b1d7010 - [DebugInfo] make DW_LANG_C11 respect -gstrict-dwarf
Author: Chen Zheng
Date: 2022-12-25T21:01:02-05:00
New Revision: b1d7010caa4394e7f5b41c627702f6acabe0cec5
URL:
https://github.com/llvm/llvm-project/commit/b1d7010caa4394e7f5b41c627702f6acabe0cec5
DIFF:
https://github.com/llvm/llvm-project/commit/b1d7010caa4394e7f5b41c627702f6acabe0cec5.diff
LOG: [DebugInfo] make DW_LANG_C11 respect -gstrict-dwarf
Reviewed By: dblaikie
Differential Revision: https://reviews.llvm.org/D140544
Added:
Modified:
clang/lib/CodeGen/CGDebugInfo.cpp
clang/test/CodeGen/debug-info-programming-language.c
Removed:
diff --git a/clang/lib/CodeGen/CGDebugInfo.cpp
b/clang/lib/CodeGen/CGDebugInfo.cpp
index 576a97b66859c..62ea222fade67 100644
--- a/clang/lib/CodeGen/CGDebugInfo.cpp
+++ b/clang/lib/CodeGen/CGDebugInfo.cpp
@@ -578,8 +578,8 @@ void CGDebugInfo::CreateCompileUnit() {
LangTag = llvm::dwarf::DW_LANG_OpenCL;
} else if (LO.RenderScript) {
LangTag = llvm::dwarf::DW_LANG_GOOGLE_RenderScript;
- } else if (LO.C11) {
-LangTag = llvm::dwarf::DW_LANG_C11;
+ } else if (LO.C11 && !(CGO.DebugStrictDwarf && CGO.DwarfVersion < 5)) {
+ LangTag = llvm::dwarf::DW_LANG_C11;
} else if (LO.C99) {
LangTag = llvm::dwarf::DW_LANG_C99;
} else {
diff --git a/clang/test/CodeGen/debug-info-programming-language.c
b/clang/test/CodeGen/debug-info-programming-language.c
index f81bab610d51e..02e45d89ca15e 100644
--- a/clang/test/CodeGen/debug-info-programming-language.c
+++ b/clang/test/CodeGen/debug-info-programming-language.c
@@ -4,7 +4,14 @@
// RUN: %clang_cc1 -dwarf-version=3 -emit-llvm -triple %itanium_abi_triple %s
-o - \
// RUN: -x c -std=c17 -O0 -disable-llvm-passes -debug-info-kind=limited \
// RUN: | FileCheck --check-prefix=CHECK-C17 %s
+// RUN: %clang_cc1 -dwarf-version=3 -emit-llvm -triple %itanium_abi_triple %s
-o - \
+// RUN: -x c -std=c11 -O0 -disable-llvm-passes -debug-info-kind=limited \
+// RUN: -gstrict-dwarf | FileCheck --check-prefix=CHECK-STRICT %s
+// RUN: %clang_cc1 -dwarf-version=5 -emit-llvm -triple %itanium_abi_triple %s
-o - \
+// RUN: -x c -std=c11 -O0 -disable-llvm-passes -debug-info-kind=limited \
+// RUN: -gstrict-dwarf | FileCheck --check-prefix=CHECK-C11 %s
+// CHECK-STRICT: !DICompileUnit(language: DW_LANG_C99
// CHECK-C11: !DICompileUnit(language: DW_LANG_C11
// Update this check once support for DW_LANG_C17 is broadly supported/known in
// consumers. Maybe we'll skip this and go to the DWARFv6 language+version
___
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[clang] [PowerPC] Support local-dynamic TLS relocation on AIX (PR #66316)
chenzheng1030 wrote: > Is it possible that we fix the hack implementation with some future version > (I will open an issue and work on it afterwards)? How about let's move on > with current approach? > @amy-kwan @stephenpeckham @bzEq @chenzheng1030 Appreciate your comments. > Thank you! I am not against this proposal given the internal timeline. https://github.com/llvm/llvm-project/pull/66316 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [PowerPC] Support local-dynamic TLS relocation on AIX (PR #66316)
chenzheng1030 wrote: The code formatting check fails. https://github.com/llvm/llvm-project/pull/66316 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)
https://github.com/chenzheng1030 created
https://github.com/llvm/llvm-project/pull/68476
Extend `PPCTargetInfo::getGCCAddlRegNames()` to aix as well. The definition
should be common between Linux PPC and AIX PPC.
I also use "abi" as the ABI name for AIX ABI. This aligns with LLVM
PPCSubtarget:
```
bool isAIXABI() const { return TargetTriple.isOSAIX(); }
bool isSVR4ABI() const { return !isAIXABI(); }
bool isELFv2ABI() const;
```
>From eada8d170cefcf2c1d152eaadc68dc4c3077c9ce Mon Sep 17 00:00:00 2001
From: Chen Zheng
Date: Sat, 7 Oct 2023 06:09:44 -0400
Subject: [PATCH] [AIX] recognize vsr in inline asm for AIX
---
clang/lib/Basic/Targets/PPC.cpp | 3 ++-
clang/lib/Basic/Targets/PPC.h| 3 ++-
clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c | 4
3 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index e0abc069032e1ce..fa56d39fd2fdada 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -807,6 +807,7 @@ ArrayRef
PPCTargetInfo::getGCCRegAliases() const {
// PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
// vs0 ~ vs31 is mapping to 32 - 63,
// vs32 ~ vs63 is mapping to 77 - 108.
+// And this mapping applies to all OSes which runs on powerpc.
const TargetInfo::AddlRegName GCCAddlRegNames[] = {
// Table of additional register names to use in user input.
{{"vs0"}, 32}, {{"vs1"}, 33}, {{"vs2"}, 34}, {{"vs3"}, 35},
@@ -828,7 +829,7 @@ const TargetInfo::AddlRegName GCCAddlRegNames[] = {
};
ArrayRef PPCTargetInfo::getGCCAddlRegNames() const {
- if (ABI == "elfv2")
+ if (ABI == "elfv2" || ABI == "aix")
return llvm::ArrayRef(GCCAddlRegNames);
else
return TargetInfo::getGCCAddlRegNames();
diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index ef667b3d511f0e6..c2a18d77a60a510 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -385,6 +385,7 @@ class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public
PPCTargetInfo {
LongDoubleWidth = 64;
LongDoubleAlign = DoubleAlign = 32;
LongDoubleFormat = &llvm::APFloat::IEEEdouble();
+ ABI = "aix";
break;
default:
break;
@@ -418,11 +419,11 @@ class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public
PPCTargetInfo {
std::string DataLayout;
if (Triple.isOSAIX()) {
- // TODO: Set appropriate ABI for AIX platform.
DataLayout = "E-m:a-Fi64-i64:64-n32:64";
LongDoubleWidth = 64;
LongDoubleAlign = DoubleAlign = 32;
LongDoubleFormat = &llvm::APFloat::IEEEdouble();
+ ABI = "aix";
} else if ((Triple.getArch() == llvm::Triple::ppc64le)) {
DataLayout = "e-m:e-Fn32-i64:64-n32:64";
ABI = "elfv2";
diff --git a/clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c
b/clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c
index a4fabd688175e14..a8033f22073cc9f 100644
--- a/clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c
+++ b/clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c
@@ -2,6 +2,10 @@
// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -target-feature +vsx \
// RUN: -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-ibm-aix -target-feature +vsx \
+// RUN: -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-ibm-aix -target-feature +vsx \
+// RUN: -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
// This case is to test VSX register support in the clobbers list for inline
asm.
void testVSX (void) {
___
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[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)
https://github.com/chenzheng1030 edited https://github.com/llvm/llvm-project/pull/68476 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)
https://github.com/chenzheng1030 updated
https://github.com/llvm/llvm-project/pull/68476
>From eada8d170cefcf2c1d152eaadc68dc4c3077c9ce Mon Sep 17 00:00:00 2001
From: Chen Zheng
Date: Sat, 7 Oct 2023 06:09:44 -0400
Subject: [PATCH 1/2] [AIX] recognize vsr in inline asm for AIX
---
clang/lib/Basic/Targets/PPC.cpp | 3 ++-
clang/lib/Basic/Targets/PPC.h| 3 ++-
clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c | 4
3 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index e0abc069032e1ce..fa56d39fd2fdada 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -807,6 +807,7 @@ ArrayRef
PPCTargetInfo::getGCCRegAliases() const {
// PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
// vs0 ~ vs31 is mapping to 32 - 63,
// vs32 ~ vs63 is mapping to 77 - 108.
+// And this mapping applies to all OSes which runs on powerpc.
const TargetInfo::AddlRegName GCCAddlRegNames[] = {
// Table of additional register names to use in user input.
{{"vs0"}, 32}, {{"vs1"}, 33}, {{"vs2"}, 34}, {{"vs3"}, 35},
@@ -828,7 +829,7 @@ const TargetInfo::AddlRegName GCCAddlRegNames[] = {
};
ArrayRef PPCTargetInfo::getGCCAddlRegNames() const {
- if (ABI == "elfv2")
+ if (ABI == "elfv2" || ABI == "aix")
return llvm::ArrayRef(GCCAddlRegNames);
else
return TargetInfo::getGCCAddlRegNames();
diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index ef667b3d511f0e6..c2a18d77a60a510 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -385,6 +385,7 @@ class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public
PPCTargetInfo {
LongDoubleWidth = 64;
LongDoubleAlign = DoubleAlign = 32;
LongDoubleFormat = &llvm::APFloat::IEEEdouble();
+ ABI = "aix";
break;
default:
break;
@@ -418,11 +419,11 @@ class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public
PPCTargetInfo {
std::string DataLayout;
if (Triple.isOSAIX()) {
- // TODO: Set appropriate ABI for AIX platform.
DataLayout = "E-m:a-Fi64-i64:64-n32:64";
LongDoubleWidth = 64;
LongDoubleAlign = DoubleAlign = 32;
LongDoubleFormat = &llvm::APFloat::IEEEdouble();
+ ABI = "aix";
} else if ((Triple.getArch() == llvm::Triple::ppc64le)) {
DataLayout = "e-m:e-Fn32-i64:64-n32:64";
ABI = "elfv2";
diff --git a/clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c
b/clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c
index a4fabd688175e14..a8033f22073cc9f 100644
--- a/clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c
+++ b/clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c
@@ -2,6 +2,10 @@
// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -target-feature +vsx \
// RUN: -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-ibm-aix -target-feature +vsx \
+// RUN: -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-ibm-aix -target-feature +vsx \
+// RUN: -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
// This case is to test VSX register support in the clobbers list for inline
asm.
void testVSX (void) {
>From 0d44bd306dc330f3f6c920789f986ae30b970505 Mon Sep 17 00:00:00 2001
From: Chen Zheng
Date: Sat, 7 Oct 2023 23:03:06 -0400
Subject: [PATCH 2/2] address comments
---
clang/lib/Basic/Targets/PPC.cpp | 7 ++-
clang/lib/Basic/Targets/PPC.h| 3 +--
clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c | 8 +---
3 files changed, 8 insertions(+), 10 deletions(-)
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index fa56d39fd2fdada..47cc8ee5db1b896 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -807,7 +807,7 @@ ArrayRef
PPCTargetInfo::getGCCRegAliases() const {
// PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
// vs0 ~ vs31 is mapping to 32 - 63,
// vs32 ~ vs63 is mapping to 77 - 108.
-// And this mapping applies to all OSes which runs on powerpc.
+// And this mapping applies to all OSes which run on powerpc.
const TargetInfo::AddlRegName GCCAddlRegNames[] = {
// Table of additional register names to use in user input.
{{"vs0"}, 32}, {{"vs1"}, 33}, {{"vs2"}, 34}, {{"vs3"}, 35},
@@ -829,10 +829,7 @@ const TargetInfo::AddlRegName GCCAddlRegNames[] = {
};
ArrayRef PPCTargetInfo::getGCCAddlRegNames() const {
- if (ABI == "elfv2" || ABI == "aix")
-return llvm::ArrayRef(GCCAddlRegNames);
- else
-return TargetInfo::getGCCAddlRegNames();
+ return llvm::ArrayRef(GCCAddlRegNames);
}
static constexpr llvm::StringLiteral ValidCPUNames[] = {
diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index c2a18d77a
[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)
@@ -807,6 +807,7 @@ ArrayRef
PPCTargetInfo::getGCCRegAliases() const {
// PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
// vs0 ~ vs31 is mapping to 32 - 63,
// vs32 ~ vs63 is mapping to 77 - 108.
+// And this mapping applies to all OSes which runs on powerpc.
chenzheng1030 wrote:
Now always return `GCCAddlRegNames()` for all PPC ABIs including big-endian
linux.
https://github.com/llvm/llvm-project/pull/68476
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[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)
@@ -2,6 +2,10 @@
// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -target-feature +vsx \
// RUN: -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-ibm-aix -target-feature +vsx \
+// RUN: -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-ibm-aix -target-feature +vsx \
+// RUN: -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
// This case is to test VSX register support in the clobbers list for inline
asm.
void testVSX (void) {
chenzheng1030 wrote:
Done, test case is updated to compileable by AIX system assembler.
https://github.com/llvm/llvm-project/pull/68476
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[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)
@@ -807,7 +807,7 @@ ArrayRef
PPCTargetInfo::getGCCRegAliases() const {
// PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
// vs0 ~ vs31 is mapping to 32 - 63,
// vs32 ~ vs63 is mapping to 77 - 108.
chenzheng1030 wrote:
This is what I get from DWARF spec:
Note that the register number represents a DWARF specific mapping of numbers
onto the actual registers of a given architecture. The mapping should be chosen
to gain optimal density and should be shared by all users of a given
architecture. It is recommended that this mapping be defined by the ABI
authoring committee for each architecture.
To me, the DWARF number should be architecture specific, i.e., although the
ABIs are different, all these ABIs on same architecture should use same DWARF
register mapping, because the hardware registers are bound to architecture?
https://github.com/llvm/llvm-project/pull/68476
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[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)
https://github.com/chenzheng1030 edited https://github.com/llvm/llvm-project/pull/68476 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][PowerPC] Support tune directive in target attribute (PR #68681)
https://github.com/chenzheng1030 approved this pull request. Make sense to me. Thanks. https://github.com/llvm/llvm-project/pull/68681 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)
@@ -828,10 +829,7 @@ const TargetInfo::AddlRegName GCCAddlRegNames[] = {
};
ArrayRef PPCTargetInfo::getGCCAddlRegNames() const {
- if (ABI == "elfv2")
-return llvm::ArrayRef(GCCAddlRegNames);
- else
-return TargetInfo::getGCCAddlRegNames();
+ return llvm::ArrayRef(GCCAddlRegNames);
chenzheng1030 wrote:
Accepting an non-exist(future defined) register in the asm clobber list should
not cause any issue in the compiler side, I think. The register allocator can
not allocate these future defined registers anyhow.
The more serious issue is that clang accepts vsx instructions in asm block even
for targets that does not have VSX, see https://godbolt.org/z/rYnMbPPTE (gcc
has same behavior.)
https://github.com/llvm/llvm-project/pull/68476
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[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)
@@ -807,7 +807,7 @@ ArrayRef
PPCTargetInfo::getGCCRegAliases() const {
// PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
// vs0 ~ vs31 is mapping to 32 - 63,
// vs32 ~ vs63 is mapping to 77 - 108.
chenzheng1030 wrote:
FP and VMX registers should have different DWARF number with VSX registers
although on PPC they are physically overlapped.
Let me check the usage for the DWARF numbers...
https://github.com/llvm/llvm-project/pull/68476
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[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)
https://github.com/chenzheng1030 edited https://github.com/llvm/llvm-project/pull/68476 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)
@@ -807,7 +807,7 @@ ArrayRef
PPCTargetInfo::getGCCRegAliases() const {
// PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
// vs0 ~ vs31 is mapping to 32 - 63,
// vs32 ~ vs63 is mapping to 77 - 108.
chenzheng1030 wrote:
@hubert-reinterpretcast I think you are right. There is a legacy issue in the
function `getNormalizedGCCRegisterName()`. Once `ReturnCanonical` is true for
that function, current clang(without this patch) will use name f0 ~ f31 and v0
~ v31 for vs0 ~ vs63 on ELFABIV2. And this patch extends this "issue" to AIX.
The `ReturnCanonical` was introduced in https://reviews.llvm.org/D15075 which
was targeted for X86. Seems for X86, physically overlapping registers have
canonical names, for example X86 ([eax|rax|al|ah] -> ax). But targets like PPC
and SystemZ do not have such canonical register names, for example, PPC (vs0 ->
f0), SystemZ(v0 -> f0) which are not right.
I prefer to solve this in another patch with solution: for targets that have no
canonical name for physically overlapping registers, `ReturnCanonical` should
always be false.
What do you think?
https://github.com/llvm/llvm-project/pull/68476
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[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)
https://github.com/chenzheng1030 updated
https://github.com/llvm/llvm-project/pull/68476
>From eada8d170cefcf2c1d152eaadc68dc4c3077c9ce Mon Sep 17 00:00:00 2001
From: Chen Zheng
Date: Sat, 7 Oct 2023 06:09:44 -0400
Subject: [PATCH 1/3] [AIX] recognize vsr in inline asm for AIX
---
clang/lib/Basic/Targets/PPC.cpp | 3 ++-
clang/lib/Basic/Targets/PPC.h| 3 ++-
clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c | 4
3 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index e0abc069032e1ce..fa56d39fd2fdada 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -807,6 +807,7 @@ ArrayRef
PPCTargetInfo::getGCCRegAliases() const {
// PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
// vs0 ~ vs31 is mapping to 32 - 63,
// vs32 ~ vs63 is mapping to 77 - 108.
+// And this mapping applies to all OSes which runs on powerpc.
const TargetInfo::AddlRegName GCCAddlRegNames[] = {
// Table of additional register names to use in user input.
{{"vs0"}, 32}, {{"vs1"}, 33}, {{"vs2"}, 34}, {{"vs3"}, 35},
@@ -828,7 +829,7 @@ const TargetInfo::AddlRegName GCCAddlRegNames[] = {
};
ArrayRef PPCTargetInfo::getGCCAddlRegNames() const {
- if (ABI == "elfv2")
+ if (ABI == "elfv2" || ABI == "aix")
return llvm::ArrayRef(GCCAddlRegNames);
else
return TargetInfo::getGCCAddlRegNames();
diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index ef667b3d511f0e6..c2a18d77a60a510 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -385,6 +385,7 @@ class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public
PPCTargetInfo {
LongDoubleWidth = 64;
LongDoubleAlign = DoubleAlign = 32;
LongDoubleFormat = &llvm::APFloat::IEEEdouble();
+ ABI = "aix";
break;
default:
break;
@@ -418,11 +419,11 @@ class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public
PPCTargetInfo {
std::string DataLayout;
if (Triple.isOSAIX()) {
- // TODO: Set appropriate ABI for AIX platform.
DataLayout = "E-m:a-Fi64-i64:64-n32:64";
LongDoubleWidth = 64;
LongDoubleAlign = DoubleAlign = 32;
LongDoubleFormat = &llvm::APFloat::IEEEdouble();
+ ABI = "aix";
} else if ((Triple.getArch() == llvm::Triple::ppc64le)) {
DataLayout = "e-m:e-Fn32-i64:64-n32:64";
ABI = "elfv2";
diff --git a/clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c
b/clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c
index a4fabd688175e14..a8033f22073cc9f 100644
--- a/clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c
+++ b/clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c
@@ -2,6 +2,10 @@
// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -target-feature +vsx \
// RUN: -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-ibm-aix -target-feature +vsx \
+// RUN: -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-ibm-aix -target-feature +vsx \
+// RUN: -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
// This case is to test VSX register support in the clobbers list for inline
asm.
void testVSX (void) {
>From 0d44bd306dc330f3f6c920789f986ae30b970505 Mon Sep 17 00:00:00 2001
From: Chen Zheng
Date: Sat, 7 Oct 2023 23:03:06 -0400
Subject: [PATCH 2/3] address comments
---
clang/lib/Basic/Targets/PPC.cpp | 7 ++-
clang/lib/Basic/Targets/PPC.h| 3 +--
clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c | 8 +---
3 files changed, 8 insertions(+), 10 deletions(-)
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index fa56d39fd2fdada..47cc8ee5db1b896 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -807,7 +807,7 @@ ArrayRef
PPCTargetInfo::getGCCRegAliases() const {
// PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
// vs0 ~ vs31 is mapping to 32 - 63,
// vs32 ~ vs63 is mapping to 77 - 108.
-// And this mapping applies to all OSes which runs on powerpc.
+// And this mapping applies to all OSes which run on powerpc.
const TargetInfo::AddlRegName GCCAddlRegNames[] = {
// Table of additional register names to use in user input.
{{"vs0"}, 32}, {{"vs1"}, 33}, {{"vs2"}, 34}, {{"vs3"}, 35},
@@ -829,10 +829,7 @@ const TargetInfo::AddlRegName GCCAddlRegNames[] = {
};
ArrayRef PPCTargetInfo::getGCCAddlRegNames() const {
- if (ABI == "elfv2" || ABI == "aix")
-return llvm::ArrayRef(GCCAddlRegNames);
- else
-return TargetInfo::getGCCAddlRegNames();
+ return llvm::ArrayRef(GCCAddlRegNames);
}
static constexpr llvm::StringLiteral ValidCPUNames[] = {
diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index c2a18d77a
[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)
@@ -807,7 +807,7 @@ ArrayRef
PPCTargetInfo::getGCCRegAliases() const {
// PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
// vs0 ~ vs31 is mapping to 32 - 63,
// vs32 ~ vs63 is mapping to 77 - 108.
chenzheng1030 wrote:
Done.
https://github.com/llvm/llvm-project/pull/68476
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[clang] [AIX] recognize vsr in inline asm for AIX (PR #68476)
https://github.com/chenzheng1030 closed https://github.com/llvm/llvm-project/pull/68476 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang] Check features of tune CPU against target CPU (PR #68861)
@@ -833,6 +833,22 @@ TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
if (!Target->handleTargetFeatures(Opts->Features, Diags))
return nullptr;
+ // If TuneCPU is set, check if it contains all instruction sets needed by
+ // current feature map.
+ if (!Opts->TuneCPU.empty() && Opts->TuneCPU != Opts->CPU) {
chenzheng1030 wrote:
Can this handle the case that we use default cpu(i.e. no -mcpu set)?
https://github.com/llvm/llvm-project/pull/68861
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[clang] 4b0a253 - [AIX] enable the cases that are excluded by XCOFF 64 integrated-as support
Author: Chen Zheng
Date: 2023-04-14T06:24:57-04:00
New Revision: 4b0a25375e9006ef82cc51119ff223a28bb15646
URL:
https://github.com/llvm/llvm-project/commit/4b0a25375e9006ef82cc51119ff223a28bb15646
DIFF:
https://github.com/llvm/llvm-project/commit/4b0a25375e9006ef82cc51119ff223a28bb15646.diff
LOG: [AIX] enable the cases that are excluded by XCOFF 64 integrated-as support
These case are excluded in https://reviews.llvm.org/D113049.
Now AIX XCOFF 64 integrated-as support improves a lot and all these
cases pass now, so enable them.
Added:
Modified:
clang/test/ASTMerge/codegen-body/test.c
clang/test/ClangScanDeps/modules-full-by-mod-name.c
clang/test/ClangScanDeps/resource_directory.c
llvm/unittests/DebugInfo/DWARF/DWARFDebugInfoTest.cpp
Removed:
diff --git a/clang/test/ASTMerge/codegen-body/test.c
b/clang/test/ASTMerge/codegen-body/test.c
index d6346c618750d..4489862eeb5c2 100644
--- a/clang/test/ASTMerge/codegen-body/test.c
+++ b/clang/test/ASTMerge/codegen-body/test.c
@@ -1,4 +1,3 @@
-// UNSUPPORTED: target=powerpc64-ibm-aix{{.*}}
// RUN: %clang_cc1 -emit-pch -o %t.1.ast %S/Inputs/body1.c
// RUN: %clang_cc1 -emit-pch -o %t.2.ast %S/Inputs/body2.c
// RUN: %clang_cc1 -emit-obj -o /dev/null -ast-merge %t.1.ast -ast-merge
%t.2.ast %s
diff --git a/clang/test/ClangScanDeps/modules-full-by-mod-name.c
b/clang/test/ClangScanDeps/modules-full-by-mod-name.c
index 054ff5494753c..7ebd39d0dc1c9 100644
--- a/clang/test/ClangScanDeps/modules-full-by-mod-name.c
+++ b/clang/test/ClangScanDeps/modules-full-by-mod-name.c
@@ -1,5 +1,3 @@
-// UNSUPPORTED: target=powerpc64-ibm-aix{{.*}}
-
// RUN: rm -rf %t
// RUN: split-file %s %t
diff --git a/clang/test/ClangScanDeps/resource_directory.c
b/clang/test/ClangScanDeps/resource_directory.c
index a528d2f8de8c1..55d5d90bbcdea 100644
--- a/clang/test/ClangScanDeps/resource_directory.c
+++ b/clang/test/ClangScanDeps/resource_directory.c
@@ -1,4 +1,3 @@
-// UNSUPPORTED: target=powerpc64-ibm-aix{{.*}}
// REQUIRES: shell
// RUN: rm -rf %t && mkdir %t
diff --git a/llvm/unittests/DebugInfo/DWARF/DWARFDebugInfoTest.cpp
b/llvm/unittests/DebugInfo/DWARF/DWARFDebugInfoTest.cpp
index 1d16a384d554a..26736fe2b687c 100644
--- a/llvm/unittests/DebugInfo/DWARF/DWARFDebugInfoTest.cpp
+++ b/llvm/unittests/DebugInfo/DWARF/DWARFDebugInfoTest.cpp
@@ -1176,11 +1176,13 @@ TEST(DWARFDebugInfo, TestStringOffsets) {
EXPECT_STREQ(String1, *Extracted3);
}
-#if defined(_AIX) && defined(__64BIT__)
+// AIX does not support string offset section.
+#if defined(_AIX)
TEST(DWARFDebugInfo, DISABLED_TestEmptyStringOffsets) {
#else
TEST(DWARFDebugInfo, TestEmptyStringOffsets) {
#endif
+
Triple Triple = getNormalizedDefaultTargetTriple();
if (!isConfigurationSupported(Triple))
GTEST_SKIP();
@@ -1209,11 +1211,7 @@ TEST(DWARFDebugInfo, TestEmptyStringOffsets) {
DwarfContext->getDWARFObj().getStrOffsetsSection().Data.empty());
}
-#if defined(_AIX) && defined(__64BIT__)
-TEST(DWARFDebugInfo, DISABLED_TestRelations) {
-#else
TEST(DWARFDebugInfo, TestRelations) {
-#endif
Triple Triple = getNormalizedDefaultTargetTriple();
if (!isConfigurationSupported(Triple))
GTEST_SKIP();
@@ -1400,11 +1398,7 @@ TEST(DWARFDebugInfo, TestDWARFDie) {
EXPECT_FALSE(DefaultDie.getSibling().isValid());
}
-#if defined(_AIX) && defined(__64BIT__)
-TEST(DWARFDebugInfo, DISABLED_TestChildIterators) {
-#else
TEST(DWARFDebugInfo, TestChildIterators) {
-#endif
Triple Triple = getNormalizedDefaultTargetTriple();
if (!isConfigurationSupported(Triple))
GTEST_SKIP();
@@ -1513,11 +1507,7 @@ TEST(DWARFDebugInfo, TestEmptyChildren) {
EXPECT_EQ(CUDie.begin(), CUDie.end());
}
-#if defined(_AIX) && defined(__64BIT__)
-TEST(DWARFDebugInfo, DISABLED_TestAttributeIterators) {
-#else
TEST(DWARFDebugInfo, TestAttributeIterators) {
-#endif
Triple Triple = getNormalizedDefaultTargetTriple();
if (!isConfigurationSupported(Triple))
GTEST_SKIP();
@@ -1579,11 +1569,7 @@ TEST(DWARFDebugInfo, TestAttributeIterators) {
EXPECT_EQ(E, ++I);
}
-#if defined(_AIX) && defined(__64BIT__)
-TEST(DWARFDebugInfo, DISABLED_TestFindRecurse) {
-#else
TEST(DWARFDebugInfo, TestFindRecurse) {
-#endif
Triple Triple = getNormalizedDefaultTargetTriple();
if (!isConfigurationSupported(Triple))
GTEST_SKIP();
@@ -1797,11 +1783,7 @@ TEST(DWARFDebugInfo, TestDwarfToFunctions) {
// Test
}
-#if defined(_AIX) && defined(__64BIT__)
-TEST(DWARFDebugInfo, DISABLED_TestFindAttrs) {
-#else
TEST(DWARFDebugInfo, TestFindAttrs) {
-#endif
Triple Triple = getNormalizedDefaultTargetTriple();
if (!isConfigurationSupported(Triple))
GTEST_SKIP();
@@ -1864,7 +1846,8 @@ TEST(DWARFDebugInfo, TestFindAttrs) {
EXPECT_EQ(DieMangled, toString(NameOpt, ""));
}
-#if defined(_AIX) && defined(__64BIT__)
+// AIX does not support debug_addr section.
+#if defined(_AIX)
TEST(DWARF
[clang] 4b27ad7 - [AIX] use system assembler for assembly files
Author: Chen Zheng
Date: 2023-06-04T21:37:48-04:00
New Revision: 4b27ad735c8da7cd21a7ea58614ebd4d3c940a89
URL:
https://github.com/llvm/llvm-project/commit/4b27ad735c8da7cd21a7ea58614ebd4d3c940a89
DIFF:
https://github.com/llvm/llvm-project/commit/4b27ad735c8da7cd21a7ea58614ebd4d3c940a89.diff
LOG: [AIX] use system assembler for assembly files
Change to system assembler to compile assembly files even
-fintegrated-as is specified. We don't have a good Clang as
for now for assembly files on AIX.
Reviewed By: qiucf
Differential Revision: https://reviews.llvm.org/D148490
Added:
Modified:
clang/lib/Driver/ToolChain.cpp
clang/test/Driver/aix-as.c
Removed:
diff --git a/clang/lib/Driver/ToolChain.cpp b/clang/lib/Driver/ToolChain.cpp
index 8bfa5baf92ff7..ccaebb384d4dc 100644
--- a/clang/lib/Driver/ToolChain.cpp
+++ b/clang/lib/Driver/ToolChain.cpp
@@ -662,7 +662,8 @@ Tool *ToolChain::SelectTool(const JobAction &JA) const {
if (D.IsFlangMode() && getDriver().ShouldUseFlangCompiler(JA)) return
getFlang();
if (getDriver().ShouldUseClangCompiler(JA)) return getClang();
Action::ActionClass AC = JA.getKind();
- if (AC == Action::AssembleJobClass && useIntegratedAs())
+ if (AC == Action::AssembleJobClass && useIntegratedAs() &&
+ !getTriple().isOSAIX())
return getClangAs();
return getTool(AC);
}
diff --git a/clang/test/Driver/aix-as.c b/clang/test/Driver/aix-as.c
index 9412604c2e84f..c6aeae4c10183 100644
--- a/clang/test/Driver/aix-as.c
+++ b/clang/test/Driver/aix-as.c
@@ -1,22 +1,40 @@
// General tests that as(1) invocations on AIX targets are sane. Note that we
// only test assembler functionalities in this suite.
+// Check powerpc-ibm-aix7.1.0.0, system assembler is used for assembly files,
32-bit.
+// RUN: %clang -x assembler %s -### -c -fintegrated-as 2>&1 \
+// RUN: --target=powerpc-ibm-aix7.1.0.0 \
+// RUN: | FileCheck --check-prefix=CHECK-AS32 %s
+//
+// RUN: %clang -x assembler %s -### -c 2>&1 -fno-integrated-as \
+// RUN: --target=powerpc-ibm-aix7.1.0.0 \
+// RUN: | FileCheck --check-prefix=CHECK-AS32 %s
+
// Check powerpc-ibm-aix7.1.0.0, 32-bit.
// RUN: %clang %s -### -c 2>&1 \
// RUN: --target=powerpc-ibm-aix7.1.0.0 \
-// RUN: | FileCheck --check-prefix=CHECK-AS32 %s
+// RUN: | FileCheck --check-prefixes=CHECK-AS32,CHECK-AS32-CC1 %s
// CHECK-AS32-NOT: warning:
-// CHECK-AS32: "-cc1" "-triple" "powerpc-ibm-aix7.1.0.0"
+// CHECK-AS32-CC1: "-cc1" "-triple" "powerpc-ibm-aix7.1.0.0"
// CHECK-AS32: "{{.*}}as{{(.exe)?}}"
// CHECK-AS32: "-a32"
// CHECK-AS32: "-many"
+// Check powerpc64-ibm-aix7.1.0.0, system assembler is used for assembly
files, 64-bit.
+// RUN: %clang -x assembler %s -### -c -fintegrated-as 2>&1 \
+// RUN: --target=powerpc64-ibm-aix7.1.0.0 \
+// RUN: | FileCheck --check-prefix=CHECK-AS64 %s
+//
+// RUN: %clang -x assembler %s -### -c -fno-integrated-as 2>&1 \
+// RUN: --target=powerpc64-ibm-aix7.1.0.0 \
+// RUN: | FileCheck --check-prefix=CHECK-AS64 %s
+
// Check powerpc64-ibm-aix7.1.0.0, 64-bit.
// RUN: %clang %s -### -c 2>&1 \
// RUN: --target=powerpc64-ibm-aix7.1.0.0 \
-// RUN: | FileCheck --check-prefix=CHECK-AS64 %s
+// RUN: | FileCheck --check-prefixes=CHECK-AS64,CHECK-AS64-CC1 %s
// CHECK-AS64-NOT: warning:
-// CHECK-AS64: "-cc1" "-triple" "powerpc64-ibm-aix7.1.0.0"
+// CHECK-AS64-CC1: "-cc1" "-triple" "powerpc64-ibm-aix7.1.0.0"
// CHECK-AS64: "{{.*}}as{{(.exe)?}}"
// CHECK-AS64: "-a64"
// CHECK-AS64: "-many"
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[clang] 225cf64 - fix failures caused by https://reviews.llvm.org/D148490
Author: Chen Zheng
Date: 2023-06-05T04:00:26-04:00
New Revision: 225cf64e03b4e394c32e95fe1d6414e6e16be094
URL:
https://github.com/llvm/llvm-project/commit/225cf64e03b4e394c32e95fe1d6414e6e16be094
DIFF:
https://github.com/llvm/llvm-project/commit/225cf64e03b4e394c32e95fe1d6414e6e16be094.diff
LOG: fix failures caused by https://reviews.llvm.org/D148490
buildbot: https://lab.llvm.org/buildbot/#/builders/214/builds/7823
Added:
clang/test/Driver/compilation-dir.c
Modified:
clang/test/Driver/as-version.s
clang/test/Driver/clang_f_opts.c
clang/test/Driver/compress-unavailable.s
clang/test/Driver/debug-options-as.c
clang/test/Driver/debug-prefix-map.S
clang/test/Driver/defsym.s
clang/test/Driver/embed-bitcode.c
clang/test/Driver/integrated-as.c
clang/test/Driver/relax.s
Removed:
diff --git a/clang/test/Driver/as-version.s b/clang/test/Driver/as-version.s
index a96b2b5762c65..5003819372be2 100644
--- a/clang/test/Driver/as-version.s
+++ b/clang/test/Driver/as-version.s
@@ -1,6 +1,6 @@
// Test version information.
-// UNSUPPORTED: target={{.*}}-zos{{.*}}
+// UNSUPPORTED: target={{.*}}-zos{{.*}}, target={{.*}}-aix{{.*}}
// RUN: %clang -Wa,--version -c -fintegrated-as %s -o /dev/null \
// RUN: | FileCheck --check-prefix=IAS %s
// IAS: clang version
diff --git a/clang/test/Driver/clang_f_opts.c
b/clang/test/Driver/clang_f_opts.c
index 67ec82a09f852..8060e52d5e8fd 100644
--- a/clang/test/Driver/clang_f_opts.c
+++ b/clang/test/Driver/clang_f_opts.c
@@ -517,15 +517,6 @@
// CHECK-CF-PROTECTION-BRANCH: -fcf-protection=branch
// CHECK-NO-CF-PROTECTION-BRANCH-NOT: -fcf-protection=branch
-// RUN: %clang -### -S -fdebug-compilation-dir . %s 2>&1 | FileCheck
-check-prefix=CHECK-DEBUG-COMPILATION-DIR %s
-// RUN: %clang -### -S -fdebug-compilation-dir=. %s 2>&1 | FileCheck
-check-prefix=CHECK-DEBUG-COMPILATION-DIR %s
-// RUN: %clang -### -integrated-as -fdebug-compilation-dir . -x assembler %s
2>&1 | FileCheck -check-prefix=CHECK-DEBUG-COMPILATION-DIR %s
-// RUN: %clang -### -integrated-as -fdebug-compilation-dir=. -x assembler %s
2>&1 | FileCheck -check-prefix=CHECK-DEBUG-COMPILATION-DIR %s
-// RUN: %clang -### -S -ffile-compilation-dir=. %s 2>&1 | FileCheck
-check-prefix=CHECK-DEBUG-COMPILATION-DIR %s
-// RUN: %clang -### -integrated-as -ffile-compilation-dir=. -x assembler %s
2>&1 | FileCheck -check-prefixes=CHECK-DEBUG-COMPILATION-DIR %s
-// CHECK-DEBUG-COMPILATION-DIR: "-fdebug-compilation-dir=."
-// CHECK-DEBUG-COMPILATION-DIR-NOT: "-ffile-compilation-dir=."
-
// RUN: %clang -### -S -fprofile-instr-generate -fcoverage-compilation-dir=.
%s 2>&1 | FileCheck -check-prefix=CHECK-COVERAGE-COMPILATION-DIR %s
// RUN: %clang -### -S -fprofile-instr-generate -ffile-compilation-dir=. %s
2>&1 | FileCheck -check-prefix=CHECK-COVERAGE-COMPILATION-DIR %s
// CHECK-COVERAGE-COMPILATION-DIR: "-fcoverage-compilation-dir=."
diff --git a/clang/test/Driver/compilation-dir.c
b/clang/test/Driver/compilation-dir.c
new file mode 100644
index 0..dbe801c9f5fcb
--- /dev/null
+++ b/clang/test/Driver/compilation-dir.c
@@ -0,0 +1,10 @@
+// XFAIL: target={{.*}}-aix{{.*}}
+
+// RUN: %clang -### -S -fdebug-compilation-dir . %s 2>&1 | FileCheck
-check-prefix=CHECK-DEBUG-COMPILATION-DIR %s
+// RUN: %clang -### -S -fdebug-compilation-dir=. %s 2>&1 | FileCheck
-check-prefix=CHECK-DEBUG-COMPILATION-DIR %s
+// RUN: %clang -### -integrated-as -fdebug-compilation-dir . -x assembler %s
2>&1 | FileCheck -check-prefix=CHECK-DEBUG-COMPILATION-DIR %s
+// RUN: %clang -### -integrated-as -fdebug-compilation-dir=. -x assembler %s
2>&1 | FileCheck -check-prefix=CHECK-DEBUG-COMPILATION-DIR %s
+// RUN: %clang -### -S -ffile-compilation-dir=. %s 2>&1 | FileCheck
-check-prefix=CHECK-DEBUG-COMPILATION-DIR %s
+// RUN: %clang -### -integrated-as -ffile-compilation-dir=. -x assembler %s
2>&1 | FileCheck -check-prefixes=CHECK-DEBUG-COMPILATION-DIR %s
+// CHECK-DEBUG-COMPILATION-DIR: "-fdebug-compilation-dir=."
+// CHECK-DEBUG-COMPILATION-DIR-NOT: "-ffile-compilation-dir=."
diff --git a/clang/test/Driver/compress-unavailable.s
b/clang/test/Driver/compress-unavailable.s
index e44fcb4ce9d5e..2842c23725eb5 100644
--- a/clang/test/Driver/compress-unavailable.s
+++ b/clang/test/Driver/compress-unavailable.s
@@ -1,3 +1,5 @@
+; XFAIL: target={{.*}}-aix{{.*}}
+
// RUN: %clang -### -fintegrated-as -gz=none -c %s 2>&1 | FileCheck %s
--check-prefix=NOWARN
// NOWARN-NOT: warning: cannot compress debug sections (zlib not enabled)
diff --git a/clang/test/Driver/debug-options-as.c
b/clang/test/Driver/debug-options-as.c
index 87268e8c5deaf..5bb67e93a1b62 100644
--- a/clang/test/Driver/debug-options-as.c
+++ b/clang/test/Driver/debug-options-as.c
@@ -1,3 +1,5 @@
+; XFAIL: target={{.*}}-aix{{.*}}
+
// Check to make sure clang is somewhat picky about -g options.
// (Delived from debug-options.c)
// rdar:/
[clang] b447dc5 - use // instad of ; in c file tests, NFC
Author: Chen Zheng
Date: 2023-06-05T05:02:38-04:00
New Revision: b447dc5a4704bef8ced95495aa8d9ea477a26814
URL:
https://github.com/llvm/llvm-project/commit/b447dc5a4704bef8ced95495aa8d9ea477a26814
DIFF:
https://github.com/llvm/llvm-project/commit/b447dc5a4704bef8ced95495aa8d9ea477a26814.diff
LOG: use // instad of ; in c file tests, NFC
Added:
Modified:
clang/test/Driver/compress-unavailable.s
clang/test/Driver/debug-options-as.c
clang/test/Driver/debug-prefix-map.S
clang/test/Driver/defsym.s
clang/test/Driver/integrated-as.c
Removed:
diff --git a/clang/test/Driver/compress-unavailable.s
b/clang/test/Driver/compress-unavailable.s
index 2842c23725eb5..de422fb088b7d 100644
--- a/clang/test/Driver/compress-unavailable.s
+++ b/clang/test/Driver/compress-unavailable.s
@@ -1,4 +1,4 @@
-; XFAIL: target={{.*}}-aix{{.*}}
+// XFAIL: target={{.*}}-aix{{.*}}
// RUN: %clang -### -fintegrated-as -gz=none -c %s 2>&1 | FileCheck %s
--check-prefix=NOWARN
// NOWARN-NOT: warning: cannot compress debug sections (zlib not enabled)
diff --git a/clang/test/Driver/debug-options-as.c
b/clang/test/Driver/debug-options-as.c
index 5bb67e93a1b62..259ad583edaa4 100644
--- a/clang/test/Driver/debug-options-as.c
+++ b/clang/test/Driver/debug-options-as.c
@@ -1,4 +1,4 @@
-; XFAIL: target={{.*}}-aix{{.*}}
+// XFAIL: target={{.*}}-aix{{.*}}
// Check to make sure clang is somewhat picky about -g options.
// (Delived from debug-options.c)
diff --git a/clang/test/Driver/debug-prefix-map.S
b/clang/test/Driver/debug-prefix-map.S
index ae526525f154c..febf608690420 100644
--- a/clang/test/Driver/debug-prefix-map.S
+++ b/clang/test/Driver/debug-prefix-map.S
@@ -1,4 +1,4 @@
-; XFAIL: target={{.*}}-aix{{.*}}
+// XFAIL: target={{.*}}-aix{{.*}}
// RUN: %clang -### -g -fintegrated-as -fdebug-prefix-map=old=new %s 2>&1 |
FileCheck %s
// RUN: %clang -### -g -fintegrated-as -ffile-prefix-map=old=new %s 2>&1 |
FileCheck %s
diff --git a/clang/test/Driver/defsym.s b/clang/test/Driver/defsym.s
index ecd13a2e497f3..165c71b2eae97 100644
--- a/clang/test/Driver/defsym.s
+++ b/clang/test/Driver/defsym.s
@@ -1,4 +1,4 @@
-; XFAIL: target={{.*}}-aix{{.*}}
+// XFAIL: target={{.*}}-aix{{.*}}
// RUN: %clang -### -c -integrated-as %s \
// RUN: -Wa,-defsym,abc=5 -Wa,-defsym,xyz=0xa \
diff --git a/clang/test/Driver/integrated-as.c
b/clang/test/Driver/integrated-as.c
index aca0ba2d19d8d..d7658fdfd6337 100644
--- a/clang/test/Driver/integrated-as.c
+++ b/clang/test/Driver/integrated-as.c
@@ -1,4 +1,4 @@
-; XFAIL: target={{.*}}-aix{{.*}}
+// XFAIL: target={{.*}}-aix{{.*}}
// RUN: %clang -### -c -save-temps -integrated-as %s 2>&1 | FileCheck %s
___
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[clang] 6a992bc - [PowerPC] refactor CPU info in PPCTargetParser.def, NFC
Author: Chen Zheng
Date: 2024-07-03T00:20:14-04:00
New Revision: 6a992bc89f5ca25d132abd044d78ecf27ae6e162
URL:
https://github.com/llvm/llvm-project/commit/6a992bc89f5ca25d132abd044d78ecf27ae6e162
DIFF:
https://github.com/llvm/llvm-project/commit/6a992bc89f5ca25d132abd044d78ecf27ae6e162.diff
LOG: [PowerPC] refactor CPU info in PPCTargetParser.def, NFC
CPU features will be done in follow up patches.
Added:
llvm/tools/clang
Modified:
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp
llvm/include/llvm/TargetParser/PPCTargetParser.def
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
Removed:
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index a1e5f20f7dbe2..89c5566f7ad09 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -928,17 +928,18 @@ bool PPCTargetInfo::validateCpuSupports(StringRef
FeatureStr) const {
bool PPCTargetInfo::validateCpuIs(StringRef CPUName) const {
llvm::Triple Triple = getTriple();
- if (Triple.isOSAIX()) {
-#define PPC_AIX_CPU(NAME, SUPPORT_METHOD, INDEX, OP, VALUE) .Case(NAME, true)
-return llvm::StringSwitch(CPUName)
-#include "llvm/TargetParser/PPCTargetParser.def"
-.Default(false);
- }
-
- assert(Triple.isOSLinux() &&
+ assert((Triple.isOSAIX() || Triple.isOSLinux()) &&
"__builtin_cpu_is() is only supported for AIX and Linux.");
-#define PPC_LNX_CPU(NAME, NUM) .Case(NAME, true)
- return llvm::StringSwitch(CPUName)
+
+#define PPC_CPU(NAME, Linux_SUPPORT_METHOD, LinuxID, AIX_SUPPORT_METHOD,
\
+AIXID)
\
+ .Case(NAME, {Linux_SUPPORT_METHOD, AIX_SUPPORT_METHOD})
+
+ std::pair SuppportMethod =
+ llvm::StringSwitch>(CPUName)
#include "llvm/TargetParser/PPCTargetParser.def"
- .Default(false);
+ .Default({BUILTIN_PPC_UNSUPPORTED, BUILTIN_PPC_UNSUPPORTED});
+ return Triple.isOSLinux()
+ ? (SuppportMethod.first != BUILTIN_PPC_UNSUPPORTED)
+ : (SuppportMethod.second != BUILTIN_PPC_UNSUPPORTED);
}
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index ed37267efe715..5b92f1837980c 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -16748,10 +16748,10 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
auto GenAIXPPCBuiltinCpuExpr = [&](unsigned SupportMethod, unsigned FieldIdx,
unsigned Mask, CmpInst::Predicate CompOp,
unsigned OpValue) -> Value * {
-if (SupportMethod == AIX_BUILTIN_PPC_FALSE)
+if (SupportMethod == BUILTIN_PPC_FALSE)
return llvm::ConstantInt::getFalse(ConvertType(E->getType()));
-if (SupportMethod == AIX_BUILTIN_PPC_TRUE)
+if (SupportMethod == BUILTIN_PPC_TRUE)
return llvm::ConstantInt::getTrue(ConvertType(E->getType()));
assert(SupportMethod <= SYS_CALL && "Invalid value for SupportMethod.");
@@ -16803,34 +16803,39 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
StringRef CPUStr = cast(CPUExpr)->getString();
llvm::Triple Triple = getTarget().getTriple();
-if (Triple.isOSAIX()) {
- unsigned SupportMethod, FieldIdx, CpuIdValue;
- CmpInst::Predicate CompareOp;
- typedef std::tuple
- CPUType;
- std::tie(SupportMethod, FieldIdx, CompareOp, CpuIdValue) =
- static_cast(StringSwitch(CPUStr)
-#define PPC_AIX_CPU(NAME, SUPPORT_METHOD, INDEX, COMPARE_OP, VALUE)
\
- .Case(NAME, {SUPPORT_METHOD, INDEX, COMPARE_OP, VALUE})
+unsigned LinuxSupportMethod, LinuxIDValue, AIXSupportMethod, AIXIDValue;
+typedef std::tuple CPUInfo;
+
+std::tie(LinuxSupportMethod, LinuxIDValue, AIXSupportMethod, AIXIDValue) =
+static_cast(StringSwitch(CPUStr)
+#define PPC_CPU(NAME, Linux_SUPPORT_METHOD, LinuxID, AIX_SUPPORT_METHOD,
\
+AIXID)
\
+ .Case(NAME, {Linux_SUPPORT_METHOD, LinuxID, AIX_SUPPORT_METHOD, AIXID})
#include "llvm/TargetParser/PPCTargetParser.def"
- .Default({AIX_BUILTIN_PPC_FALSE, 0,
- CmpInst::Predicate(), 0}));
- return GenAIXPPCBuiltinCpuExpr(SupportMethod, FieldIdx, 0, CompareOp,
- CpuIdValue);
+ .Default({BUILTIN_PPC_UNSUPPORTED, 0,
+ BUILTIN_PPC_UNSUPPORTED, 0}));
+
+if (Triple.isOSAIX()) {
+ assert((AIXSupportMethod != BUILTIN_PPC_UNSUPPORTED) &&
+ "Invalid CPU name. Missed by SemaChecking?");
+ return GenAIXPPCBuiltinCpuExpr(AIXSupportMethod, AIX_SYSCON_IMPL_IDX, 0,
+ ICmpInst::ICMP_EQ, AIXIDValue);
}
a
[clang] [llvm] [PowerPC] add TargetParser for PPC target (PR #97541)
https://github.com/chenzheng1030 created
https://github.com/llvm/llvm-project/pull/97541
For now only focus on the CPU type, will work on the CPU features part later.
With the CPU handling in TargetParser, clang and llc/opt are able to query
common interfaces.
So we can set same default CPU and CPU features with same interfaces.
>From 5a2787925bc05453763b2577fd95daa8f39acb1b Mon Sep 17 00:00:00 2001
From: Chen Zheng
Date: Wed, 3 Jul 2024 04:42:25 -0400
Subject: [PATCH] [PowerPC] add TargetParser for PPC target For now only focus
on the CPU type, will work on the CPU features part later.
---
clang/lib/Basic/Targets/PPC.cpp | 18 +--
clang/lib/Driver/ToolChains/Arch/PPC.cpp | 72 ---
clang/lib/Driver/ToolChains/Arch/PPC.h| 4 -
clang/lib/Driver/ToolChains/Clang.cpp | 8 +-
clang/lib/Driver/ToolChains/CommonArgs.cpp| 5 +-
clang/test/CodeGen/aix-builtin-cpu-is.c | 42 +++---
clang/test/Misc/target-invalid-cpu-note.c | 2 +-
.../llvm/TargetParser/PPCTargetParser.def | 53 +++-
.../llvm/TargetParser/PPCTargetParser.h | 37 ++
llvm/lib/TargetParser/CMakeLists.txt | 1 +
llvm/lib/TargetParser/PPCTargetParser.cpp | 121 ++
.../secondary/llvm/lib/TargetParser/BUILD.gn | 1 +
12 files changed, 251 insertions(+), 113 deletions(-)
create mode 100644 llvm/include/llvm/TargetParser/PPCTargetParser.h
create mode 100644 llvm/lib/TargetParser/PPCTargetParser.cpp
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 89c5566f7ad09..5543f4a100c46 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -14,6 +14,7 @@
#include "clang/Basic/Diagnostic.h"
#include "clang/Basic/MacroBuilder.h"
#include "clang/Basic/TargetBuiltins.h"
+#include "llvm/TargetParser/PPCTargetParser.h"
using namespace clang;
using namespace clang::targets;
@@ -866,25 +867,12 @@ ArrayRef
PPCTargetInfo::getGCCAddlRegNames() const {
return llvm::ArrayRef(GCCAddlRegNames);
}
-static constexpr llvm::StringLiteral ValidCPUNames[] = {
-{"generic"}, {"440"}, {"450"},{"601"}, {"602"},
-{"603"}, {"603e"},{"603ev"}, {"604"}, {"604e"},
-{"620"}, {"630"}, {"g3"}, {"7400"}, {"g4"},
-{"7450"},{"g4+"}, {"750"},{"8548"}, {"970"},
-{"g5"}, {"a2"}, {"e500"}, {"e500mc"},{"e5500"},
-{"power3"}, {"pwr3"},{"power4"}, {"pwr4"}, {"power5"},
-{"pwr5"},{"power5x"}, {"pwr5x"}, {"power6"},{"pwr6"},
-{"power6x"}, {"pwr6x"}, {"power7"}, {"pwr7"}, {"power8"},
-{"pwr8"},{"power9"}, {"pwr9"}, {"power10"}, {"pwr10"},
-{"powerpc"}, {"ppc"}, {"ppc32"}, {"powerpc64"}, {"ppc64"},
-{"powerpc64le"}, {"ppc64le"}, {"future"}};
-
bool PPCTargetInfo::isValidCPUName(StringRef Name) const {
- return llvm::is_contained(ValidCPUNames, Name);
+ return llvm::PPC::isValidCPU(Name);
}
void PPCTargetInfo::fillValidCPUList(SmallVectorImpl &Values) const
{
- Values.append(std::begin(ValidCPUNames), std::end(ValidCPUNames));
+ llvm::PPC::fillValidCPUList(Values);
}
void PPCTargetInfo::adjust(DiagnosticsEngine &Diags, LangOptions &Opts) {
diff --git a/clang/lib/Driver/ToolChains/Arch/PPC.cpp
b/clang/lib/Driver/ToolChains/Arch/PPC.cpp
index 634c096523319..b63e16c22370d 100644
--- a/clang/lib/Driver/ToolChains/Arch/PPC.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/PPC.cpp
@@ -20,78 +20,6 @@ using namespace clang::driver::tools;
using namespace clang;
using namespace llvm::opt;
-static std::string getPPCGenericTargetCPU(const llvm::Triple &T) {
- // LLVM may default to generating code for the native CPU,
- // but, like gcc, we default to a more generic option for
- // each architecture. (except on AIX)
- if (T.isOSAIX())
-return "pwr7";
- else if (T.getArch() == llvm::Triple::ppc64le)
-return "ppc64le";
- else if (T.getArch() == llvm::Triple::ppc64)
-return "ppc64";
- else
-return "ppc";
-}
-
-static std::string normalizeCPUName(StringRef CPUName, const llvm::Triple &T) {
- // Clang/LLVM does not actually support code generation
- // for the 405 CPU. However, there are uses of this CPU ID
- // in projects that previously used GCC and rely on Clang
- // accepting it. Clang has always ignored it and passed the
- // generic CPU ID to the back end.
- if (CPUName == "generic" || CPUName == "405")
-return getPPCGenericTargetCPU(T);
-
- if (CPUName == "native") {
-std::string CPU = std::string(llvm::sys::getHostCPUName());
-if (!CPU.empty() && CPU != "generic")
- return CPU;
-else
- return getPPCGenericTargetCPU(T);
- }
-
- return llvm::StringSwitch(CPUName)
- .Case("common", "generic")
- .Case("440fp", "440")
- .Case("630", "pwr3")
- .Case("G3", "g3")
- .Case("G4", "g4")
- .Case("G4+", "g4+")
- .Case("8548
[clang] [llvm] [PowerPC] add TargetParser for PPC target (PR #97541)
https://github.com/chenzheng1030 unassigned https://github.com/llvm/llvm-project/pull/97541 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PowerPC] add TargetParser for PPC target (PR #97541)
https://github.com/chenzheng1030 updated
https://github.com/llvm/llvm-project/pull/97541
>From 405639a8847111e401d5c2b69bb801c1c0ccadb7 Mon Sep 17 00:00:00 2001
From: Chen Zheng
Date: Wed, 3 Jul 2024 04:42:25 -0400
Subject: [PATCH] [PowerPC] add TargetParser for PPC target For now only focus
on the CPU type, will work on the CPU features part later.
---
clang/lib/Basic/Targets/PPC.cpp | 18 +--
clang/lib/Driver/ToolChains/Arch/PPC.cpp | 72 ---
clang/lib/Driver/ToolChains/Arch/PPC.h| 4 -
clang/lib/Driver/ToolChains/Clang.cpp | 8 +-
clang/lib/Driver/ToolChains/CommonArgs.cpp| 5 +-
clang/test/CodeGen/aix-builtin-cpu-is.c | 42 +++---
clang/test/Misc/target-invalid-cpu-note.c | 2 +-
.../llvm/TargetParser/PPCTargetParser.def | 53 +++-
.../llvm/TargetParser/PPCTargetParser.h | 37 ++
llvm/lib/TargetParser/CMakeLists.txt | 1 +
llvm/lib/TargetParser/PPCTargetParser.cpp | 120 ++
.../secondary/llvm/lib/TargetParser/BUILD.gn | 1 +
12 files changed, 250 insertions(+), 113 deletions(-)
create mode 100644 llvm/include/llvm/TargetParser/PPCTargetParser.h
create mode 100644 llvm/lib/TargetParser/PPCTargetParser.cpp
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 89c5566f7ad09..5543f4a100c46 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -14,6 +14,7 @@
#include "clang/Basic/Diagnostic.h"
#include "clang/Basic/MacroBuilder.h"
#include "clang/Basic/TargetBuiltins.h"
+#include "llvm/TargetParser/PPCTargetParser.h"
using namespace clang;
using namespace clang::targets;
@@ -866,25 +867,12 @@ ArrayRef
PPCTargetInfo::getGCCAddlRegNames() const {
return llvm::ArrayRef(GCCAddlRegNames);
}
-static constexpr llvm::StringLiteral ValidCPUNames[] = {
-{"generic"}, {"440"}, {"450"},{"601"}, {"602"},
-{"603"}, {"603e"},{"603ev"}, {"604"}, {"604e"},
-{"620"}, {"630"}, {"g3"}, {"7400"}, {"g4"},
-{"7450"},{"g4+"}, {"750"},{"8548"}, {"970"},
-{"g5"}, {"a2"}, {"e500"}, {"e500mc"},{"e5500"},
-{"power3"}, {"pwr3"},{"power4"}, {"pwr4"}, {"power5"},
-{"pwr5"},{"power5x"}, {"pwr5x"}, {"power6"},{"pwr6"},
-{"power6x"}, {"pwr6x"}, {"power7"}, {"pwr7"}, {"power8"},
-{"pwr8"},{"power9"}, {"pwr9"}, {"power10"}, {"pwr10"},
-{"powerpc"}, {"ppc"}, {"ppc32"}, {"powerpc64"}, {"ppc64"},
-{"powerpc64le"}, {"ppc64le"}, {"future"}};
-
bool PPCTargetInfo::isValidCPUName(StringRef Name) const {
- return llvm::is_contained(ValidCPUNames, Name);
+ return llvm::PPC::isValidCPU(Name);
}
void PPCTargetInfo::fillValidCPUList(SmallVectorImpl &Values) const
{
- Values.append(std::begin(ValidCPUNames), std::end(ValidCPUNames));
+ llvm::PPC::fillValidCPUList(Values);
}
void PPCTargetInfo::adjust(DiagnosticsEngine &Diags, LangOptions &Opts) {
diff --git a/clang/lib/Driver/ToolChains/Arch/PPC.cpp
b/clang/lib/Driver/ToolChains/Arch/PPC.cpp
index 634c096523319..b63e16c22370d 100644
--- a/clang/lib/Driver/ToolChains/Arch/PPC.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/PPC.cpp
@@ -20,78 +20,6 @@ using namespace clang::driver::tools;
using namespace clang;
using namespace llvm::opt;
-static std::string getPPCGenericTargetCPU(const llvm::Triple &T) {
- // LLVM may default to generating code for the native CPU,
- // but, like gcc, we default to a more generic option for
- // each architecture. (except on AIX)
- if (T.isOSAIX())
-return "pwr7";
- else if (T.getArch() == llvm::Triple::ppc64le)
-return "ppc64le";
- else if (T.getArch() == llvm::Triple::ppc64)
-return "ppc64";
- else
-return "ppc";
-}
-
-static std::string normalizeCPUName(StringRef CPUName, const llvm::Triple &T) {
- // Clang/LLVM does not actually support code generation
- // for the 405 CPU. However, there are uses of this CPU ID
- // in projects that previously used GCC and rely on Clang
- // accepting it. Clang has always ignored it and passed the
- // generic CPU ID to the back end.
- if (CPUName == "generic" || CPUName == "405")
-return getPPCGenericTargetCPU(T);
-
- if (CPUName == "native") {
-std::string CPU = std::string(llvm::sys::getHostCPUName());
-if (!CPU.empty() && CPU != "generic")
- return CPU;
-else
- return getPPCGenericTargetCPU(T);
- }
-
- return llvm::StringSwitch(CPUName)
- .Case("common", "generic")
- .Case("440fp", "440")
- .Case("630", "pwr3")
- .Case("G3", "g3")
- .Case("G4", "g4")
- .Case("G4+", "g4+")
- .Case("8548", "e500")
- .Case("G5", "g5")
- .Case("power3", "pwr3")
- .Case("power4", "pwr4")
- .Case("power5", "pwr5")
- .Case("power5x", "pwr5x")
- .Case("power6", "pwr6")
- .Case("power6x", "pwr6x")
- .Case("power7
[clang] [llvm] [PowerPC] add TargetParser for PPC target (PR #97541)
https://github.com/chenzheng1030 updated
https://github.com/llvm/llvm-project/pull/97541
>From 405639a8847111e401d5c2b69bb801c1c0ccadb7 Mon Sep 17 00:00:00 2001
From: Chen Zheng
Date: Wed, 3 Jul 2024 04:42:25 -0400
Subject: [PATCH 1/2] [PowerPC] add TargetParser for PPC target For now only
focus on the CPU type, will work on the CPU features part later.
---
clang/lib/Basic/Targets/PPC.cpp | 18 +--
clang/lib/Driver/ToolChains/Arch/PPC.cpp | 72 ---
clang/lib/Driver/ToolChains/Arch/PPC.h| 4 -
clang/lib/Driver/ToolChains/Clang.cpp | 8 +-
clang/lib/Driver/ToolChains/CommonArgs.cpp| 5 +-
clang/test/CodeGen/aix-builtin-cpu-is.c | 42 +++---
clang/test/Misc/target-invalid-cpu-note.c | 2 +-
.../llvm/TargetParser/PPCTargetParser.def | 53 +++-
.../llvm/TargetParser/PPCTargetParser.h | 37 ++
llvm/lib/TargetParser/CMakeLists.txt | 1 +
llvm/lib/TargetParser/PPCTargetParser.cpp | 120 ++
.../secondary/llvm/lib/TargetParser/BUILD.gn | 1 +
12 files changed, 250 insertions(+), 113 deletions(-)
create mode 100644 llvm/include/llvm/TargetParser/PPCTargetParser.h
create mode 100644 llvm/lib/TargetParser/PPCTargetParser.cpp
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 89c5566f7ad09..5543f4a100c46 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -14,6 +14,7 @@
#include "clang/Basic/Diagnostic.h"
#include "clang/Basic/MacroBuilder.h"
#include "clang/Basic/TargetBuiltins.h"
+#include "llvm/TargetParser/PPCTargetParser.h"
using namespace clang;
using namespace clang::targets;
@@ -866,25 +867,12 @@ ArrayRef
PPCTargetInfo::getGCCAddlRegNames() const {
return llvm::ArrayRef(GCCAddlRegNames);
}
-static constexpr llvm::StringLiteral ValidCPUNames[] = {
-{"generic"}, {"440"}, {"450"},{"601"}, {"602"},
-{"603"}, {"603e"},{"603ev"}, {"604"}, {"604e"},
-{"620"}, {"630"}, {"g3"}, {"7400"}, {"g4"},
-{"7450"},{"g4+"}, {"750"},{"8548"}, {"970"},
-{"g5"}, {"a2"}, {"e500"}, {"e500mc"},{"e5500"},
-{"power3"}, {"pwr3"},{"power4"}, {"pwr4"}, {"power5"},
-{"pwr5"},{"power5x"}, {"pwr5x"}, {"power6"},{"pwr6"},
-{"power6x"}, {"pwr6x"}, {"power7"}, {"pwr7"}, {"power8"},
-{"pwr8"},{"power9"}, {"pwr9"}, {"power10"}, {"pwr10"},
-{"powerpc"}, {"ppc"}, {"ppc32"}, {"powerpc64"}, {"ppc64"},
-{"powerpc64le"}, {"ppc64le"}, {"future"}};
-
bool PPCTargetInfo::isValidCPUName(StringRef Name) const {
- return llvm::is_contained(ValidCPUNames, Name);
+ return llvm::PPC::isValidCPU(Name);
}
void PPCTargetInfo::fillValidCPUList(SmallVectorImpl &Values) const
{
- Values.append(std::begin(ValidCPUNames), std::end(ValidCPUNames));
+ llvm::PPC::fillValidCPUList(Values);
}
void PPCTargetInfo::adjust(DiagnosticsEngine &Diags, LangOptions &Opts) {
diff --git a/clang/lib/Driver/ToolChains/Arch/PPC.cpp
b/clang/lib/Driver/ToolChains/Arch/PPC.cpp
index 634c096523319..b63e16c22370d 100644
--- a/clang/lib/Driver/ToolChains/Arch/PPC.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/PPC.cpp
@@ -20,78 +20,6 @@ using namespace clang::driver::tools;
using namespace clang;
using namespace llvm::opt;
-static std::string getPPCGenericTargetCPU(const llvm::Triple &T) {
- // LLVM may default to generating code for the native CPU,
- // but, like gcc, we default to a more generic option for
- // each architecture. (except on AIX)
- if (T.isOSAIX())
-return "pwr7";
- else if (T.getArch() == llvm::Triple::ppc64le)
-return "ppc64le";
- else if (T.getArch() == llvm::Triple::ppc64)
-return "ppc64";
- else
-return "ppc";
-}
-
-static std::string normalizeCPUName(StringRef CPUName, const llvm::Triple &T) {
- // Clang/LLVM does not actually support code generation
- // for the 405 CPU. However, there are uses of this CPU ID
- // in projects that previously used GCC and rely on Clang
- // accepting it. Clang has always ignored it and passed the
- // generic CPU ID to the back end.
- if (CPUName == "generic" || CPUName == "405")
-return getPPCGenericTargetCPU(T);
-
- if (CPUName == "native") {
-std::string CPU = std::string(llvm::sys::getHostCPUName());
-if (!CPU.empty() && CPU != "generic")
- return CPU;
-else
- return getPPCGenericTargetCPU(T);
- }
-
- return llvm::StringSwitch(CPUName)
- .Case("common", "generic")
- .Case("440fp", "440")
- .Case("630", "pwr3")
- .Case("G3", "g3")
- .Case("G4", "g4")
- .Case("G4+", "g4+")
- .Case("8548", "e500")
- .Case("G5", "g5")
- .Case("power3", "pwr3")
- .Case("power4", "pwr4")
- .Case("power5", "pwr5")
- .Case("power5x", "pwr5x")
- .Case("power6", "pwr6")
- .Case("power6x", "pwr6x")
- .Case("po
[clang] [llvm] [PowerPC] add TargetParser for PPC target (PR #97541)
https://github.com/chenzheng1030 edited https://github.com/llvm/llvm-project/pull/97541 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PowerPC] add TargetParser for PPC target (PR #97541)
@@ -85,8 +85,59 @@
#define AIX_PPC9_VALUE 0x0002
#define AIX_PPC10_VALUE 0x0004
-// __builtin_cpu_is() and __builtin_cpu_supports() are supported only on
Power7 and up on AIX.
// PPC_CPU(Name, Linux_SUPPORT_METHOD, LinuxID, AIX_SUPPORT_METHOD, AIXID)
+
+// Valid CPUs not supported by __builtin_cpu_is()
+PPC_CPU("generic",BUILTIN_PPC_FALSE,0,BUILTIN_PPC_FALSE,0)
+PPC_CPU("440",SYS_CALL,42,BUILTIN_PPC_FALSE,0)
chenzheng1030 wrote:
I added some cpu checks in `clang/test/CodeGen/builtin-cpu-supports.c`.
https://github.com/llvm/llvm-project/pull/97541
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[clang] [llvm] [PowerPC] add TargetParser for PPC target (PR #97541)
https://github.com/chenzheng1030 commented: Thanks for your comments @daltenty @ecnelises . Comments addressed. https://github.com/llvm/llvm-project/pull/97541 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PowerPC] add TargetParser for PPC target (PR #97541)
@@ -0,0 +1,120 @@
+//=== PPCTargetParser.cpp - Parser for target features --*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file implements a target parser to recognise hardware features
+// for PPC CPUs.
+//
+//===--===//
+
+#include "llvm/TargetParser/PPCTargetParser.h"
+#include "llvm/ADT/StringSwitch.h"
+#include "llvm/TargetParser/Host.h"
+
+namespace llvm {
+namespace PPC {
+
+struct CPUInfo {
+ StringLiteral Name;
+ // FIXME: add the features field for this CPU.
+};
+
+constexpr CPUInfo PPCCPUInfo[] = {
+#define PPC_CPU(Name, Linux_SUPPORT_METHOD, LinuxID, AIX_SUPPORT_METHOD,
\
+AIXID)
\
+ Name,
+#include "llvm/TargetParser/PPCTargetParser.def"
+};
+
+static const CPUInfo *getCPUInfoByName(StringRef CPU) {
+ for (auto &C : PPCCPUInfo)
+if (C.Name == CPU)
+ return &C;
+ return nullptr;
+}
+
+StringRef normalizeCPUName(StringRef CPUName) {
+ // Clang/LLVM does not actually support code generation
+ // for the 405 CPU. However, there are uses of this CPU ID
+ // in projects that previously used GCC and rely on Clang
+ // accepting it. Clang has always ignored it and passed the
+ // generic CPU ID to the back end.
+ return StringSwitch(CPUName)
+ .Cases("common", "405", "generic")
+ .Cases("ppc440", "440fp", "440")
+ .Cases("630", "power3", "pwr3")
+ .Case("G3", "g3")
+ .Case("G4", "g4")
+ .Case("G4+", "g4+")
+ .Case("8548", "e500")
+ .Case("ppc970", "970")
+ .Case("G5", "g5")
+ .Case("ppca2", "a2")
+ .Case("power4", "pwr4")
+ .Case("power5", "pwr5")
+ .Case("power5x", "pwr5x")
+ .Case("power5+", "pwr5+")
+ .Case("power6", "pwr6")
+ .Case("power6x", "pwr6x")
+ .Case("power7", "pwr7")
+ .Case("power8", "pwr8")
+ .Case("power9", "pwr9")
+ .Case("power10", "pwr10")
+ .Cases("powerpc", "powerpc32", "ppc")
+ .Case("powerpc64", "ppc64")
+ .Case("powerpc64le", "ppc64le")
+ .Default(CPUName);
+}
+
+void fillValidCPUList(SmallVectorImpl &Values) {
+ for (const auto &C : PPCCPUInfo)
+Values.emplace_back(C.Name);
+}
+
+void fillValidTuneCPUList(SmallVectorImpl &Values) {
+ for (const auto &C : PPCCPUInfo)
+Values.emplace_back(C.Name);
+}
+
+bool isValidCPU(StringRef CPU) {
+ const CPUInfo *Info = getCPUInfoByName(CPU);
+ if (!Info)
+return false;
+ return true;
+}
+
+StringRef getPPCGenericTargetCPU(const Triple &T, StringRef CPUName) {
+ if (!CPUName.empty()) {
+if (CPUName == "native") {
+ std::string CPU = std::string(sys::getHostCPUName());
+ if (!CPU.empty() && CPU != "generic")
+return CPU;
+}
+
+StringRef CPU = normalizeCPUName(CPUName);
+if (CPU != "generic")
+ return CPU;
+ }
+
+ // LLVM may default to generating code for the native CPU, but, like gcc, we
+ // default to a more generic option for each architecture. (except on AIX)
+ if (T.isOSAIX())
+return "pwr7";
+ else if (T.getArch() == Triple::ppc64le)
+return "ppc64le";
+ else if (T.getArch() == Triple::ppc64)
+return "ppc64";
chenzheng1030 wrote:
This is a good comment. Let's change this in another patch. Thanks.
https://github.com/llvm/llvm-project/pull/97541
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[clang] [llvm] [PowerPC] add TargetParser for PPC target (PR #97541)
@@ -1,52 +1,60 @@
-// RUN: echo "int main() { return __builtin_cpu_is(\"ppc970\");}" > %t.c
+// RUN: echo "int main() { return __builtin_cpu_is(\"ppc970\");}" > %t.c
// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s
-// RUN: echo "int main() { return __builtin_cpu_is(\"ppc-cell-be\");}" > %t.c
+// RUN: echo "int main() { return __builtin_cpu_is(\"ppc-cell-be\");}" > %t.c
// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s
-// RUN: echo "int main() { return __builtin_cpu_is(\"ppca2\");}" > %t.c
+// RUN: echo "int main() { return __builtin_cpu_is(\"ppca2\");}" > %t.c
// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s
-// RUN: echo "int main() { return __builtin_cpu_is(\"ppc405\");}" > %t.c
+// RUN: echo "int main() { return __builtin_cpu_is(\"ppc405\");}" > %t.c
// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s
-// RUN: echo "int main() { return __builtin_cpu_is(\"ppc440\");}" > %t.c
+// RUN: echo "int main() { return __builtin_cpu_is(\"ppc440\");}" > %t.c
// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s
-// RUN: echo "int main() { return __builtin_cpu_is(\"ppc464\");}" > %t.c
+// RUN: echo "int main() { return __builtin_cpu_is(\"ppc464\");}" > %t.c
// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s
-// RUN: echo "int main() { return __builtin_cpu_is(\"ppc476\");}" > %t.c
+// RUN: echo "int main() { return __builtin_cpu_is(\"ppc476\");}" > %t.c
// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s
-// RUN: echo "int main() { return __builtin_cpu_is(\"power4\");}" > %t.c
+// RUN: echo "int main() { return __builtin_cpu_is(\"power4\");}" > %t.c
// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s
-// RUN: echo "int main() { return __builtin_cpu_is(\"power5\");}" > %t.c
+// RUN: echo "int main() { return __builtin_cpu_is(\"power5\");}" > %t.c
// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s
-// RUN: echo "int main() { return __builtin_cpu_is(\"power5+\");}" > %t.c
+// RUN: echo "int main() { return __builtin_cpu_is(\"power5+\");}" > %t.c
// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s
-// RUN: echo "int main() { return __builtin_cpu_is(\"power6\");}" > %t.c
+// RUN: echo "int main() { return __builtin_cpu_is(\"power6\");}" > %t.c
// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s
-// RUN: echo "int main() { return __builtin_cpu_is(\"power6x\");}" > %t.c
+// RUN: echo "int main() { return __builtin_cpu_is(\"power6x\");}" > %t.c
// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s
-// RUN: echo "int main() { return __builtin_cpu_is(\"power7\");}" > %t.c
+// RUN: echo "int main() { return __builtin_cpu_is(\"power7\");}" > %t.c
// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s -DVALUE=32768 \
// RUN: --check-prefix=CHECKOP
-// RUN: echo "int main() { return __builtin_cpu_is(\"power8\");}" > %t.c
+// RUN: echo "int main() { return __builtin_cpu_is(\"pwr7\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s -DVALUE=32768 \
+// RUN: --check-prefix=CHECKOP
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"power8\");}" > %t.c
chenzheng1030 wrote:
ha, I just want to avoid unnecessary tests. Coverage should be enough by
checking pwr7 and pwr10. If you think pwr8 and pwr9 cases are necessary, I can
add them
https://github.com/llvm/llvm-project/pull/97541
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[clang] [llvm] [PowerPC] Diagnose musttail instead of crash inside backend (PR #93267)
chenzheng1030 wrote: @efriedma-quic sorry to bother you. Do you think the new update is the correct one? Thanks very much. https://github.com/llvm/llvm-project/pull/93267 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PowerPC] Diagnose musttail instead of crash inside backend (PR #93267)
https://github.com/chenzheng1030 closed https://github.com/llvm/llvm-project/pull/93267 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][Driver] Define soft float macros for PPC. (PR #106012)
https://github.com/chenzheng1030 closed https://github.com/llvm/llvm-project/pull/106012 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [PowerPC] Support -mno-red-zone option (PR #94581)
https://github.com/chenzheng1030 commented: Are there backend cases that shows with -disable-red-zone, the final assembly is still correct? https://github.com/llvm/llvm-project/pull/94581 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [PowerPC] Support -mno-red-zone option (PR #94581)
https://github.com/chenzheng1030 edited https://github.com/llvm/llvm-project/pull/94581 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [PowerPC] Support -mno-red-zone option (PR #94581)
chenzheng1030 wrote: > No. `-disable-red-zone` does nothing but add `noredzone` IR attribute to > functions. We need to add cases to test for `noredzone` behavior on PPC (arm > and x86 have). Yeah, go ahead to add some backend tests first to make sure we have good functionality for `noredzone` attribute. Thanks. https://github.com/llvm/llvm-project/pull/94581 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PowerPC] Support -mno-red-zone option (PR #94581)
https://github.com/chenzheng1030 approved this pull request. The small LIT cases seem all good. Based on that, the patch LGTM. If possible, can you run some big applications with `-mno-redzone` to double confirm the functionality? I am not so sure about its quality since the option seems not be tested on PPC at all... https://github.com/llvm/llvm-project/pull/94581 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
