[PATCH 04/17] drm/amd/display: Add SMU timeout check and retry
Instead of only asserting in the case of the SMU wait time is not what
we expect, add the SMU timeout check and try again.
Signed-off-by: Rodrigo Siqueira
---
.../display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 11 ---
.../drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c| 6 +-
2 files changed, 13 insertions(+), 4 deletions(-)
diff --git
a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
index d72acbb049b1..23b390245b5d 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
@@ -26,6 +26,10 @@
#include "core_types.h"
#include "clk_mgr_internal.h"
#include "reg_helper.h"
+#include "dm_helpers.h"
+
+#include "rn_clk_mgr_vbios_smu.h"
+
#include
#include "renoir_ip_offset.h"
@@ -33,8 +37,6 @@
#include "mp/mp_12_0_0_offset.h"
#include "mp/mp_12_0_0_sh_mask.h"
-#include "rn_clk_mgr_vbios_smu.h"
-
#define REG(reg_name) \
(MP0_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ##
reg_name)
@@ -120,7 +122,10 @@ static int rn_vbios_smu_send_msg_with_param(struct
clk_mgr_internal *clk_mgr,
result = rn_smu_wait_for_response(clk_mgr, 10, 20);
- ASSERT(result == VBIOSSMC_Result_OK || result ==
VBIOSSMC_Result_UnknownCmd);
+ if (IS_SMU_TIMEOUT(result)) {
+ ASSERT(0);
+ dm_helpers_smu_timeout(CTX, msg_id, param, 10 * 20);
+ }
/* Actual dispclk set is returned in the parameter register */
return REG_READ(MP1_SMN_C2PMSG_83);
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
index 19e5b3be9275..b4fb17b7a096 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
@@ -29,6 +29,7 @@
#include
#include "dcn301_smu.h"
+#include "dm_helpers.h"
#include "vangogh_ip_offset.h"
@@ -120,7 +121,10 @@ static int dcn301_smu_send_msg_with_param(struct
clk_mgr_internal *clk_mgr,
result = dcn301_smu_wait_for_response(clk_mgr, 10, 20);
- ASSERT(result == VBIOSSMC_Result_OK);
+ if (IS_SMU_TIMEOUT(result)) {
+ ASSERT(0);
+ dm_helpers_smu_timeout(CTX, msg_id, param, 10 * 20);
+ }
/* Actual dispclk set is returned in the parameter register */
return REG_READ(MP1_SMN_C2PMSG_83);
--
2.43.0
[PATCH 01/17] drm/amd/display: Remove break after return
Remove break after return since it will never be reached.
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
index 28a2a837d2f0..86ee4fe4f5e3 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
@@ -340,7 +340,6 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx,
struct pp_smu_funcs *p
dcn32_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
return &clk_mgr->base;
- break;
}
case AMDGPU_FAMILY_GC_11_0_1: {
--
2.43.0
[PATCH 00/17] DC Patches February 14, 2024
This DC patchset brings improvements in multiple areas. In summary, we highlight: - Re-enable windowed MPO support for DCN32/321. - Improvements in the subvp feature. - Code clean-up. - USB4 fixes. Cc: Daniel Wheeler Thanks Siqueira Alvin Lee (2): drm/amd/display: Generalize new minimal transition path drm/amd/display: Remove pixle rate limit for subvp Aric Cyr (2): drm/amd/display: Fix nanosec stat overflow drm/amd/display: 3.2.273 Ethan Bitnun (1): drm/amd/display: Only log during optimize_bandwidth call George Shen (1): drm/amd/display: Check DP Alt mode DPCS state via DMUB Lewis Huang (1): drm/amd/display: Only allow dig mapping to pwrseq in new asic Nicholas Kazlauskas (1): drm/amd/display: Fix S4 hang polling on HW power up done for VBIOS DMCUB Rodrigo Siqueira (6): drm/amd/display: Remove break after return drm/amd/display: Initialize variable with default value drm/amd/display: Remove unused file drm/amd/display: Add SMU timeout check and retry drm/amd/display: Remove redundant FPU guard drm/amd/display: Drop unnecessary header Swapnil Patel (1): drm/amd/display: fix input states translation error for dcn35 & dcn351 Wayne Lin (1): drm/amd/display: adjust few initialization order in dm Wenjing Liu (1): drm/amd/display: reenable windowed mpo odm support on dcn32 and dcn321 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 37 +++-- .../gpu/drm/amd/display/dc/basics/dce_calcs.c | 2 - .../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 3 - .../display/dc/clk_mgr/dce100/dce_clk_mgr.c | 2 +- .../display/dc/clk_mgr/dcn10/rv1_clk_mgr.c| 2 - .../dc/clk_mgr/dcn10/rv1_clk_mgr_clk.c| 79 -- .../dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 11 +- .../display/dc/clk_mgr/dcn301/dcn301_smu.c| 6 +- .../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 4 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 146 +++--- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- .../drm/amd/display/dc/dce/dce_panel_cntl.c | 1 + .../amd/display/dc/dcn301/dcn301_panel_cntl.c | 1 + .../amd/display/dc/dcn31/dcn31_panel_cntl.c | 18 ++- .../display/dc/dcn32/dcn32_dio_link_encoder.c | 85 +++--- .../display/dc/dcn32/dcn32_dio_link_encoder.h | 5 + .../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 1 - .../display/dc/dml2/dml2_translation_helper.c | 9 +- .../gpu/drm/amd/display/dc/hdcp/hdcp_msg.c| 2 - .../gpu/drm/amd/display/dc/inc/core_types.h | 31 ++-- .../drm/amd/display/dc/inc/hw/panel_cntl.h| 2 +- .../display/dc/irq/dcn20/irq_service_dcn20.c | 2 - .../display/dc/irq/dcn21/irq_service_dcn21.c | 2 - .../drm/amd/display/dc/link/link_factory.c| 26 +--- .../dc/resource/dcn20/dcn20_resource.c| 2 - .../dc/resource/dcn32/dcn32_resource.c| 1 + .../dc/resource/dcn321/dcn321_resource.c | 2 +- .../gpu/drm/amd/display/dmub/src/dmub_dcn35.c | 8 +- .../gpu/drm/amd/display/dmub/src/dmub_srv.c | 9 +- .../drm/amd/display/modules/inc/mod_stats.h | 4 +- 30 files changed, 223 insertions(+), 282 deletions(-) delete mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_clk.c -- 2.43.0
[PATCH 03/17] drm/amd/display: Remove unused file
The file rv1_clk_mgr_clk.c is not used and for this reason useless. Drop
the unnecessary file.
Signed-off-by: Rodrigo Siqueira
---
.../dc/clk_mgr/dcn10/rv1_clk_mgr_clk.c| 79 ---
1 file changed, 79 deletions(-)
delete mode 100644
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_clk.c
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_clk.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_clk.c
deleted file mode 100644
index 61dd12198a3c..
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_clk.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Copyright 2012-16 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "reg_helper.h"
-#include "clk_mgr_internal.h"
-#include "rv1_clk_mgr_clk.h"
-
-#include "ip/Discovery/hwid.h"
-#include "ip/Discovery/v1/ip_offset_1.h"
-#include "ip/CLK/clk_10_0_default.h"
-#include "ip/CLK/clk_10_0_offset.h"
-#include "ip/CLK/clk_10_0_reg.h"
-#include "ip/CLK/clk_10_0_sh_mask.h"
-
-#include "dce100/dce_clk_mgr.h"
-
-#define CLK_BASE_INNER(inst) \
- CLK_BASE__INST ## inst ## _SEG0
-
-
-#define CLK_REG(reg_name, block, inst)\
- CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
- mm ## block ## _ ## inst ## _ ##
reg_name
-
-#define REG(reg_name) \
- CLK_REG(reg_name, CLK0, 0)
-
-
-/* Only used by testing framework*/
-void rv1_dump_clk_registers(struct clk_state_registers *regs, struct
clk_bypass *bypass, struct clk_mgr *clk_mgr_base)
-{
- struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
-
- regs->CLK0_CLK8_CURRENT_CNT = REG_READ(CLK0_CLK8_CURRENT_CNT) /
10; //dcf clk
-
- bypass->dcfclk_bypass = REG_READ(CLK0_CLK8_BYPASS_CNTL) &
0x0007;
- if (bypass->dcfclk_bypass < 0 || bypass->dcfclk_bypass > 4)
- bypass->dcfclk_bypass = 0;
-
-
- regs->CLK0_CLK8_DS_CNTL = REG_READ(CLK0_CLK8_DS_CNTL) / 10;
//dcf deep sleep divider
-
- regs->CLK0_CLK8_ALLOW_DS = REG_READ(CLK0_CLK8_ALLOW_DS); //dcf
deep sleep allow
-
- regs->CLK0_CLK10_CURRENT_CNT = REG_READ(CLK0_CLK10_CURRENT_CNT)
/ 10; //dpref clk
-
- bypass->dispclk_pypass = REG_READ(CLK0_CLK10_BYPASS_CNTL) &
0x0007;
- if (bypass->dispclk_pypass < 0 || bypass->dispclk_pypass > 4)
- bypass->dispclk_pypass = 0;
-
- regs->CLK0_CLK11_CURRENT_CNT = REG_READ(CLK0_CLK11_CURRENT_CNT)
/ 10; //disp clk
-
- bypass->dprefclk_bypass = REG_READ(CLK0_CLK11_BYPASS_CNTL) &
0x0007;
- if (bypass->dprefclk_bypass < 0 || bypass->dprefclk_bypass > 4)
- bypass->dprefclk_bypass = 0;
-
-}
--
2.43.0
[PATCH 02/17] drm/amd/display: Initialize variable with default value
Set a default value for target_div. Signed-off-by: Rodrigo Siqueira --- drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c index 26feefbb8990..b77804cfde0f 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c @@ -132,7 +132,7 @@ int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) int dprefclk_wdivider; int dprefclk_src_sel; int dp_ref_clk_khz; - int target_div; + int target_div = 60; /* ASSERT DP Reference Clock source is from DFS*/ REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, &dprefclk_src_sel); -- 2.43.0
[PATCH 05/17] drm/amd/display: Remove redundant FPU guard
The function dcn32_build_wm_range_table call DC_FP_START/END. Drop the unnecessary FPU guard. Signed-off-by: Rodrigo Siqueira --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index e64e45e4c833..ee5e7512a7ee 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -243,10 +243,8 @@ void dcn32_init_clocks(struct clk_mgr *clk_mgr_base) /* Get UCLK, update bounding box */ clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base); - DC_FP_START(); /* WM range table */ dcn32_build_wm_range_table(clk_mgr); - DC_FP_END(); } static void dcn32_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr, -- 2.43.0
[PATCH 06/17] drm/amd/display: adjust few initialization order in dm
From: Wayne Lin
[Why]
Observe error message "Can't retrieve aconnector in hpd_rx_irq_offload_work"
when boot up with a mst tbt4 dock connected. After analyzing, there are few
parts needed to be adjusted:
1. hpd_rx_offload_wq[].aconnector is not initialzed before the dmub outbox
hpd_irq handler get registered which causes the error message.
2. registeration of hpd and hpd_rx_irq event for usb4 dp tunneling is not
aligned with legacy interface sequence
[How]
Put DMUB_NOTIFICATION_HPD and DMUB_NOTIFICATION_HPD_IRQ handler
registration into register_hpd_handlers() to align other interfaces and
get hpd_rx_offload_wq[].aconnector initialized earlier than that.
Leave DMUB_NOTIFICATION_AUX_REPLY registered as it was since we need that
while calling dc_link_detect(). USB4 connection status will be proactively
detected by dc_link_detect_connection_type() in
amdgpu_dm_initialize_drm_device()
Cc: Stable
Reviewed-by: Aurabindo Pillai
Acked-by: Rodrigo Siqueira
Signed-off-by: Wayne Lin
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 37 +--
1 file changed, 18 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index b9ac3d2f8029..ed0ad44dd1d8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1843,21 +1843,12 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
DRM_ERROR("amdgpu: fail to register dmub aux callback");
goto error;
}
- if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD,
dmub_hpd_callback, true)) {
- DRM_ERROR("amdgpu: fail to register dmub hpd callback");
- goto error;
- }
- if (!register_dmub_notify_callback(adev,
DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) {
- DRM_ERROR("amdgpu: fail to register dmub hpd callback");
- goto error;
- }
- }
-
- /* Enable outbox notification only after IRQ handlers are registered
and DMUB is alive.
-* It is expected that DMUB will resend any pending notifications at
this point, for
-* example HPD from DPIA.
-*/
- if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
+ /* Enable outbox notification only after IRQ handlers are
registered and DMUB is alive.
+* It is expected that DMUB will resend any pending
notifications at this point. Note
+* that hpd and hpd_irq handler registration are deferred to
register_hpd_handlers() to
+* align legacy interface initialization sequence. Connection
status will be proactivly
+* detected once in the amdgpu_dm_initialize_drm_device.
+*/
dc_enable_dmub_outbox(adev->dm.dc);
/* DPIA trace goes to dmesg logs only if outbox is enabled */
@@ -3546,6 +3537,14 @@ static void register_hpd_handlers(struct amdgpu_device
*adev)
int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
+ if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
+ if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD,
dmub_hpd_callback, true))
+ DRM_ERROR("amdgpu: fail to register dmub hpd callback");
+
+ if (!register_dmub_notify_callback(adev,
DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true))
+ DRM_ERROR("amdgpu: fail to register dmub hpd callback");
+ }
+
list_for_each_entry(connector,
&dev->mode_config.connector_list, head) {
@@ -3574,10 +3573,6 @@ static void register_hpd_handlers(struct amdgpu_device
*adev)
handle_hpd_rx_irq,
(void *) aconnector);
}
-
- if (adev->dm.hpd_rx_offload_wq)
- adev->dm.hpd_rx_offload_wq[connector->index].aconnector
=
- aconnector;
}
}
@@ -4589,6 +4584,10 @@ static int amdgpu_dm_initialize_drm_device(struct
amdgpu_device *adev)
goto fail;
}
+ if (dm->hpd_rx_offload_wq)
+
dm->hpd_rx_offload_wq[aconnector->base.index].aconnector =
+ aconnector;
+
if (!dc_link_detect_connection_type(link, &new_connection_type))
DRM_ERROR("KMS: Failed to detect connector\n");
--
2.43.0
[PATCH 09/17] drm/amd/display: Check DP Alt mode DPCS state via DMUB
From: George Shen
[Why]
Currently, driver state for DCN3.2 is not strictly matching HW state for
the USBC port. To reduce inconsistencies while debugging, the driver
should match HW configuration.
[How]
Update link encoder flag to indicate USBC port. Call into DMUB to check
when DP Alt mode is entered, and also to check for 2-lane versuse 4-lane
mode.
Reviewed-by: Charlene Liu
Acked-by: Rodrigo Siqueira
Signed-off-by: George Shen
---
.../display/dc/dcn32/dcn32_dio_link_encoder.c | 85 ++-
.../display/dc/dcn32/dcn32_dio_link_encoder.h | 5 ++
2 files changed, 71 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c
index d761b0df2878..e224a028d68a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c
@@ -34,6 +34,7 @@
#include "dc_bios_types.h"
#include "link_enc_cfg.h"
+#include "dc_dmub_srv.h"
#include "gpio_service_interface.h"
#ifndef MIN
@@ -61,6 +62,38 @@
#define AUX_REG_WRITE(reg_name, val) \
dm_write_reg(CTX, AUX_REG(reg_name), val)
+static uint8_t phy_id_from_transmitter(enum transmitter t)
+{
+ uint8_t phy_id;
+
+ switch (t) {
+ case TRANSMITTER_UNIPHY_A:
+ phy_id = 0;
+ break;
+ case TRANSMITTER_UNIPHY_B:
+ phy_id = 1;
+ break;
+ case TRANSMITTER_UNIPHY_C:
+ phy_id = 2;
+ break;
+ case TRANSMITTER_UNIPHY_D:
+ phy_id = 3;
+ break;
+ case TRANSMITTER_UNIPHY_E:
+ phy_id = 4;
+ break;
+ case TRANSMITTER_UNIPHY_F:
+ phy_id = 5;
+ break;
+ case TRANSMITTER_UNIPHY_G:
+ phy_id = 6;
+ break;
+ default:
+ phy_id = 0;
+ break;
+ }
+ return phy_id;
+}
void enc32_hw_init(struct link_encoder *enc)
{
@@ -117,38 +150,50 @@ void dcn32_link_encoder_enable_dp_output(
}
}
-static bool dcn32_link_encoder_is_in_alt_mode(struct link_encoder *enc)
+static bool query_dp_alt_from_dmub(struct link_encoder *enc,
+ union dmub_rb_cmd *cmd)
{
struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
- uint32_t dp_alt_mode_disable = 0;
- bool is_usb_c_alt_mode = false;
- if (enc->features.flags.bits.DP_IS_USB_C) {
- /* if value == 1 alt mode is disabled, otherwise it is enabled
*/
- REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE,
&dp_alt_mode_disable);
- is_usb_c_alt_mode = (dp_alt_mode_disable == 0);
- }
+ memset(cmd, 0, sizeof(*cmd));
+ cmd->query_dp_alt.header.type = DMUB_CMD__VBIOS;
+ cmd->query_dp_alt.header.sub_type =
+ DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT;
+ cmd->query_dp_alt.header.payload_bytes = sizeof(cmd->query_dp_alt.data);
+ cmd->query_dp_alt.data.phy_id =
phy_id_from_transmitter(enc10->base.transmitter);
+
+ if (!dc_wake_and_execute_dmub_cmd(enc->ctx, cmd,
DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))
+ return false;
- return is_usb_c_alt_mode;
+ return true;
}
-static void dcn32_link_encoder_get_max_link_cap(struct link_encoder *enc,
+bool dcn32_link_encoder_is_in_alt_mode(struct link_encoder *enc)
+{
+ union dmub_rb_cmd cmd;
+
+ if (!query_dp_alt_from_dmub(enc, &cmd))
+ return false;
+
+ return (cmd.query_dp_alt.data.is_dp_alt_disable == 0);
+}
+
+void dcn32_link_encoder_get_max_link_cap(struct link_encoder *enc,
struct dc_link_settings *link_settings)
{
- struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
- uint32_t is_in_usb_c_dp4_mode = 0;
+ union dmub_rb_cmd cmd;
dcn10_link_encoder_get_max_link_cap(enc, link_settings);
- /* in usb c dp2 mode, max lane count is 2 */
- if (enc->funcs->is_in_alt_mode && enc->funcs->is_in_alt_mode(enc)) {
- REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DP4,
&is_in_usb_c_dp4_mode);
- if (!is_in_usb_c_dp4_mode)
- link_settings->lane_count = MIN(LANE_COUNT_TWO,
link_settings->lane_count);
- }
+ if (!query_dp_alt_from_dmub(enc, &cmd))
+ return;
+ if (cmd.query_dp_alt.data.is_usb &&
+ cmd.query_dp_alt.data.is_dp4 == 0)
+ link_settings->lane_count = MIN(LANE_COUNT_TWO,
link_settings->lane_count);
}
+
static const struct link_encoder_funcs dcn32_link_enc_funcs = {
.read_state = link_enc2_read_state,
.validate_output_with_stream =
@@ -203,13 +248,15 @@ void dcn32_link_encoder_construct(
[PATCH 07/17] drm/amd/display: Only allow dig mapping to pwrseq in new asic
From: Lewis Huang
[Why]
The old asic only have 1 pwrseq hw.
We don't need to map the diginst to pwrseq inst in old asic.
[How]
1. Only mapping dig to pwrseq for new asic.
2. Move mapping function into dcn specific panel control component
Cc: Stable # v6.6+
Cc: Mario Limonciello
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3122
Reviewed-by: Anthony Koo
Acked-by: Rodrigo Siqueira
Signed-off-by: Lewis Huang
---
.../drm/amd/display/dc/dce/dce_panel_cntl.c | 1 +
.../amd/display/dc/dcn301/dcn301_panel_cntl.c | 1 +
.../amd/display/dc/dcn31/dcn31_panel_cntl.c | 18 -
.../drm/amd/display/dc/inc/hw/panel_cntl.h| 2 +-
.../drm/amd/display/dc/link/link_factory.c| 26 +--
5 files changed, 21 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
index e8570060d007..5bca67407c5b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
@@ -290,4 +290,5 @@ void dce_panel_cntl_construct(
dce_panel_cntl->base.funcs = &dce_link_panel_cntl_funcs;
dce_panel_cntl->base.ctx = init_data->ctx;
dce_panel_cntl->base.inst = init_data->inst;
+ dce_panel_cntl->base.pwrseq_inst = 0;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
index ad0df1a72a90..9e96a3ace207 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
@@ -215,4 +215,5 @@ void dcn301_panel_cntl_construct(
dcn301_panel_cntl->base.funcs = &dcn301_link_panel_cntl_funcs;
dcn301_panel_cntl->base.ctx = init_data->ctx;
dcn301_panel_cntl->base.inst = init_data->inst;
+ dcn301_panel_cntl->base.pwrseq_inst = 0;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c
index 03248422d6ff..281be20b1a10 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c
@@ -154,8 +154,24 @@ void dcn31_panel_cntl_construct(
struct dcn31_panel_cntl *dcn31_panel_cntl,
const struct panel_cntl_init_data *init_data)
{
+ uint8_t pwrseq_inst = 0xF;
+
dcn31_panel_cntl->base.funcs = &dcn31_link_panel_cntl_funcs;
dcn31_panel_cntl->base.ctx = init_data->ctx;
dcn31_panel_cntl->base.inst = init_data->inst;
- dcn31_panel_cntl->base.pwrseq_inst = init_data->pwrseq_inst;
+
+ switch (init_data->eng_id) {
+ case ENGINE_ID_DIGA:
+ pwrseq_inst = 0;
+ break;
+ case ENGINE_ID_DIGB:
+ pwrseq_inst = 1;
+ break;
+ default:
+ DC_LOG_WARNING("Unsupported pwrseq engine id: %d!\n",
init_data->eng_id);
+ ASSERT(false);
+ break;
+ }
+
+ dcn31_panel_cntl->base.pwrseq_inst = pwrseq_inst;
}
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h
b/drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h
index 5dcbaa2db964..e97d964a1791 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h
@@ -57,7 +57,7 @@ struct panel_cntl_funcs {
struct panel_cntl_init_data {
struct dc_context *ctx;
uint32_t inst;
- uint32_t pwrseq_inst;
+ uint32_t eng_id;
};
struct panel_cntl {
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.c
b/drivers/gpu/drm/amd/display/dc/link/link_factory.c
index 37d3027c32dc..cf22b8f28ba6 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c
@@ -370,30 +370,6 @@ static enum transmitter translate_encoder_to_transmitter(
}
}
-static uint8_t translate_dig_inst_to_pwrseq_inst(struct dc_link *link)
-{
- uint8_t pwrseq_inst = 0xF;
- struct dc_context *dc_ctx = link->dc->ctx;
-
- DC_LOGGER_INIT(dc_ctx->logger);
-
- switch (link->eng_id) {
- case ENGINE_ID_DIGA:
- pwrseq_inst = 0;
- break;
- case ENGINE_ID_DIGB:
- pwrseq_inst = 1;
- break;
- default:
- DC_LOG_WARNING("Unsupported pwrseq engine id: %d!\n",
link->eng_id);
- ASSERT(false);
- break;
- }
-
- return pwrseq_inst;
-}
-
-
static void link_destruct(struct dc_link *link)
{
int i;
@@ -657,7 +633,7 @@ static bool construct_phy(struct dc_link *link,
link->link_id.id == CONNECTOR_ID_LVDS)) {
panel_cntl_init_data.ctx = dc_ctx;
panel_cntl_init_data.inst =
panel_cntl_i
[PATCH 08/17] drm/amd/display: Fix S4 hang polling on HW power up done for VBIOS DMCUB
From: Nicholas Kazlauskas
[Why]
VBIOS DMCUB firmware doesn't set the dal_fw bit and we end up hanging
waiting for HW power up done because of it.
[How]
Simplify the path and allow mailbox_rdy to be a functional check when
we detect VBIOS firmware.
Reviewed-by: Charlene Liu
Acked-by: Rodrigo Siqueira
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c | 8 +++-
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 9 +
2 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
index 60223efc6fc8..53f359f3fae2 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
@@ -555,8 +555,14 @@ uint32_t dmub_dcn35_read_inbox0_ack_register(struct
dmub_srv *dmub)
bool dmub_dcn35_is_hw_powered_up(struct dmub_srv *dmub)
{
union dmub_fw_boot_status status;
+ uint32_t is_enable;
+
+ REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enable);
+ if (is_enable == 0)
+ return false;
status.all = REG_READ(DMCUB_SCRATCH0);
- return status.bits.hw_power_init_done;
+ return (status.bits.dal_fw && status.bits.hw_power_init_done &&
status.bits.mailbox_rdy) ||
+ (!status.bits.dal_fw && status.bits.mailbox_rdy);
}
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index fb66832dc996..cd97983cf759 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -800,20 +800,13 @@ enum dmub_status dmub_srv_cmd_execute(struct dmub_srv
*dmub)
bool dmub_srv_is_hw_pwr_up(struct dmub_srv *dmub)
{
- union dmub_fw_boot_status status;
-
if (!dmub->hw_funcs.is_hw_powered_up)
return true;
if (!dmub->hw_funcs.is_hw_powered_up(dmub))
return false;
- if (!dmub->hw_funcs.is_hw_init(dmub))
- return false;
-
- status = dmub->hw_funcs.get_fw_status(dmub);
-
- return status.bits.dal_fw && status.bits.mailbox_rdy;
+ return true;
}
enum dmub_status dmub_srv_wait_for_hw_pwr_up(struct dmub_srv *dmub,
--
2.43.0
[PATCH 10/17] drm/amd/display: Generalize new minimal transition path
From: Alvin Lee
Previously the new minimal transition path was only used for windowed
MPO + ODM for plane scaling updates. However, we want to generalize the
transition for all cases whenever a non-seamless transition is detected
(such as for MPO -> SubVP + MPC).
To make this change we add pointers in the plane state, stream, and
pointers in the stream state to the dc_scratch state and backup and
restore these so the minimal transition can take place successfully.
Reviewed-by: Wenjing Liu
Acked-by: Rodrigo Siqueira
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 146 +++---
.../gpu/drm/amd/display/dc/inc/core_types.h | 31 ++--
2 files changed, 77 insertions(+), 100 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 4d5194293dbd..5211c1c0f3c0 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2032,7 +2032,7 @@ static enum dc_status dc_commit_state_no_check(struct dc
*dc, struct dc_state *c
return result;
}
-static bool commit_minimal_transition_state(struct dc *dc,
+static bool commit_minimal_transition_state_legacy(struct dc *dc,
struct dc_state *transition_base_context);
/**
@@ -2098,7 +2098,7 @@ enum dc_status dc_commit_streams(struct dc *dc,
}
if (handle_exit_odm2to1)
- res = commit_minimal_transition_state(dc, dc->current_state);
+ res = commit_minimal_transition_state_legacy(dc,
dc->current_state);
context = dc_state_create_current_copy(dc);
if (!context)
@@ -2952,8 +2952,8 @@ static void copy_stream_update_to_stream(struct dc *dc,
}
}
-static void backup_plane_states_for_stream(
- struct dc_plane_state plane_states[MAX_SURFACE_NUM],
+static void backup_planes_and_stream_state(
+ struct dc_scratch_space *scratch,
struct dc_stream_state *stream)
{
int i;
@@ -2962,12 +2962,20 @@ static void backup_plane_states_for_stream(
if (!status)
return;
- for (i = 0; i < status->plane_count; i++)
- plane_states[i] = *status->plane_states[i];
+ for (i = 0; i < status->plane_count; i++) {
+ scratch->plane_states[i] = *status->plane_states[i];
+ scratch->gamma_correction[i] =
*status->plane_states[i]->gamma_correction;
+ scratch->in_transfer_func[i] =
*status->plane_states[i]->in_transfer_func;
+ scratch->lut3d_func[i] = *status->plane_states[i]->lut3d_func;
+ scratch->in_shaper_func[i] =
*status->plane_states[i]->in_shaper_func;
+ scratch->blend_tf[i] = *status->plane_states[i]->blend_tf;
+ }
+ scratch->stream_state = *stream;
+ scratch->out_transfer_func = *stream->out_transfer_func;
}
-static void restore_plane_states_for_stream(
- struct dc_plane_state plane_states[MAX_SURFACE_NUM],
+static void restore_planes_and_stream_state(
+ struct dc_scratch_space *scratch,
struct dc_stream_state *stream)
{
int i;
@@ -2976,8 +2984,16 @@ static void restore_plane_states_for_stream(
if (!status)
return;
- for (i = 0; i < status->plane_count; i++)
- *status->plane_states[i] = plane_states[i];
+ for (i = 0; i < status->plane_count; i++) {
+ *status->plane_states[i] = scratch->plane_states[i];
+ *status->plane_states[i]->gamma_correction =
scratch->gamma_correction[i];
+ *status->plane_states[i]->in_transfer_func =
scratch->in_transfer_func[i];
+ *status->plane_states[i]->lut3d_func = scratch->lut3d_func[i];
+ *status->plane_states[i]->in_shaper_func =
scratch->in_shaper_func[i];
+ *status->plane_states[i]->blend_tf = scratch->blend_tf[i];
+ }
+ *stream = scratch->stream_state;
+ *stream->out_transfer_func = scratch->out_transfer_func;
}
static bool update_planes_and_stream_state(struct dc *dc,
@@ -3003,7 +3019,7 @@ static bool update_planes_and_stream_state(struct dc *dc,
}
context = dc->current_state;
- backup_plane_states_for_stream(dc->current_state->scratch.plane_states,
stream);
+ backup_planes_and_stream_state(&dc->current_state->scratch, stream);
update_type = dc_check_update_surfaces_for_stream(
dc, srf_updates, surface_count, stream_update,
stream_status);
@@ -3103,7 +3119,7 @@ static bool update_planes_and_stream_state(struct dc *dc,
*new_context = context;
*new_update_type = update_type;
- backup_plane_states_for_stream(context->scratch.plane_states,
[PATCH 13/17] drm/amd/display: Remove pixle rate limit for subvp
From: Alvin Lee Subvp bugs related to 8K60 have been fixed, so remove the limit that blocks 8K60 timings from enabling SubVP. Reviewed-by: Nevenko Stupar Reviewed-by: Chaitanya Dhere Acked-by: Rodrigo Siqueira Signed-off-by: Alvin Lee --- drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c index a0a65e099104..b49e1dc9d8ba 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c @@ -623,7 +623,6 @@ static bool dcn32_assign_subvp_pipe(struct dc *dc, * - Not TMZ surface */ if (pipe->plane_state && !pipe->top_pipe && !dcn32_is_center_timing(pipe) && - !(pipe->stream->timing.pix_clk_100hz / 1 > DCN3_2_MAX_SUBVP_PIXEL_RATE_MHZ) && (!dcn32_is_psr_capable(pipe) || (context->stream_count == 1 && dc->caps.dmub_caps.subvp_psr)) && dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_NONE && (refresh_rate < 120 || dcn32_allow_subvp_high_refresh_rate(dc, context, pipe)) && -- 2.43.0
[PATCH 11/17] drm/amd/display: fix input states translation error for dcn35 & dcn351
From: Swapnil Patel
[Why]
Currently there is an error while translating input clock sates into
output clock states. The highest fclk setting from output sates is
being dropped because of this error.
[How]
For dcn35 and dcn351, make output_states equal to input states.
Reviewed-by: Charlene Liu
Acked-by: Rodrigo Siqueira
Signed-off-by: Swapnil Patel
---
.../drm/amd/display/dc/dml2/dml2_translation_helper.c| 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
index 23a608274096..1ba6933d2b36 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
@@ -398,7 +398,6 @@ void dml2_init_soc_states(struct dml2_context *dml2, const
struct dc *in_dc,
/* Copy clocks tables entries, if available */
if (dml2->config.bbox_overrides.clks_table.num_states) {
p->in_states->num_states =
dml2->config.bbox_overrides.clks_table.num_states;
-
for (i = 0; i <
dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels;
i++) {
p->in_states->state_array[i].dcfclk_mhz =
dml2->config.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz;
}
@@ -437,6 +436,14 @@ void dml2_init_soc_states(struct dml2_context *dml2, const
struct dc *in_dc,
}
dml2_policy_build_synthetic_soc_states(s, p);
+ if (dml2->v20.dml_core_ctx.project == dml_project_dcn35 ||
+ dml2->v20.dml_core_ctx.project == dml_project_dcn351) {
+ // Override last out_state with data from last in_state
+ // This will ensure that out_state contains max fclk
+ memcpy(&p->out_states->state_array[p->out_states->num_states -
1],
+
&p->in_states->state_array[p->in_states->num_states - 1],
+ sizeof(struct soc_state_bounding_box_st));
+ }
}
void dml2_translate_ip_params(const struct dc *in, struct ip_params_st *out)
--
2.43.0
[PATCH 14/17] drm/amd/display: reenable windowed mpo odm support on dcn32 and dcn321
From: Wenjing Liu
[why]
The feature was disabled due to regression found during testing. Now
that all the pending issues are addressed, we are reenabling the power
saving feature again.
The feature optimizes dispclk level when user is using MPO capable
broswers or watching MPO capable videos in windowed mode. The feature
achieves power optimization by utilizing free pipes to process incoming
pixels in parallel. So it reduces max dispclk requirements for each
pipe.
Previously ODM power optimization will be disabled when MPO plane is
present due to technical challeges. This is mainly because ODM divides
pixel workload with respect to stream but MPO plane position and size
are arbitrary with respect to stream. The pixel processing workload of
an MPO plane is not guarenteed to be evenly distributed across DCN pipes.
For example if a plane is moved inside single ODM slice, all the
processing for the plane is distributed to the pipe in the current ODM
slice, while the other ODM slices don't need to process this plane. If
the plane is then moved to the middle crosing two ODM slices, each ODM
slice gets half of the workload. This is especially difficult when the
plane itself has a large source rect which can't be processed by single
DCN pipe. In this case we can't enable ODM power optimization when the
plane is only within one ODM slice.
[how]
To overcome the challeges, new pipe resource management is in place to
make sure a plane is validated with ODM power optimization support if
it can be validated regardless of its position and the same pipe
topology can be used regardless of the plane's position. When the plane
is moved outside current ODM slice, we will set recout to 0 so the pipe
can be idling without the need to update pipe topology. When the user
resizes a plane, it may result in downscaling ratio changes. When the
downscaling ratio is above single pipe's threshold, we will seamlessly
exit ODM power optimization and applies MPC combine to support the plane.
when downscaling ratio becomes smaller, we will seamlessly enter ODM
power optimization again. All these pipe transitions happen
automatically and quietly when the conditions are met without any visual
impacts to the user.
Reviewed-by: Martin Leung
Acked-by: Rodrigo Siqueira
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c | 1 +
.../gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c| 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
index 6f10052caeef..3f3951f3ba98 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
@@ -2118,6 +2118,7 @@ static bool dcn32_resource_construct(
dc->config.use_pipe_ctx_sync_logic = true;
dc->config.dc_mode_clk_limit_support = true;
+ dc->config.enable_windowed_mpo_odm = true;
/* read VBIOS LTTPR caps */
{
if (ctx->dc_bios->funcs->get_lttpr_caps) {
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
index 6f832bf278cf..b356fed1726d 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
@@ -1760,7 +1760,7 @@ static bool dcn321_resource_construct(
dc->caps.color.mpc.ocsc = 1;
dc->config.dc_mode_clk_limit_support = true;
- dc->config.enable_windowed_mpo_odm = false;
+ dc->config.enable_windowed_mpo_odm = true;
/* read VBIOS LTTPR caps */
{
if (ctx->dc_bios->funcs->get_lttpr_caps) {
--
2.43.0
[PATCH 12/17] drm/amd/display: Only log during optimize_bandwidth call
From: Ethan Bitnun
Prevent logs during a prepare_bandwidth call to ensure log accuracy.
Reviewed-by: Alvin Lee
Acked-by: Rodrigo Siqueira
Signed-off-by: Ethan Bitnun
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index ee5e7512a7ee..668f05c8654e 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -815,7 +815,7 @@ static void dcn32_update_clocks(struct clk_mgr
*clk_mgr_base,
dmcu->funcs->set_psr_wait_loop(dmcu,
clk_mgr_base->clks.dispclk_khz / 1000 / 7);
- if (dc->config.enable_auto_dpm_test_logs) {
+ if (dc->config.enable_auto_dpm_test_logs && safe_to_lower) {
dcn32_auto_dpm_test_log(new_clocks, clk_mgr, context);
}
}
--
2.43.0
[PATCH 16/17] drm/amd/display: Fix nanosec stat overflow
From: Aric Cyr [Why] Nanosec stats can overflow on long running systems potentially causing statistic logging issues. [How] Use 64bit types for nanosec stats to ensure no overflow. Reviewed-by: Rodrigo Siqueira Signed-off-by: Aric Cyr --- drivers/gpu/drm/amd/display/modules/inc/mod_stats.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_stats.h b/drivers/gpu/drm/amd/display/modules/inc/mod_stats.h index 5960dd760e91..8ce6c22e5d04 100644 --- a/drivers/gpu/drm/amd/display/modules/inc/mod_stats.h +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_stats.h @@ -57,10 +57,10 @@ void mod_stats_update_event(struct mod_stats *mod_stats, unsigned int length); void mod_stats_update_flip(struct mod_stats *mod_stats, - unsigned long timestamp_in_ns); + unsigned long long timestamp_in_ns); void mod_stats_update_vupdate(struct mod_stats *mod_stats, - unsigned long timestamp_in_ns); + unsigned long long timestamp_in_ns); void mod_stats_update_freesync(struct mod_stats *mod_stats, unsigned int v_total_min, -- 2.43.0
[PATCH 15/17] drm/amd/display: Drop unnecessary header
A long time ago, the slab header was added to multiple files in DC. We also included it in the os_types.h, which is included in many of those DC files. At this point, there is no need to insert the slab.h header in multiple files, so this commit drops those includes. Signed-off-by: Rodrigo Siqueira --- drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c | 2 -- drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 2 -- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c | 2 -- drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c | 2 -- drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c | 2 -- drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c | 2 -- drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c | 2 -- 7 files changed, 14 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c index 39530b2ea495..b30c2cdc1a61 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c @@ -23,8 +23,6 @@ * */ -#include - #include "resource.h" #include "dm_services.h" #include "dce_calcs.h" diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c index 86ee4fe4f5e3..9f0f25aee426 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c @@ -23,8 +23,6 @@ * */ -#include - #include "dal_asic_id.h" #include "dc_types.h" #include "dccg.h" diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c index 60761ff3cbf1..2a74e2d74909 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c @@ -23,8 +23,6 @@ * */ -#include - #include "reg_helper.h" #include "core_types.h" #include "clk_mgr_internal.h" diff --git a/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c b/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c index 25ffc052d53b..99e17c164ce7 100644 --- a/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c +++ b/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c @@ -23,8 +23,6 @@ * */ -#include - #include "dm_services.h" #include "dm_helpers.h" #include "include/hdcp_msg_types.h" diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c b/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c index e8baafa02443..916f0c974637 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c @@ -23,8 +23,6 @@ * */ -#include - #include "dm_services.h" #include "include/logger_interface.h" diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c b/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c index 03c5e8ff8cbd..42cdfe6c3538 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c @@ -23,8 +23,6 @@ * */ -#include - #include "dm_services.h" #include "include/logger_interface.h" diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c index f9c5bc624be3..a2387cea1af9 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c @@ -24,8 +24,6 @@ * */ -#include - #include "dm_services.h" #include "dc.h" -- 2.43.0
[PATCH 17/17] drm/amd/display: 3.2.273
From: Aric Cyr This version brings along the following: - Re-enable windowed MPO support for DCN32/321 - Improvements in the subvp feature - Code clean up - USB4 fixes Acked-by: Rodrigo Siqueira Signed-off-by: Aric Cyr --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 9b42f6fc8c69..ee8453bf958f 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -51,7 +51,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.272" +#define DC_VER "3.2.273" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.43.0
[PATCH v5 0/8] drm/amd/display: Introduce KUnit to Display Mode Library
In 2022, we got a great patchset from a GSoC project introducing unit tests to the amdgpu display. Since version 3, this effort was put on hold, and now I'm attempting to revive it. I'll add part of the original cover letter at the bottom of this cover letter, but you can read all the original messages at: https://lore.kernel.org/amd-gfx/20220912155919.39877-1-mairaca...@riseup.net/ Changes since V3: - Rebase and adjust conflicts. - Rewrite part of the dc_dmub_srv_test to represent a real scenario that simulates some parameter configuration for using 4k144 and 4k240 displays. Changes since v4: - Rebase. - Change the folder organization to better align with the display code. - Fix the wrong CONFIG used in the FPU code. - Drop unstable tests. Thanks Siqueira Original cover letter Hello, This series is version 3 of the introduction of unit testing to the AMDPGU driver [1]. Our main goal is to bring unit testing to the AMD display driver; in particular, we'll focus on the Display Mode Library (DML) for DCN2.0, DMUB, and some of the DCE functions. This implementation intends to help developers to recognize bugs before they are merged into the mainline and also makes it possible for future code refactors of the AMD display driver. For the implementation of the tests, we decided to go with the Kernel Unit Testing Framework (KUnit). KUnit makes it possible to run test suites on kernel boot or load the tests as a module. It reports all test case results through a TAP (Test Anything Protocol) in the kernel log. Moreover, KUnit unifies the test structure and provides tools to simplify the testing for developers and CI systems. In regards to CI pipelines, we believe kunit_tool [2] provides ease of use, but we are also working on integrating KUnit into IGT [3]. Since the second version, we've chosen a mix of approaches to integrate KUnit tests into amdgpu: 1. Tests that use static functions are included through guards [4]. 2. Tests without static functions are included through a Makefile. We understand that testing static functions is not ideal, but taking into consideration that this driver relies heavily on static functions with complex behavior which would benefit from unit testing, otherwise, black-box tested through public functions with dozens of arguments and sometimes high cyclomatic complexity. The first seven patches represent what we intend to do for the rest of the DML modules: systematic testing of the DML functions, especially mathematically complicated functions. Also, it shows how simple it is to add new tests to the DML. Among the tests, we highlight the dcn20_fpu_test, which, had it existed then, could catch the defects introduced to dcn20_fpu.c by 8861c27a6c [5] later fixed by 9ad5d02c2a [6]. In this series, there's also an example of how unit tests can help avoid regressions and keep track of changes in behavior. [..] Isabella Basso (1): drm/amd/display: Introduce KUnit tests to display_rq_dlg_calc_20 Magali Lemes (1): drm/amd/display: Introduce KUnit tests for dcn20_fpu MaÃra Canal (5): drm/amd/display: Introduce KUnit tests to the bw_fixed library drm/amd/display: Introduce KUnit tests to the display_mode_vba library drm/amd/display: Introduce KUnit to dcn20/display_mode_vba_20 library drm/amd/display: Introduce KUnit tests to dc_dmub_srv library Documentation/gpu: Add Display Core Unit Test documentation Tales Aparecida (1): drm/amd/display: Introduce KUnit tests for fixed31_32 library .../gpu/amdgpu/display/display-test.rst | 88 ++ Documentation/gpu/amdgpu/display/index.rst| 1 + drivers/gpu/drm/amd/display/Kconfig | 52 ++ drivers/gpu/drm/amd/display/Makefile | 2 +- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 4 + .../dc/dml/dcn20/display_mode_vba_20.c| 4 + .../dc/dml/dcn20/display_rq_dlg_calc_20.c | 4 + .../drm/amd/display/test/kunit/.kunitconfig | 9 + .../gpu/drm/amd/display/test/kunit/Makefile | 18 + .../test/kunit/dc/basics/fixpt31_32_test.c| 232 ++ .../display/test/kunit/dc/dc_dmub_srv_test.c | 159 .../test/kunit/dc/dml/calcs/bw_fixed_test.c | 323 .../test/kunit/dc/dml/dcn20/dcn20_fpu_test.c | 561 + .../dc/dml/dcn20/display_mode_vba_20_test.c | 780 ++ .../dml/dcn20/display_rq_dlg_calc_20_test.c | 124 +++ .../test/kunit/dc/dml/display_mode_vba_test.c | 741 + 16 files changed, 3101 insertions(+), 1 deletion(-) create mode 100644 Documentation/gpu/amdgpu/display/display-test.rst create mode 100644 drivers/gpu/drm/amd/display/test/kunit/.kunitconfig create mode 100644 drivers/gpu/drm/amd/display/test/kunit/Makefile create mode 100644 drivers/gpu/drm/amd/display/test/kunit/dc/basics/fixpt31_32_test.c create mode 100644 drivers/gpu/drm/amd/display/test/kunit/dc/dc_dmub_srv_test.c create mode 100644 drivers/gpu/drm/amd/display/test/kunit/dc/dml/calcs/bw_fixed_test.c create mode 100644 dr
[PATCH v5 1/8] drm/amd/display: Introduce KUnit tests for fixed31_32 library
From: Tales Aparecida
The fixed31_32 library performs a lot of the mathematical operations
involving fixed-point arithmetic and the conversion of integers to
fixed-point representation.
This unit tests intend to assure the proper functioning of the basic
mathematical operations of fixed-point arithmetic, such as
multiplication, conversion from fractional to fixed-point number,
and more. Use kunit_tool to run:
$ ./tools/testing/kunit/kunit.py run --arch=x86_64 \
--kunitconfig=drivers/gpu/drm/amd/display/test/kunit
Reviewed-by: David Gow
Signed-off-by: Tales Aparecida
Signed-off-by: MaÃra Canal
---
drivers/gpu/drm/amd/display/Kconfig | 13 +
drivers/gpu/drm/amd/display/Makefile | 2 +-
.../drm/amd/display/test/kunit/.kunitconfig | 6 +
.../gpu/drm/amd/display/test/kunit/Makefile | 12 +
.../test/kunit/dc/basics/fixpt31_32_test.c| 232 ++
5 files changed, 264 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/display/test/kunit/.kunitconfig
create mode 100644 drivers/gpu/drm/amd/display/test/kunit/Makefile
create mode 100644
drivers/gpu/drm/amd/display/test/kunit/dc/basics/fixpt31_32_test.c
diff --git a/drivers/gpu/drm/amd/display/Kconfig
b/drivers/gpu/drm/amd/display/Kconfig
index 901d1961b739..e35eef026097 100644
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -51,4 +51,17 @@ config DRM_AMD_SECURE_DISPLAY
This option enables the calculation of crc of specific region via
debugfs. Cooperate with specific DMCU FW.
+config AMD_DC_BASICS_KUNIT_TEST
+ bool "Enable KUnit tests for the 'basics' sub-component of DAL" if
!KUNIT_ALL_TESTS
+ depends on DRM_AMD_DC && KUNIT
+ default KUNIT_ALL_TESTS
+ help
+ Enables unit tests for the Display Core. Only useful for kernel
+ devs running KUnit.
+
+ For more information on KUnit and unit tests in general please
refer to
+ the KUnit documentation in Documentation/dev-tools/kunit/.
+
+ If unsure, say N.
+
endmenu
diff --git a/drivers/gpu/drm/amd/display/Makefile
b/drivers/gpu/drm/amd/display/Makefile
index 92a5c5efcf92..5e11ee266028 100644
--- a/drivers/gpu/drm/amd/display/Makefile
+++ b/drivers/gpu/drm/amd/display/Makefile
@@ -45,7 +45,7 @@ subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/hdcp
#TODO: remove when Timing Sync feature is complete
subdir-ccflags-y += -DBUILD_FEATURE_TIMING_SYNC=0
-DAL_LIBS = amdgpu_dm dcmodules/freesync modules/color
modules/info_packet modules/power dmub/src
+DAL_LIBS = amdgpu_dm dcmodules/freesync modules/color
modules/info_packet modules/power dmub/src test/kunit
DAL_LIBS += modules/hdcp
diff --git a/drivers/gpu/drm/amd/display/test/kunit/.kunitconfig
b/drivers/gpu/drm/amd/display/test/kunit/.kunitconfig
new file mode 100644
index ..862e6506ddd3
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/test/kunit/.kunitconfig
@@ -0,0 +1,6 @@
+CONFIG_KUNIT=y
+CONFIG_PCI=y
+CONFIG_DRM=y
+CONFIG_DRM_AMDGPU=y
+CONFIG_DRM_AMD_DC=y
+CONFIG_AMD_DC_BASICS_KUNIT_TEST=y
diff --git a/drivers/gpu/drm/amd/display/test/kunit/Makefile
b/drivers/gpu/drm/amd/display/test/kunit/Makefile
new file mode 100644
index ..84b22ecb98df
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/test/kunit/Makefile
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: MIT
+#
+# Makefile for the KUnit Tests for DC
+#
+
+ifdef CONFIG_AMD_DC_BASICS_KUNIT_TEST
+ DC_TESTS += dc/basics/fixpt31_32_test.o
+endif
+
+AMD_DAL_DC_TESTS = $(addprefix $(AMDDALPATH)/test/kunit/,$(DC_TESTS))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_DC_TESTS)
diff --git a/drivers/gpu/drm/amd/display/test/kunit/dc/basics/fixpt31_32_test.c
b/drivers/gpu/drm/amd/display/test/kunit/dc/basics/fixpt31_32_test.c
new file mode 100644
index ..2fc489203499
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/test/kunit/dc/basics/fixpt31_32_test.c
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: MIT
+/* Unit tests for display/include/fixed31_32.h and dc/basics/fixpt31_32.c
+ *
+ * Copyright (C) 2022, Tales Aparecida
+ */
+
+#include
+#include "os_types.h"
+#include "fixed31_32.h"
+
+static const struct fixed31_32 dc_fixpt_minus_one = { -0x1LL };
+
+/**
+ * dc_fixpt_from_int_test - KUnit test for dc_fixpt_from_int
+ * @test: represents a running instance of a test.
+ */
+static void dc_fixpt_from_int_test(struct kunit *test)
+{
+ struct fixed31_32 res;
+
+ res = dc_fixpt_from_int(0);
+ KUNIT_EXPECT_EQ(test, res.value, dc_fixpt_zero.value);
+
+ res = dc_fixpt_from_int(1);
+ KUNIT_EXPECT_EQ(test, res.value, dc_fixpt_one.value);
+
+ res = dc_fixpt_from_int(-1);
+ KUNIT_EXPECT_EQ(test, res.value, -dc_fixpt_one.value);
+
+ res = dc_fixpt_from_int(INT_MAX);
+ KUNIT_EXPECT_EQ(test, res.value, 0x7FFFLL);
+
+ res = dc_fixpt_from_int(INT_MIN);
+ KUNIT_EXPECT_EQ(
[PATCH v5 3/8] drm/amd/display: Introduce KUnit tests to display_rq_dlg_calc_20
From: Isabella Basso
This adds tests to the bit encoding format verification functions on the
file. They're meant to be simpler so as to provide a proof of concept on
testing DML code.
Change since v4:
- Use DRM_AMD_DC_FP guard for FPU tests
Signed-off-by: Isabella Basso
Signed-off-by: MaÃra Canal
---
drivers/gpu/drm/amd/display/Kconfig | 13 ++
.../dc/dml/dcn20/display_rq_dlg_calc_20.c | 4 +
.../drm/amd/display/test/kunit/.kunitconfig | 1 +
.../dml/dcn20/display_rq_dlg_calc_20_test.c | 124 ++
4 files changed, 142 insertions(+)
create mode 100644
drivers/gpu/drm/amd/display/test/kunit/dc/dml/dcn20/display_rq_dlg_calc_20_test.c
diff --git a/drivers/gpu/drm/amd/display/Kconfig
b/drivers/gpu/drm/amd/display/Kconfig
index d54036dcac78..ab52b135db85 100644
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -64,6 +64,19 @@ config DCE_KUNIT_TEST
If unsure, say N.
+config DML_KUNIT_TEST
+ bool "Run all KUnit tests for DML" if !KUNIT_ALL_TESTS
+ depends on DRM_AMD_DC_FP && KUNIT
+ default KUNIT_ALL_TESTS
+ help
+ Enables unit tests for the Display Controller Engine. Only
useful for kernel
+ devs running KUnit.
+
+ For more information on KUnit and unit tests in general please
refer to
+ the KUnit documentation in Documentation/dev-tools/kunit/.
+
+ If unsure, say N.
+
config AMD_DC_BASICS_KUNIT_TEST
bool "Enable KUnit tests for the 'basics' sub-component of DAL" if
!KUNIT_ALL_TESTS
depends on DRM_AMD_DC && KUNIT
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
index 548cdef8a8ad..45f75a7f84c7 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
@@ -1683,3 +1683,7 @@ static void calculate_ttu_cursor(struct display_mode_lib
*mode_lib,
ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13));
}
}
+
+#if IS_ENABLED(CONFIG_DML_KUNIT_TEST)
+#include "../../../test/kunit/dc/dml/dcn20/display_rq_dlg_calc_20_test.c"
+#endif
diff --git a/drivers/gpu/drm/amd/display/test/kunit/.kunitconfig
b/drivers/gpu/drm/amd/display/test/kunit/.kunitconfig
index 7a58f75a8dfc..eb6f81601757 100644
--- a/drivers/gpu/drm/amd/display/test/kunit/.kunitconfig
+++ b/drivers/gpu/drm/amd/display/test/kunit/.kunitconfig
@@ -5,3 +5,4 @@ CONFIG_DRM_AMDGPU=y
CONFIG_DRM_AMD_DC=y
CONFIG_AMD_DC_BASICS_KUNIT_TEST=y
CONFIG_DCE_KUNIT_TEST=y
+CONFIG_DML_KUNIT_TEST=y
diff --git
a/drivers/gpu/drm/amd/display/test/kunit/dc/dml/dcn20/display_rq_dlg_calc_20_test.c
b/drivers/gpu/drm/amd/display/test/kunit/dc/dml/dcn20/display_rq_dlg_calc_20_test.c
new file mode 100644
index ..e6d3e356205c
--- /dev/null
+++
b/drivers/gpu/drm/amd/display/test/kunit/dc/dml/dcn20/display_rq_dlg_calc_20_test.c
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: MIT
+/*
+ * KUnit tests for dml/dcn20/display_rq_dlg_calc_20.c
+ *
+ * Copyright (c) 2022, Isabella Basso
+ */
+
+#include
+#include "dml/display_mode_lib.h"
+
+/**
+ * get_bytes_per_element_test - KUnit test for get_bytes_per_element
+ * @test: represents a running instance of a test.
+ */
+static void get_bytes_per_element_test(struct kunit *test)
+{
+ /* last numbers should tell us the horizontal 4-element region binary
+* size N used for subsampling, thus giving us N/8 bytes per element
+*/
+ /* note that 4:4:4 is not subsampled */
+ KUNIT_ASSERT_EQ(test, get_bytes_per_element(dm_444_16, false), 2);
+ KUNIT_ASSERT_EQ(test, get_bytes_per_element(dm_444_32, false), 4);
+ KUNIT_ASSERT_EQ(test, get_bytes_per_element(dm_444_64, false), 8);
+
+ /* dcn20 doesn't support bit depths over 10b */
+ KUNIT_ASSERT_EQ(test, get_bytes_per_element(dm_420_12, false), 0);
+ KUNIT_ASSERT_EQ(test, get_bytes_per_element(dm_420_12, true), 0);
+
+ /* dm_444_XX are not dual plane */
+ KUNIT_ASSERT_EQ(test, get_bytes_per_element(dm_444_16, true), 0);
+ KUNIT_ASSERT_EQ(test, get_bytes_per_element(dm_444_32, true), 0);
+ KUNIT_ASSERT_EQ(test, get_bytes_per_element(dm_444_64, true), 0);
+
+ /* in the dm_42* values, last numbers specify bit depth, demanding we
+* treat chroma and luma channels separately
+*/
+ /* thus we'll now have ceil(N/8) bytes for luma */
+ KUNIT_ASSERT_EQ(test, get_bytes_per_element(dm_420_8, false), 1);
+ KUNIT_ASSERT_EQ(test, get_bytes_per_element(dm_420_10, false), 2);
+ /* and double the luma value for accommodating blue and red chroma
+* channels
+*/
+ KUNIT_ASSERT_EQ(test, get_bytes_per_element(dm_420_8, true), 2);
+ KUNIT_ASSERT_EQ(test, get_bytes_per_element(dm_420_10, true), 4);
+
+ /* monochrome encodings sh
[PATCH v5 2/8] drm/amd/display: Introduce KUnit tests to the bw_fixed library
From: MaÃra Canal
KUnit unifies the test structure and provides helper tools that simplify
the development of tests. Basic use case allows running tests as regular
processes, which makes easier to run unit tests on a development machine
and to integrate the tests in a CI system.
This commit introduces a unit test to the bw_fixed library, which
performs a lot of the mathematical operations involving fixed-point
arithmetic and the conversion of integers to fixed-point representation
inside the Display Mode Library.
As fixed-point representation is the base foundation of the DML calcs
operations, this unit tests intend to assure the proper functioning of
the basic mathematical operations of fixed-point arithmetic, such as
multiplication, conversion from fractional to fixed-point number, and
more. You can run it with: ./tools/testing/kunit/kunit.py run \
--arch=x86_64 \
--kunitconfig=drivers/gpu/drm/amd/display/test/kunit
Co-developed-by: Magali Lemes
Signed-off-by: Magali Lemes
Co-developed-by: Tales Aparecida
Signed-off-by: Tales Aparecida
Signed-off-by: MaÃra Canal
---
drivers/gpu/drm/amd/display/Kconfig | 13 +
.../drm/amd/display/test/kunit/.kunitconfig | 1 +
.../test/kunit/dc/dml/calcs/bw_fixed_test.c | 323 ++
3 files changed, 337 insertions(+)
create mode 100644
drivers/gpu/drm/amd/display/test/kunit/dc/dml/calcs/bw_fixed_test.c
diff --git a/drivers/gpu/drm/amd/display/Kconfig
b/drivers/gpu/drm/amd/display/Kconfig
index e35eef026097..d54036dcac78 100644
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -51,6 +51,19 @@ config DRM_AMD_SECURE_DISPLAY
This option enables the calculation of crc of specific region via
debugfs. Cooperate with specific DMCU FW.
+config DCE_KUNIT_TEST
+ bool "Run all KUnit tests for DCE" if !KUNIT_ALL_TESTS
+ depends on DRM_AMD_DC && KUNIT
+ default KUNIT_ALL_TESTS
+ help
+ Enables unit tests for the Display Controller Engine. Only
useful for kernel
+ devs running KUnit.
+
+ For more information on KUnit and unit tests in general please
refer to
+ the KUnit documentation in Documentation/dev-tools/kunit/.
+
+ If unsure, say N.
+
config AMD_DC_BASICS_KUNIT_TEST
bool "Enable KUnit tests for the 'basics' sub-component of DAL" if
!KUNIT_ALL_TESTS
depends on DRM_AMD_DC && KUNIT
diff --git a/drivers/gpu/drm/amd/display/test/kunit/.kunitconfig
b/drivers/gpu/drm/amd/display/test/kunit/.kunitconfig
index 862e6506ddd3..7a58f75a8dfc 100644
--- a/drivers/gpu/drm/amd/display/test/kunit/.kunitconfig
+++ b/drivers/gpu/drm/amd/display/test/kunit/.kunitconfig
@@ -4,3 +4,4 @@ CONFIG_DRM=y
CONFIG_DRM_AMDGPU=y
CONFIG_DRM_AMD_DC=y
CONFIG_AMD_DC_BASICS_KUNIT_TEST=y
+CONFIG_DCE_KUNIT_TEST=y
diff --git
a/drivers/gpu/drm/amd/display/test/kunit/dc/dml/calcs/bw_fixed_test.c
b/drivers/gpu/drm/amd/display/test/kunit/dc/dml/calcs/bw_fixed_test.c
new file mode 100644
index ..1369da49f444
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/test/kunit/dc/dml/calcs/bw_fixed_test.c
@@ -0,0 +1,323 @@
+// SPDX-License-Identifier: MIT
+/*
+ * KUnit tests for dml/calcs/bw_fixed.h
+ *
+ * Copyright (C) 2022, Magali Lemes
+ * Copyright (C) 2022, MaÃra Canal
+ * Copyright (C) 2022, Tales Aparecida
+ */
+
+#include
+#include
+#include "bw_fixed.h"
+
+/**
+ * DOC: Unit tests for AMDGPU DML calcs/bw_fixed.h
+ *
+ * bw_fixed.h performs a lot of the mathematical operations involving
+ * fixed-point arithmetic and the conversion of integers to fixed-point
+ * representation.
+ *
+ * As fixed-point representation is the base foundation of the DML calcs
+ * operations, these tests intend to assure the proper functioning of the
+ * basic mathematical operations of fixed-point arithmetic, such as
+ * multiplication, conversion from fractional to fixed-point number, and more.
+ *
+ */
+
+/**
+ * abs_i64_test - KUnit test for abs_i64
+ * @test: represents a running instance of a test.
+ */
+static void abs_i64_test(struct kunit *test)
+{
+ KUNIT_EXPECT_EQ(test, 0ULL, abs_i64(0LL));
+
+ /* Argument type limits */
+ KUNIT_EXPECT_EQ(test, (uint64_t)MAX_I64, abs_i64(MAX_I64));
+ KUNIT_EXPECT_EQ(test, (uint64_t)MAX_I64 + 1, abs_i64(MIN_I64));
+}
+
+/**
+ * bw_int_to_fixed_nonconst_test - KUnit test for bw_int_to_fixed_nonconst
+ * @test: represents a running instance of a test.
+ */
+static void bw_int_to_fixed_nonconst_test(struct kunit *test)
+{
+ struct bw_fixed res;
+
+ /* Add BW_FIXED_BITS_PER_FRACTIONAL_PART trailing 0s to binary number */
+ res = bw_int_to_fixed_nonconst(1000); /* 0x3E8 */
+ KUNIT_EXPECT_EQ(test, 16777216000, res.value); /* 0x3E800 */
+
+ res = bw_int_to_fixed_nonconst(-1000); /* -0x3E8 */
+ KUNIT_EXPECT_EQ(test, -16777216000, res.value); /* -0x3E800 */
+
+ res = bw_in
[PATCH v5 4/8] drm/amd/display: Introduce KUnit tests to the display_mode_vba library
From: MaÃra Canal
The display_mode_vba library deals with hundreds of display parameters
and sometimes does it in odd ways. The addition of unit tests intends to
assure the quality of the code delivered by HW engineers and, also make
it possible to refactor the code decreasing concerns about adding bugs
to the codebase.
Signed-off-by: MaÃra Canal
---
.../gpu/drm/amd/display/test/kunit/Makefile | 5 +
.../test/kunit/dc/dml/display_mode_vba_test.c | 741 ++
2 files changed, 746 insertions(+)
create mode 100644
drivers/gpu/drm/amd/display/test/kunit/dc/dml/display_mode_vba_test.c
diff --git a/drivers/gpu/drm/amd/display/test/kunit/Makefile
b/drivers/gpu/drm/amd/display/test/kunit/Makefile
index 84b22ecb98df..ec3883029052 100644
--- a/drivers/gpu/drm/amd/display/test/kunit/Makefile
+++ b/drivers/gpu/drm/amd/display/test/kunit/Makefile
@@ -7,6 +7,11 @@ ifdef CONFIG_AMD_DC_BASICS_KUNIT_TEST
DC_TESTS += dc/basics/fixpt31_32_test.o
endif
+ifdef CONFIG_DML_KUNIT_TEST
+ CFLAGS_$(AMDDALPATH)/test/kunit/dc/dml/display_mode_vba_test.o :=
$(dml_ccflags)
+ DC_TESTS += dc/dml/display_mode_vba_test.o
+endif
+
AMD_DAL_DC_TESTS = $(addprefix $(AMDDALPATH)/test/kunit/,$(DC_TESTS))
AMD_DISPLAY_FILES += $(AMD_DAL_DC_TESTS)
diff --git
a/drivers/gpu/drm/amd/display/test/kunit/dc/dml/display_mode_vba_test.c
b/drivers/gpu/drm/amd/display/test/kunit/dc/dml/display_mode_vba_test.c
new file mode 100644
index ..d3e3a9f50c3d
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/test/kunit/dc/dml/display_mode_vba_test.c
@@ -0,0 +1,741 @@
+// SPDX-License-Identifier: MIT
+/*
+ * KUnit tests for dml/display_mode_vba.h
+ *
+ * Copyright (C) 2022, MaÃra Canal
+ */
+
+#include
+#include "dml/display_mode_lib.h"
+
+struct pixel_clock_adjustment_for_progressive_to_interlace_unit_expected {
+ const double pixel_clock[DC__NUM_DPP__MAX];
+ const double pixel_clock_backend[DC__NUM_DPP__MAX];
+};
+
+struct pixel_clock_adjustment_for_progressive_to_interlace_unit_test_case {
+ const char *desc;
+ const unsigned int number_of_active_planes;
+ const bool interlace[DC__NUM_DPP__MAX];
+ const bool progressive_to_interlace_unit_in_OPP;
+ const double pixel_clock[DC__NUM_DPP__MAX];
+ const struct
pixel_clock_adjustment_for_progressive_to_interlace_unit_expected expected;
+};
+
+struct calculate_256B_block_sizes_test_case {
+ const char *desc;
+ const enum source_format_class source_pixel_format;
+ const enum dm_swizzle_mode surface_tiling;
+ const unsigned int byte_per_pixel_Y;
+ const unsigned int byte_per_pixel_C;
+ const unsigned int block_height_256_bytes_Y;
+ const unsigned int block_height_256_bytes_C;
+ const unsigned int block_width_256_bytes_Y;
+ const unsigned int block_width_256_bytes_C;
+};
+
+struct calculate_write_back_DISPCLK_test_case {
+ const char *desc;
+ const enum source_format_class writeback_pixel_format;
+ const double pixel_clock;
+ const double writeback_HRatio;
+ const double writeback_VRatio;
+ const unsigned int writeback_luma_HTaps;
+ const unsigned int writeback_luma_VTaps;
+ const unsigned int writeback_chroma_HTaps;
+ const unsigned int writeback_chroma_VTaps;
+ const double writeback_destination_width;
+ const unsigned int HTotal;
+ const unsigned int writeback_chroma_line_buffer_width;
+ const double calculate_write_back_DISPCLK;
+};
+
+/**
+ * pclk_adjustment_for_progressive_to_interlace_unit_test - KUnit test
+ * for PixelClockAdjustmentForProgressiveToInterlaceUnit
+ * @test: represents a running instance of a test.
+ */
+static void pclk_adjustment_for_progressive_to_interlace_unit_test(struct
kunit *test)
+{
+ const struct
pixel_clock_adjustment_for_progressive_to_interlace_unit_test_case
+ *test_param = test->param_value;
+ struct display_mode_lib *mode_lib;
+ size_t pixel_clock_size = DC__NUM_DPP__MAX * sizeof(const double);
+ size_t interlace_size = DC__NUM_DPP__MAX * sizeof(const bool);
+
+ mode_lib = kunit_kzalloc(test, sizeof(struct display_mode_lib),
+GFP_KERNEL);
+ KUNIT_ASSERT_NOT_ERR_OR_NULL(test, mode_lib);
+
+ mode_lib->vba.NumberOfActivePlanes =
test_param->number_of_active_planes;
+ memcpy(mode_lib->vba.Interlace, test_param->interlace, interlace_size);
+ mode_lib->vba.ProgressiveToInterlaceUnitInOPP =
+ test_param->progressive_to_interlace_unit_in_OPP;
+ memcpy(mode_lib->vba.PixelClock, test_param->pixel_clock,
pixel_clock_size);
+
+ PixelClockAdjustmentForProgressiveToInterlaceUnit(mode_lib);
+
+ KUNIT_EXPECT_TRUE(test, !memcmp(mode_lib->vba.PixelClock,
+ test_param->expected.pixel_clock,
+ pixel_clock_size));
+ KUNIT_EXPECT_TRUE(test, !memcmp(
[PATCH v5 5/8] drm/amd/display: Introduce KUnit to dcn20/display_mode_vba_20 library
From: MaÃra Canal
The display_mode_vba_20 deals with hundreds of display parameters for
the DCN20 and sometimes does it in odd ways. The addition of unit tests
intends to assure the quality of the code delivered by HW engineers and,
also make it possible to refactor the code decreasing concerns about adding
bugs to the codebase.
Change since v4:
- Drop some unstable tests
Signed-off-by: MaÃra Canal
---
.../dc/dml/dcn20/display_mode_vba_20.c| 4 +
.../dc/dml/dcn20/display_mode_vba_20_test.c | 780 ++
2 files changed, 784 insertions(+)
create mode 100644
drivers/gpu/drm/amd/display/test/kunit/dc/dml/dcn20/display_mode_vba_20_test.c
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
index 7bf4bb7ad044..aea6e29fd6e5 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
@@ -5116,3 +5116,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct
display_mode_lib *mode_l
locals->OutputBppPerState[mode_lib->vba.VoltageLevel][k];
}
}
+
+#if IS_ENABLED(CONFIG_DML_KUNIT_TEST)
+#include "../../test/kunit/dc/dml/dcn20/display_mode_vba_20_test.c"
+#endif
diff --git
a/drivers/gpu/drm/amd/display/test/kunit/dc/dml/dcn20/display_mode_vba_20_test.c
b/drivers/gpu/drm/amd/display/test/kunit/dc/dml/dcn20/display_mode_vba_20_test.c
new file mode 100644
index ..b3202c3152d7
--- /dev/null
+++
b/drivers/gpu/drm/amd/display/test/kunit/dc/dml/dcn20/display_mode_vba_20_test.c
@@ -0,0 +1,780 @@
+// SPDX-License-Identifier: MIT
+/*
+ * KUnit tests for dml/dcn20/display_mode_vba_20.c
+ *
+ * Copyright (C) 2022, MaÃra Canal
+ */
+
+#include
+#include "dml/display_mode_enums.h"
+
+struct calculate_write_back_delay_test_case {
+ const char *desc;
+ const enum source_format_class writeback_pixel_format;
+ const double writeback_HRatio;
+ const double writeback_VRatio;
+ const unsigned int writeback_luma_HTaps;
+ const unsigned int writeback_luma_VTaps;
+ const unsigned int writeback_chroma_HTaps;
+ const unsigned int writeback_chroma_VTaps;
+ const unsigned int writeback_destination_width;
+ const double calculate_write_back_delay;
+};
+
+struct calculate_active_row_bandwidth_test_case {
+ const char *desc;
+ const bool GPUVM_enable;
+ const enum source_format_class source_pixel_format;
+ const double VRatio;
+ const bool DCC_enable;
+ const double line_time;
+ const unsigned int meta_row_byte_luma;
+ const unsigned int meta_row_byte_chroma;
+ const unsigned int meta_row_height_luma;
+ const unsigned int meta_row_height_chroma;
+ const unsigned int pixel_PTE_bytes_per_row_luma;
+ const unsigned int pixel_PTE_bytes_per_row_chroma;
+ const unsigned int dpte_row_height_luma;
+ const unsigned int dpte_row_height_chroma;
+ const double meta_row_bw;
+ const double dpte_row_bw;
+ const double qual_row_bw;
+};
+
+/**
+ * dscce_compute_delay_test - KUnit test for dscceComputeDelay
+ * @test: represents a running instance of a test.
+ */
+static void dscce_compute_delay_test(struct kunit *test)
+{
+ /* Testing all the valid values for bits per color (bpc): {8, 10, 12} */
+ /* Testing all the valid values for number of slices: {1, 2, 3, 4} */
+
+ /*
+* For 4:4:4 encoding, the minimum bpp value is 8 and is incremented by
+* 1/16 of a bit. Moreover, the sliceWidth must be less than or equal to
+* 5184/numSlices.
+*/
+
+ /* Minimum sliceWidth value on 4:4:4 encoding */
+ KUNIT_EXPECT_EQ(test, dscceComputeDelay(8, 8.0, 1, 1, dm_444), 2004);
+
+ KUNIT_EXPECT_EQ(test, dscceComputeDelay(8, 8.0625, 5184, 1, dm_444),
885);
+
+ KUNIT_EXPECT_EQ(test, dscceComputeDelay(10, 8.125, 2592, 2, dm_444),
3495);
+
+ KUNIT_EXPECT_EQ(test, dscceComputeDelay(10, 8.1875, 1728, 3, dm_444),
4356);
+
+ KUNIT_EXPECT_EQ(test, dscceComputeDelay(12, 8.25, 864, 3, dm_444),
4425);
+
+ KUNIT_EXPECT_EQ(test, dscceComputeDelay(12, 8.3125, 1296, 4, dm_444),
4854);
+
+ /*
+* For 4:2:0 encoding, the minimum bpp value is 6 and is incremented by
+* 1/16 of a bit. Moreover, the sliceWidth must be less than or equal to
+* 4096/numSlices.
+*/
+
+ /* Minimum sliceWidth value on 4:2:0 encoding */
+ KUNIT_EXPECT_EQ(test, dscceComputeDelay(8, 6.0, 2, 1, dm_420), 2982);
+
+ KUNIT_EXPECT_EQ(test, dscceComputeDelay(8, 6.0625, 4096, 1, dm_420),
1428);
+
+ KUNIT_EXPECT_EQ(test, dscceComputeDelay(10, 6.125, 2048, 2, dm_420),
3522);
+
+ KUNIT_EXPECT_EQ(test, dscceComputeDelay(10, 6.1875, 1365, 3, dm_420),
4200);
+
+ KUNIT_EXPECT_EQ(test, dscceComputeDelay(12, 6.25, 682, 3, dm_420),
5706);
+
+
[PATCH v5 6/8] drm/amd/display: Introduce KUnit tests for dcn20_fpu
From: Magali Lemes
This commit adds unit tests to the functions dcn20_cap_soc_clocks and
dcn21_update_bw_bounding_box from dcn20/dcn20_fpu.
Signed-off-by: Magali Lemes
Signed-off-by: MaÃra Canal
---
.../gpu/drm/amd/display/test/kunit/Makefile | 3 +-
.../test/kunit/dc/dml/dcn20/dcn20_fpu_test.c | 561 ++
2 files changed, 563 insertions(+), 1 deletion(-)
create mode 100644
drivers/gpu/drm/amd/display/test/kunit/dc/dml/dcn20/dcn20_fpu_test.c
diff --git a/drivers/gpu/drm/amd/display/test/kunit/Makefile
b/drivers/gpu/drm/amd/display/test/kunit/Makefile
index ec3883029052..a6ad449f9885 100644
--- a/drivers/gpu/drm/amd/display/test/kunit/Makefile
+++ b/drivers/gpu/drm/amd/display/test/kunit/Makefile
@@ -9,7 +9,8 @@ endif
ifdef CONFIG_DML_KUNIT_TEST
CFLAGS_$(AMDDALPATH)/test/kunit/dc/dml/display_mode_vba_test.o :=
$(dml_ccflags)
- DC_TESTS += dc/dml/display_mode_vba_test.o
+ CFLAGS_$(AMDDALPATH)/test/kunit/dc/dml/dcn20/dcn20_fpu_test.o :=
$(dml_ccflags)
+ DC_TESTS += dc/dml/display_mode_vba_test.o dc/dml/dcn20/dcn20_fpu_test.o
endif
AMD_DAL_DC_TESTS = $(addprefix $(AMDDALPATH)/test/kunit/,$(DC_TESTS))
diff --git
a/drivers/gpu/drm/amd/display/test/kunit/dc/dml/dcn20/dcn20_fpu_test.c
b/drivers/gpu/drm/amd/display/test/kunit/dc/dml/dcn20/dcn20_fpu_test.c
new file mode 100644
index ..c51a0afbe518
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/test/kunit/dc/dml/dcn20/dcn20_fpu_test.c
@@ -0,0 +1,561 @@
+// SPDX-License-Identifier: MIT
+/*
+ * KUnit tests for dml/dcn20/dcn20_fpu.h
+ *
+ * Copyright (C) 2022, Magali Lemes
+ */
+
+#include
+
+#include "dc/inc/resource.h"
+#include "dc/inc/hw/clk_mgr.h"
+#include "dcn21/dcn21_resource.h"
+
+#include "dml/dcn20/dcn20_fpu.h"
+
+/**
+ * DOC: Unit tests for AMDGPU DML dcn20/dcn20_fpu.h
+ */
+
+struct dcn20_cap_soc_clocks_test_case {
+ const char *desc;
+ struct _vcs_dpi_soc_bounding_box_st bb;
+ struct pp_smu_nv_clock_table max_clocks;
+ const int clock_states;
+ const struct _vcs_dpi_voltage_scaling_st
expected_clock_limits[DC__VOLTAGE_STATES];
+};
+
+struct dcn21_update_bw_bounding_box_test_case {
+ const char *desc;
+ struct dc dc;
+ struct clk_bw_params bw_params;
+ const int clocks_to_compare;
+ const struct _vcs_dpi_voltage_scaling_st
expected_clock_limits[DC__VOLTAGE_STATES];
+};
+
+struct dcn20_cap_soc_clocks_test_case dcn20_cap_soc_clocks_test_cases[] = {
+ {
+ .desc = "4-state bounding box clock limits ",
+ .bb = {
+ .clock_limits = {
+ {
+ .dcfclk_mhz = 506.0,
+ .fabricclk_mhz = 506.0,
+ .dispclk_mhz = 1284.0,
+ .dppclk_mhz = 400.0,
+ .phyclk_mhz = 810.0,
+ .socclk_mhz = 506.0,
+ .dscclk_mhz = 428.0,
+ .dram_speed_mts = 1600.0,
+ },
+ {
+ .dcfclk_mhz = 540.0,
+ .fabricclk_mhz = 540.0,
+ .dispclk_mhz = 1284.0,
+ .dppclk_mhz = 1284.0,
+ .phyclk_mhz = 810.0,
+ .socclk_mhz = 540.0,
+ .dscclk_mhz = 428.0,
+ .dram_speed_mts = 8000.0,
+ },
+ {
+ .dcfclk_mhz = 675.0,
+ .fabricclk_mhz = 675.0,
+ .dispclk_mhz = 1284.0,
+ .dppclk_mhz = 1284.0,
+ .phyclk_mhz = 810.0,
+ .socclk_mhz = 675.0,
+ .dscclk_mhz = 428.0,
+ .dram_speed_mts = 1.0,
+ },
+ {
+ .dcfclk_mhz = 1265.0,
+ .fabricclk_mhz = 1266.0,
+ .dispclk_mhz = 1284.0,
+ .dppclk_mhz = 1284.0,
+ .phyclk_mhz = 810.0,
+ .socclk_mhz = 1266.0,
+ .dscclk_mhz = 428.0,
+ .dram_speed_mts = 15000.0,
+ },
+ },
+ .num_states = 4,
+ },
+ .m
[PATCH v5 7/8] drm/amd/display: Introduce KUnit tests to dc_dmub_srv library
From: MaÃra Canal
Add a unit test to the SubVP feature in order to avoid possible
regressions and ensure code robustness. In particular, this new test
validates the expected parameters when using 4k144 and 4k240 displays.
Signed-off-by: MaÃra Canal
Co-developed-by: Rodrigo Siqueira
Reported-by: kernel test robot
---
drivers/gpu/drm/amd/display/Kconfig | 13 ++
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 4 +
.../drm/amd/display/test/kunit/.kunitconfig | 1 +
.../display/test/kunit/dc/dc_dmub_srv_test.c | 159 ++
4 files changed, 177 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/test/kunit/dc/dc_dmub_srv_test.c
diff --git a/drivers/gpu/drm/amd/display/Kconfig
b/drivers/gpu/drm/amd/display/Kconfig
index ab52b135db85..11b0e54262f3 100644
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -90,4 +90,17 @@ config AMD_DC_BASICS_KUNIT_TEST
If unsure, say N.
+config AMD_DC_KUNIT_TEST
+ bool "Enable KUnit tests for the 'utils' sub-component of DAL" if
!KUNIT_ALL_TESTS
+ depends on DRM_AMD_DC && KUNIT
+ default KUNIT_ALL_TESTS
+ help
+ Enables unit tests for the basics folder of Display Core. Only
useful for
+ kernel devs running KUnit.
+
+ For more information on KUnit and unit tests in general please
refer to
+ the KUnit documentation in Documentation/dev-tools/kunit/.
+
+ If unsure, say N.
+
endmenu
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 6083b1dcf050..7aafdfeac60e 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -1438,3 +1438,7 @@ bool dc_wake_and_execute_gpint(const struct dc_context
*ctx, enum dmub_gpint_com
return result;
}
+
+#if IS_ENABLED(CONFIG_AMD_DC_KUNIT_TEST)
+#include "../test/kunit/dc/dc_dmub_srv_test.c"
+#endif
diff --git a/drivers/gpu/drm/amd/display/test/kunit/.kunitconfig
b/drivers/gpu/drm/amd/display/test/kunit/.kunitconfig
index eb6f81601757..4c5861ad58bd 100644
--- a/drivers/gpu/drm/amd/display/test/kunit/.kunitconfig
+++ b/drivers/gpu/drm/amd/display/test/kunit/.kunitconfig
@@ -4,5 +4,6 @@ CONFIG_DRM=y
CONFIG_DRM_AMDGPU=y
CONFIG_DRM_AMD_DC=y
CONFIG_AMD_DC_BASICS_KUNIT_TEST=y
+CONFIG_AMD_DC_KUNIT_TEST=y
CONFIG_DCE_KUNIT_TEST=y
CONFIG_DML_KUNIT_TEST=y
diff --git a/drivers/gpu/drm/amd/display/test/kunit/dc/dc_dmub_srv_test.c
b/drivers/gpu/drm/amd/display/test/kunit/dc/dc_dmub_srv_test.c
new file mode 100644
index ..d12c4e3816b5
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/test/kunit/dc/dc_dmub_srv_test.c
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: MIT
+/*
+ * KUnit tests for dc_dmub_srv.c
+ *
+ * Copyright (C) 2022, MaÃra Canal
+ */
+
+#include
+#include "dc_dmub_srv.h"
+
+/**
+ * DOC: overview
+ *
+ * The file dc_dumb_srv.c has many functions that work as an interface to
+ * generate some of the DMUB parameters. To offload some of the complexity from
+ * the DMUB, the 'dc_dmub_srv.c' file provides functions that perform
+ * mathematical calculations to generate the parameter that will be passed to
+ * the DMUB to enable specific configurations.
+ */
+
+/**
+ * struct populate_subvp_cmd_drr_info_test_case - Fields for subvp validation
+ *
+ * The function populate_subvp_cmd_drr_info() performs calculations based on
+ * different pipe context timing values. This struct maintains those fields
+ * required to be passed to the populate_subvp_cmd_drr_info.
+ */
+struct populate_subvp_cmd_drr_info_test_case {
+ const char *desc;
+ /**
+ * @dc: In the specific context of populate_subvp_cmd_drr_info() test,
+ * we only care about the DC capabilities.
+ */
+ struct dc *dc;
+
+ /**
+* @subvp_pipe: This parameter plays an essential role in the
+* populate_subvp_cmd_drr_info validation because it will be used to
+* derive some of the parameters for the max VTotal, but it is also
+* employed in a pointer validation that extracts the phantom timing
+* from the context.
+*/
+ struct pipe_ctx *subvp_pipe;
+
+ /**
+* @vblank_pipe: This field keeps the DRR timing values used in the Max
+* and Min VTotal calculation.
+*/
+ struct pipe_ctx *vblank_pipe;
+
+ /**
+* @context: In the context of populate_subvp_cmd_drr_info(), this
+* field it is only necessary to fulfill the requirements for
+* dc_state_get_paired_subvp_stream() helper.
+*/
+ struct dc_state *context;
+};
+
+const struct dc_stream_status mock_dc_stream_state_returned_from_get_paired = {
+ .mall_stream_config = (struct mall_stream_config) {
+ .paired_stream = &(struct dc_stream_state) {
+
[PATCH v5 8/8] Documentation/gpu: Add Display Core Unit Test documentation
From: MaÃra Canal Explain how to run the KUnit tests present in the AMDGPU's Display Core and clarify which architectures and tools can be used to run the tests. Moreover, explains how to add new tests to the existing tests. Signed-off-by: MaÃra Canal --- .../gpu/amdgpu/display/display-test.rst | 88 +++ Documentation/gpu/amdgpu/display/index.rst| 1 + 2 files changed, 89 insertions(+) create mode 100644 Documentation/gpu/amdgpu/display/display-test.rst diff --git a/Documentation/gpu/amdgpu/display/display-test.rst b/Documentation/gpu/amdgpu/display/display-test.rst new file mode 100644 index ..a8c136ce87b7 --- /dev/null +++ b/Documentation/gpu/amdgpu/display/display-test.rst @@ -0,0 +1,88 @@ +.. SPDX-License-Identifier: GPL-2.0+ + + +Display Core Unit Tests + + +Display core provides a set of unit tests, currently focused on the Display Mode +Library. The unit tests use KUnit (Kernel Unit Testing Framework), a common +framework for unit tests within the Linux Kernel. + +This section covers the specifics of the tests for the AMDGPU driver. For general +information about KUnit, please refer to Documentation/dev-tools/kunit/start.rst. + +How to run the tests? += + +In order to facilitate running the test suite, a configuration file is present +in ``drivers/gpu/drm/amd/display/tests/dc/.kunitconfig``. This configuration file +can be used to run the kunit_tool, a Python script (``tools/testing/kunit/kunit.py``) +used to configure, build, exec, parse and run tests. + +.. code-block:: bash + + $ ./tools/testing/kunit/kunit.py run --arch=x86_64 \ + --kunitconfig=drivers/gpu/drm/amd/display/tests + +Currently, the Display Core Unit Tests are only supported on x86_64. + +Moreover, the tests can also be run on real hardware or in other emulation +environments. To include the Display Core Unit Tests on a deployable kernel, +you might add the following config options to your ``.config``: + +.. code-block:: none + + CONFIG_KUNIT=y + CONFIG_AMDGPU=m + CONFIG_AMD_DC_BASICS_KUNIT_TEST=y + CONFIG_AMD_DC_KUNIT_TEST=y + CONFIG_DCE_KUNIT_TEST=y + CONFIG_DML_KUNIT_TEST=y + +Once the kernel is built and installed, you can load the ``amdgpu`` module +to run all tests available. + +Also, the tests can be added to the kernel as built-in modules, by adding the +following config options to your ``.config``: + +.. code-block:: none + + CONFIG_KUNIT=y + CONFIG_AMDGPU=y + CONFIG_AMD_DC_BASICS_KUNIT_TEST=y + CONFIG_AMD_DC_KUNIT_TEST=y + CONFIG_DCE_KUNIT_TEST=y + CONFIG_DML_KUNIT_TEST=y + +In order to run specific tests, you can check the filter options from KUnit on +Documentation/dev-tools/kunit/kunit-tool.rst. + +How to add new tests? += + +Tests covering different parts of the Display Core are always welcomed. Adding +a new test is a simple procedure, that consists in creating a unit test file +and adding the following guard to the end of the tested file when you are +testing static functions: + +.. code-block:: c + + #ifdef CONFIG_MY_KUNIT_TEST + #include "my_kunit_test.c" + #endif + +If you are not testing static functions, you should use the Makefile placed on +``display/tests``. In order to add a test to the Makefile, you can just add +the following entry to the Makefile: + +.. code-block:: make + + ifdef CONFIG_MY_KUNIT_TEST + DC_TESTS += my_kunit_test.o + endif + +The ``display/tests`` folder replicates the folder hierarchy of the ``display`` +folder, so this must be considered while adding new tests. + +More information on how to write unit tests with the KUnit API can be provided +on Documentation/dev-tools/kunit/api/test.rst. diff --git a/Documentation/gpu/amdgpu/display/index.rst b/Documentation/gpu/amdgpu/display/index.rst index f0c342e00a39..e5895e658943 100644 --- a/Documentation/gpu/amdgpu/display/index.rst +++ b/Documentation/gpu/amdgpu/display/index.rst @@ -92,5 +92,6 @@ table of content: dcn-blocks.rst mpo-overview.rst dc-debug.rst + display-test.rst display-contributing.rst dc-glossary.rst -- 2.43.0
[PATCH] drm/amd/display: Add monitor patch for specific eDP
From: Ivan Lipski
[WHY]
Some eDP panels's ext caps don't write initial value cause the value of
dpcd_addr(0x317) is random. It means that sometimes the eDP will
clarify it is OLED, miniLED...etc cause the backlight control interface
is incorrect.
[HOW]
Add a new panel patch to remove sink ext caps(HDR,OLED...etc)
Cc: sta...@vger.kernel.org # 6.5.x
Cc: Hamza Mahfooz
Cc: Tsung-hua Lin
Cc: Chris Chi
Cc: Harry Wentland
Tested-by: Daniel Wheeler
Reviewed-by: Sun peng Li
Acked-by: Rodrigo Siqueira
Signed-off-by: Ivan Lipski
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index d9a482908380..764dc3ffd91b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -63,6 +63,12 @@ static void apply_edid_quirks(struct edid *edid, struct
dc_edid_caps *edid_caps)
DRM_DEBUG_DRIVER("Disabling FAMS on monitor with panel id
%X\n", panel_id);
edid_caps->panel_patch.disable_fams = true;
break;
+ /* Workaround for some monitors that do not clear DPCD 0x317 if
FreeSync is unsupported */
+ case drm_edid_encode_panel_id('A', 'U', 'O', 0xA7AB):
+ case drm_edid_encode_panel_id('A', 'U', 'O', 0xE69B):
+ DRM_DEBUG_DRIVER("Clearing DPCD 0x317 on monitor with panel id
%X\n", panel_id);
+ edid_caps->panel_patch.remove_sink_ext_caps = true;
+ break;
default:
return;
}
--
2.43.0
[PATCH 00/25] DC Patches April 10, 2024
This DC patchset brings improvements in multiple areas. In summary, we have: * Expand dmub_cmd operations. * Update DVI configuration. * Modify power sequence. * Enable Z10 flag for IPS. * Multiple code cleanups. Cc: Daniel Wheeler Thanks Siqueira Anthony Koo (1): drm/amd/display: Expand dmub_cmd operations Aric Cyr (1): drm/amd/display: 3.2.281 Bitnun, Ethan (1): drm/amd/display: Improve the log precision Chaitanya Dhere (1): drm/amd/display: Fix incorrect pointer assignment Charlene Liu (1): drm/amd/display: limit the code change to ips enabled asic Chris Park (1): drm/amd/display: Add a function for checking tmds mode Eric Bernstein (1): drm/amd/display: Update FMT settings for 4:2:0 Mikita Lipski (1): drm/amd/display: Fix PSR command version passed Nicholas Kazlauskas (1): drm/amd/display: Pass sequential ONO bit to DMCUB boot options Rodrigo Siqueira (11): drm/amd/display: Use dce_version instead of chip_id drm/amd/display: Adjust headers drm/amd/display: Group scl_data together in resource_build_scaling_params drm/amd/display: Replace int with unsigned int drm/amd/display: Update some comments to improve the code readability drm/amd/display: Remove unnecessary code drm/amd/display: Rework dcn10_stream_encoder header drm/amd/display: Move REG sequence from program ogam to idle before connect drm/amd/display: Update DCN201 link encoder registers drm/amd/display: Add missing callback for init_watermarks in DCN 301 drm/amd/display: Add missing replay field Samson Tam (1): drm/amd/display: add support for chroma offset Sung Joon Kim (4): drm/amd/display: Modify power sequence drm/amd/display: Modify resource allocation logic drm/amd/display: Enable Z10 flag for IPS FSM drm/amd/display: Rework power sequence and resource allocation logic .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 + .../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 2 +- .../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 3 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 8 +- .../gpu/drm/amd/display/dc/core/dc_resource.c | 5 +- .../gpu/drm/amd/display/dc/core/dc_state.c| 10 +- .../gpu/drm/amd/display/dc/core/dc_stream.c | 2 +- drivers/gpu/drm/amd/display/dc/dc.h | 16 +- drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 7 + drivers/gpu/drm/amd/display/dc/dc_types.h | 2 + .../gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 6 - .../amd/display/dc/dcn10/dcn10_link_encoder.h | 6 - .../gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 9 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 2 + .../display/dc/dcn10/dcn10_stream_encoder.h | 10 +- .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 2 +- .../gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c | 10 +- .../drm/amd/display/dc/dcn201/dcn201_hubp.c | 5 + .../display/dc/dcn201/dcn201_link_encoder.h | 14 +- .../gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h | 18 -- .../dc/dcn30/dcn30_dio_stream_encoder.c | 1 - .../gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c | 2 - .../drm/amd/display/dc/dcn301/dcn301_hubbub.c | 1 + drivers/gpu/drm/amd/display/dc/hwss/Makefile | 2 +- .../drm/amd/display/dc/hwss/dcn351/Makefile | 25 ++- .../amd/display/dc/hwss/dcn351/dcn351_hwseq.c | 182 ++ .../amd/display/dc/hwss/dcn351/dcn351_hwseq.h | 41 .../amd/display/dc/hwss/dcn351/dcn351_init.c | 1 + .../dc/resource/dcn32/dcn32_resource.c| 4 +- .../dc/resource/dcn32/dcn32_resource.h| 6 + .../dc/resource/dcn351/dcn351_resource.c | 5 +- drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 1 + .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 53 - .../gpu/drm/amd/display/dmub/src/dmub_dcn35.c | 1 + .../drm/amd/display/include/signal_types.h| 13 ++ 35 files changed, 402 insertions(+), 82 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c create mode 100644 drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h -- 2.43.0
[PATCH 01/25] drm/amd/display: Modify power sequence
From: Sung Joon Kim Need to update the power sequence to help prevent potential issues like multi-display or multi-plane. Reviewed-by: Duncan Ma Acked-by: Rodrigo Siqueira Signed-off-by: Sung Joon Kim --- drivers/gpu/drm/amd/display/dc/hwss/Makefile | 2 +- .../drm/amd/display/dc/hwss/dcn351/Makefile | 25 ++- .../amd/display/dc/hwss/dcn351/dcn351_hwseq.c | 182 ++ .../amd/display/dc/hwss/dcn351/dcn351_hwseq.h | 41 .../amd/display/dc/hwss/dcn351/dcn351_init.c | 9 +- 5 files changed, 247 insertions(+), 12 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c create mode 100644 drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h diff --git a/drivers/gpu/drm/amd/display/dc/hwss/Makefile b/drivers/gpu/drm/amd/display/dc/hwss/Makefile index 9e8e9de51a92..cf8aa23b4415 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/Makefile +++ b/drivers/gpu/drm/amd/display/dc/hwss/Makefile @@ -180,7 +180,7 @@ AMD_DISPLAY_FILES += $(AMD_DAL_HWSS_DCN35) ### -HWSS_DCN351 = dcn351_init.o +HWSS_DCN351 = dcn351_hwseq.o dcn351_init.o AMD_DAL_HWSS_DCN351 = $(addprefix $(AMDDALPATH)/dc/hwss/dcn351/,$(HWSS_DCN351)) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/Makefile b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/Makefile index b24ad27fe6ef..a4b3c1e99ec6 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/Makefile +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/Makefile @@ -1,16 +1,27 @@ # -# (c) Copyright 2022 Advanced Micro Devices, Inc. All the rights reserved +# Copyright (c) 2022-2024 Advanced Micro Devices, Inc. # -# All rights reserved. This notice is intended as a precaution against -# inadvertent publication and does not imply publication or any waiver -# of confidentiality. The year included in the foregoing notice is the -# year of creation of the work. +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: # -# Authors: AMD +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. # # Makefile for DCN351. -DCN351 = dcn351_init.o +DCN351 = dcn351_hwseq.o dcn351_init.o AMD_DAL_DCN351 = $(addprefix $(AMDDALPATH)/dc/dcn351/,$(DCN351)) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c new file mode 100644 index ..93fe5b262a3d --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c @@ -0,0 +1,182 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "core_types.h" +#include "resource.h" +#include "dcn351_hwseq.h" +#include "dcn35/dcn35_hwseq.h" + +#define DC_LOGGER_INIT(logger) \ + struct dal_logger *dc_logger = logger + +#defin
[PATCH 03/25] drm/amd/display: Modify resource allocation logic
From: Sung Joon Kim
To reduce the complexity of pipe resource allocation for different
use-cases, now we search for any free pipe sequentially rather than from
bottom up.
Reviewed-by: Wenjing Liu
Acked-by: Rodrigo Siqueira
Signed-off-by: Sung Joon Kim
---
.../dc/resource/dcn32/dcn32_resource.c| 4 +--
.../dc/resource/dcn32/dcn32_resource.h| 6
.../dc/resource/dcn351/dcn351_resource.c | 35 ++-
.../dc/resource/dcn351/dcn351_resource.h | 6
4 files changed, 48 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
index 9aa39bd25be9..c16e915686fc 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
@@ -2547,7 +2547,7 @@ struct resource_pool *dcn32_create_resource_pool(
* full update which delays the flip for 1 frame. If we use the original pipe
* we don't have to toggle its power. So we can flip faster.
*/
-static int find_optimal_free_pipe_as_secondary_dpp_pipe(
+int dcn32_find_optimal_free_pipe_as_secondary_dpp_pipe(
const struct resource_context *cur_res_ctx,
struct resource_context *new_res_ctx,
const struct resource_pool *pool,
@@ -2730,7 +2730,7 @@ struct pipe_ctx
*dcn32_acquire_free_pipe_as_secondary_dpp_pipe(
return dcn32_acquire_idle_pipe_for_head_pipe_in_layer(
new_ctx, pool, opp_head_pipe->stream,
opp_head_pipe);
- free_pipe_idx = find_optimal_free_pipe_as_secondary_dpp_pipe(
+ free_pipe_idx = dcn32_find_optimal_free_pipe_as_secondary_dpp_pipe(
&cur_ctx->res_ctx, &new_ctx->res_ctx,
pool, opp_head_pipe);
if (free_pipe_idx >= 0) {
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
index 286e20ad46ed..fee67fbab8e2 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
@@ -137,6 +137,12 @@ bool dcn32_any_surfaces_rotated(struct dc *dc, struct
dc_state *context);
bool dcn32_is_center_timing(struct pipe_ctx *pipe);
bool dcn32_is_psr_capable(struct pipe_ctx *pipe);
+int dcn32_find_optimal_free_pipe_as_secondary_dpp_pipe(
+ const struct resource_context *cur_res_ctx,
+ struct resource_context *new_res_ctx,
+ const struct resource_pool *pool,
+ const struct pipe_ctx *new_opp_head);
+
struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe(
const struct dc_state *cur_ctx,
struct dc_state *new_ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
index 8a57adb27264..cc1a44a890b5 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
@@ -1728,6 +1728,37 @@ static bool dcn351_validate_bandwidth(struct dc *dc,
return out;
}
+struct pipe_ctx *dcn351_acquire_free_pipe_as_secondary_dpp_pipe(
+ const struct dc_state *cur_ctx,
+ struct dc_state *new_ctx,
+ const struct resource_pool *pool,
+ const struct pipe_ctx *opp_head_pipe)
+{
+ int free_pipe_idx;
+ struct pipe_ctx *free_pipe;
+
+ free_pipe_idx = dcn32_find_optimal_free_pipe_as_secondary_dpp_pipe(
+ &cur_ctx->res_ctx, &new_ctx->res_ctx,
+ pool, opp_head_pipe);
+ if (free_pipe_idx >= 0) {
+ free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx];
+ free_pipe->pipe_idx = free_pipe_idx;
+ free_pipe->stream = opp_head_pipe->stream;
+ free_pipe->stream_res.tg = opp_head_pipe->stream_res.tg;
+ free_pipe->stream_res.opp = opp_head_pipe->stream_res.opp;
+
+ free_pipe->plane_res.hubp = pool->hubps[free_pipe->pipe_idx];
+ free_pipe->plane_res.ipp = pool->ipps[free_pipe->pipe_idx];
+ free_pipe->plane_res.dpp = pool->dpps[free_pipe->pipe_idx];
+ free_pipe->plane_res.mpcc_inst =
+ pool->dpps[free_pipe->pipe_idx]->inst;
+ } else {
+ ASSERT(opp_head_pipe);
+ free_pipe = NULL;
+ }
+
+ return free_pipe;
+}
static struct resource_funcs dcn351_res_pool_funcs = {
.destroy = dcn351_destroy_resource_pool,
@@ -1740,7 +1771,8 @@ static struct resource_funcs dcn351_res_
[PATCH 02/25] drm/amd/display: Add a function for checking tmds mode
From: Chris Park
[Why]
DVI is TMDS signal like HDMI but without audio. Current signal check
does not correctly reflect DVI clock programming.
[How]
Define a new signal check for TMDS that includes DVI to HDMI TMDS
programming.
Reviewed-by: Dillon Varone
Acked-by: Rodrigo Siqueira
Signed-off-by: Chris Park
---
drivers/gpu/drm/amd/display/include/signal_types.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/include/signal_types.h
b/drivers/gpu/drm/amd/display/include/signal_types.h
index 1b14b17a79c7..a10d6b988aab 100644
--- a/drivers/gpu/drm/amd/display/include/signal_types.h
+++ b/drivers/gpu/drm/amd/display/include/signal_types.h
@@ -118,6 +118,19 @@ static inline bool dc_is_dvi_signal(enum signal_type
signal)
}
}
+static inline bool dc_is_tmds_signal(enum signal_type signal)
+{
+ switch (signal) {
+ case SIGNAL_TYPE_DVI_SINGLE_LINK:
+ case SIGNAL_TYPE_DVI_DUAL_LINK:
+ case SIGNAL_TYPE_HDMI_TYPE_A:
+ return true;
+ break;
+ default:
+ return false;
+ }
+}
+
static inline bool dc_is_dvi_single_link_signal(enum signal_type signal)
{
return (signal == SIGNAL_TYPE_DVI_SINGLE_LINK);
--
2.43.0
[PATCH 05/25] drm/amd/display: add support for chroma offset
From: Samson Tam
[Why]
Adding support for chroma subsampling offset (cositing) in scaler
calculations to adjust reference point where we determine post-scaling
chroma value in YUV420 surfaces.
[How]
Add support for cositing options: NONE, LEFT and TOPLEFT Add debug
option force_cositing and set default to TOPLEFT to maintain same
behaviour as without offset support.
Reviewed-by: Jun Lei
Acked-by: Rodrigo Siqueira
Signed-off-by: Samson Tam
---
drivers/gpu/drm/amd/display/dc/dc.h | 3 +++
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 7 +++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 54534df73e83..188f2d401124 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1003,6 +1003,7 @@ struct dc_debug_options {
unsigned int static_screen_wait_frames;
bool force_chroma_subsampling_1tap;
bool disable_422_left_edge_pixel;
+ unsigned int force_cositing;
};
struct gpu_info_soc_bounding_box_v1_0;
@@ -1285,6 +1286,7 @@ struct dc_plane_state {
struct tg_color visual_confirm_color;
bool is_statically_allocated;
+ enum chroma_cositing cositing;
};
struct dc_plane_info {
@@ -1303,6 +1305,7 @@ struct dc_plane_info {
int global_alpha_value;
bool input_csc_enabled;
int layer_index;
+ enum chroma_cositing cositing;
};
#include "dc_stream.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index 465e15f57f93..2ad7f60805f5 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -738,6 +738,13 @@ enum scanning_type {
SCANNING_TYPE_UNDEFINED
};
+enum chroma_cositing {
+ CHROMA_COSITING_NONE,
+ CHROMA_COSITING_LEFT,
+ CHROMA_COSITING_TOPLEFT,
+ CHROMA_COSITING_COUNT
+};
+
struct dc_crtc_timing_flags {
uint32_t INTERLACE :1;
uint32_t HSYNC_POSITIVE_POLARITY :1; /* when set to 1,
--
2.43.0
[PATCH 04/25] drm/amd/display: limit the code change to ips enabled asic
From: Charlene Liu
Limit the code change for ips enable to reduce the impact for now. Also
exit_ips first before dc_power_down to avoid 0x9f.
Reviewed-by: Chris Park
Acked-by: Rodrigo Siqueira
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 145cdab92ca0..01c75b66e8f1 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -5042,8 +5042,13 @@ void dc_interrupt_ack(struct dc *dc, enum dc_irq_source
src)
void dc_power_down_on_boot(struct dc *dc)
{
if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW &&
- dc->hwss.power_down_on_boot)
+ dc->hwss.power_down_on_boot) {
+
+ if (dc->caps.ips_support)
+ dc_exit_ips_for_hw_access(dc);
+
dc->hwss.power_down_on_boot(dc);
+ }
}
void dc_set_power_state(
--
2.43.0
[PATCH 06/25] drm/amd/display: Pass sequential ONO bit to DMCUB boot options
From: Nicholas Kazlauskas
[Why]
IPS ono sequence ordering differs based on the ASIC.
[How]
Detect the ASIC ID revision and set the boot option accordingly. Feed
it through the DCN35 DMUB functions.
Reviewed-by: Sung joon Kim
Acked-by: Rodrigo Siqueira
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 1 +
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c | 1 +
3 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index d52701f6d1d0..2c06f2bee4a5 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1230,6 +1230,15 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
break;
}
+ switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
+ case IP_VERSION(3, 5, 0):
+ case IP_VERSION(3, 5, 1):
+ hw_params.ips_sequential_ono = adev->external_rev_id > 0x10;
+ break;
+ default:
+ break;
+ }
+
status = dmub_srv_hw_init(dmub_srv, &hw_params);
if (status != DMUB_STATUS_OK) {
DRM_ERROR("Error initializing DMUB HW: %d\n", status);
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index 662bdb0e5d3d..2fde1f043d50 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -297,6 +297,7 @@ struct dmub_srv_hw_params {
bool dpia_hpd_int_enable_supported;
bool disable_clock_gate;
bool disallow_dispclk_dppclk_ds;
+ bool ips_sequential_ono;
enum dmub_memory_access_type mem_access_type;
enum dmub_ips_disable_type disable_ips;
};
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
index 98afaecd3984..70e63aeb8f89 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
@@ -420,6 +420,7 @@ void dmub_dcn35_enable_dmub_boot_options(struct dmub_srv
*dmub, const struct dmu
boot_options.bits.disable_clk_ds = params->disallow_dispclk_dppclk_ds;
boot_options.bits.disable_clk_gate = params->disable_clock_gate;
boot_options.bits.ips_disable = params->disable_ips;
+ boot_options.bits.ips_sequential_ono = params->ips_sequential_ono;
REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
}
--
2.43.0
[PATCH 07/25] drm/amd/display: Fix incorrect pointer assignment
From: Chaitanya Dhere
[Why]
Pointer initialization and assignment for dml2_options is not done
correctly. While this works for some compilers, others give an error.
[How]
Modify dc_state_create code to correctly initialize the dml2_opt pointer
and pass it to dml2_create. Also update the code with correct derefrence
operations.
Reviewed-by: Aurabindo Pillai
Acked-by: Rodrigo Siqueira
Signed-off-by: Chaitanya Dhere
---
drivers/gpu/drm/amd/display/dc/core/dc_state.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_state.c
b/drivers/gpu/drm/amd/display/dc/core/dc_state.c
index bf889bdd3925..76bb05f4d6bf 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_state.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_state.c
@@ -191,7 +191,7 @@ static void init_state(struct dc *dc, struct dc_state
*state)
struct dc_state *dc_state_create(struct dc *dc, struct dc_state_create_params
*params)
{
#ifdef CONFIG_DRM_AMD_DC_FP
- struct dml2_configuration_options dml2_opt = dc->dml2_options;
+ struct dml2_configuration_options *dml2_opt = &dc->dml2_options;
#endif
struct dc_state *state = kvzalloc(sizeof(struct dc_state),
GFP_KERNEL);
@@ -205,11 +205,11 @@ struct dc_state *dc_state_create(struct dc *dc, struct
dc_state_create_params *p
#ifdef CONFIG_DRM_AMD_DC_FP
if (dc->debug.using_dml2) {
- dml2_opt.use_clock_dc_limits = false;
- dml2_create(dc, &dml2_opt, &state->bw_ctx.dml2);
+ dml2_opt->use_clock_dc_limits = false;
+ dml2_create(dc, dml2_opt, &state->bw_ctx.dml2);
- dml2_opt.use_clock_dc_limits = true;
- dml2_create(dc, &dml2_opt, &state->bw_ctx.dml2_dc_power_source);
+ dml2_opt->use_clock_dc_limits = true;
+ dml2_create(dc, dml2_opt, &state->bw_ctx.dml2_dc_power_source);
}
#endif
--
2.43.0
[PATCH 12/25] drm/amd/display: Adjust headers
Update headers by removing two unecessary headers and include a new one. Signed-off-by: Rodrigo Siqueira --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 1 + drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c| 3 --- .../gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c| 1 - 3 files changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index bec252e1dd27..358a83b1114b 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -29,6 +29,7 @@ #include "dcn20/dcn20_clk_mgr.h" #include "dce100/dce_clk_mgr.h" #include "dcn31/dcn31_clk_mgr.h" +#include "dcn32/dcn32_clk_mgr.h" #include "reg_helper.h" #include "core_types.h" #include "dm_helpers.h" diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c index a2f48d46d199..744c335718a7 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c @@ -22,9 +22,6 @@ * Authors: AMD * */ - -#include - #include "resource.h" #include "dce_i2c.h" #include "dce_i2c_hw.h" diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c index 8ed7125d230d..425b830b88d2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c @@ -29,7 +29,6 @@ #include "reg_helper.h" #include "hw_shared.h" #include "dc.h" -#include "core_types.h" #define DC_LOGGER \ enc1->base.ctx->logger -- 2.43.0
[PATCH 08/25] drm/amd/display: Enable Z10 flag for IPS FSM
From: Sung Joon Kim
[why]
IPS FSM requires Z10 flag to be enabled to do save and restore the
registers properly.
[how]
Enable Z10 and use the correct function to determine Z10 capability
Reviewed-by: Nicholas Kazlauskas
Acked-by: Rodrigo Siqueira
Signed-off-by: Sung Joon Kim
---
.../gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
index cc1a44a890b5..b29d7d47552b 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
@@ -758,7 +758,7 @@ static const struct dc_debug_options debug_defaults_drv = {
//must match enable_single_display_2to1_odm_policy to support dynamic
ODM transitions
.enable_double_buffered_dsc_pg_support = true,
.enable_dp_dig_pixel_rate_div_policy = 1,
- .disable_z10 = true,
+ .disable_z10 = false,
.ignore_pg = true,
.psp_disabled_wa = true,
.ips2_eval_delay_us = 2000,
@@ -1722,7 +1722,7 @@ static bool dcn351_validate_bandwidth(struct dc *dc,
return out;
DC_FP_START();
- dcn351_decide_zstate_support(dc, context);
+ dcn35_decide_zstate_support(dc, context);
DC_FP_END();
return out;
--
2.43.0
[PATCH 15/25] drm/amd/display: Group scl_data together in resource_build_scaling_params
Move the scl_data.format to be close to other similar parts. Signed-off-by: Rodrigo Siqueira --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 2633e481234f..876b0e5eda95 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1500,9 +1500,6 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) return false; } - pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface( - pipe_ctx->plane_state->format); - /* Timing borders are part of vactive that we are also supposed to skip in addition * to any stream dst offset. Since dm logic assumes dst is in addressable * space we need to add the left and top borders to dst offsets temporarily. @@ -1514,6 +1511,8 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) /* Calculate H and V active size */ pipe_ctx->plane_res.scl_data.h_active = odm_slice_rec.width; pipe_ctx->plane_res.scl_data.v_active = odm_slice_rec.height; + pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface( + pipe_ctx->plane_state->format); /* depends on h_active */ calculate_recout(pipe_ctx); -- 2.43.0
[PATCH 11/25] drm/amd/display: Use dce_version instead of chip_id
The chip ID DEVICE_ID_NV_13FE is not meaningful and represents a legacy
way of dealing with chip ID. This commit uses dc_version instead of
chip_id and also DCN_VERSION_2_01 instead of DEVICE_ID_NV_13FE.
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
index c1a5908b97c8..a2b4ff2cff16 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
@@ -272,7 +272,7 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx,
struct pp_smu_funcs *p
dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
return &clk_mgr->base;
}
- if (asic_id.chip_id == DEVICE_ID_NV_13FE) {
+ if (ctx->dce_version == DCN_VERSION_2_01) {
dcn201_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
return &clk_mgr->base;
}
--
2.43.0
[PATCH 13/25] drm/amd/display: Improve the log precision
From: "Bitnun, Ethan"
The previous assumption that there will be an optimize_bandwidth call
following every prepare_bandwidth call was incorrect and caused small
inaccuracies in logging, as some info was only updated in later prepare
calls.
Signed-off-by: Ethan Bitnun
Reviewed-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index 358a83b1114b..7eecb3403f74 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -830,7 +830,7 @@ static void dcn32_update_clocks(struct clk_mgr
*clk_mgr_base,
dmcu->funcs->set_psr_wait_loop(dmcu,
clk_mgr_base->clks.dispclk_khz / 1000 / 7);
- if (dc->config.enable_auto_dpm_test_logs && safe_to_lower) {
+ if (dc->config.enable_auto_dpm_test_logs) {
dcn32_auto_dpm_test_log(new_clocks, clk_mgr, context);
}
}
--
2.43.0
[PATCH 14/25] drm/amd/display: Fix PSR command version passed
From: Mikita Lipski [why] Driver was passing a wrong command version which to DMCUB which caused the DMCUB to treat it as 0, so it wouldn't support dual eDP and would override the panel index to 0 instead of choosing between 0/1. [how] Use DMUB_CMD_PSR_CONTROL_VERSION_1 instead of PSR_VERSION_1. Signed-off-by: Mikita Lipski Reviewed-by: Rodrigo Siqueira --- drivers/gpu/drm/amd/display/dc/core/dc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 01c75b66e8f1..8eefba757da4 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -3446,6 +3446,7 @@ void dc_dmub_update_dirty_rect(struct dc *dc, if (srf_updates[i].surface->flip_immediate) continue; + update_dirty_rect->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count; memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects, sizeof(flip_addr->dirty_rects)); -- 2.43.0
[PATCH 17/25] drm/amd/display: Update some comments to improve the code readability
This commit updates some comments to be more precise and adds another
small comment to some other parts to improve the code readability.
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dc.h | 10 +-
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 2 +-
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubp.c | 5 +
3 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 188f2d401124..4e36a4f9a4a8 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -309,12 +309,12 @@ struct dc_dcc_setting {
unsigned int max_compressed_blk_size;
unsigned int max_uncompressed_blk_size;
bool independent_64b_blks;
- //These bitfields to be used starting with DCN
+ //These bitfields to be used starting with DCN 3.0
struct {
- uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the
worst compression case)
- uint32_t dcc_128_128_uncontrained : 1; //available in ASICs
before DCN
- uint32_t dcc_256_128_128 : 1; //available starting
with DCN
- uint32_t dcc_256_256_unconstrained : 1; //available in ASICs
before DCN (the best compression case)
+ uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0
(the worst compression case)
+ uint32_t dcc_128_128_uncontrained : 1; //available in ASICs
before DCN 3.0
+ uint32_t dcc_256_128_128 : 1; //available starting
with DCN 3.0
+ uint32_t dcc_256_256_unconstrained : 1; //available in ASICs
before DCN 3.0 (the best compression case)
} dcc_controls;
};
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
index efa2adf4f83d..8da3084d933f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
@@ -147,7 +147,7 @@
uint32_t DCN_CUR1_TTU_CNTL1;\
uint32_t VMID_SETTINGS_0
-
+/*shared with dcn3.x*/
#define DCN21_HUBP_REG_COMMON_VARIABLE_LIST \
DCN2_HUBP_REG_COMMON_VARIABLE_LIST; \
uint32_t FLIP_PARAMETERS_3;\
diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubp.c
b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubp.c
index 35dd4bac242a..cd2bfcc51276 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubp.c
@@ -77,6 +77,7 @@ static void hubp201_program_requestor(struct hubp *hubp,
MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
+ /* no need to program PTE */
REG_SET_5(DCHUBP_REQ_SIZE_CONFIG, 0,
CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
@@ -99,6 +100,10 @@ static void hubp201_setup(
struct _vcs_dpi_display_rq_regs_st *rq_regs,
struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
{
+ /*
+* otg is locked when this func is called. Register are double buffered.
+* disable the requestors is not needed
+*/
hubp2_vready_at_or_After_vsync(hubp, pipe_dest);
hubp201_program_requestor(hubp, rq_regs);
hubp201_program_deadline(hubp, dlg_attr, ttu_attr);
--
2.43.0
[PATCH 10/25] drm/amd/display: Expand dmub_cmd operations
From: Anthony Koo
Update dmub_cmd to manipulate SDP control in replay FSM, add command
for panel_cntl, expand link rate enum, and increase the reserve byte.
Acked-by: Rodrigo Siqueira
Signed-off-by: Anthony Koo
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 53 ++-
1 file changed, 52 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 944f14307517..e85fd3ac52c7 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -1614,7 +1614,7 @@ struct dmub_rb_cmd_idle_opt_dcn_restore {
*/
struct dmub_dcn_notify_idle_cntl_data {
uint8_t driver_idle;
- uint8_t pad[1];
+ uint8_t reserved[59];
};
/**
@@ -2335,6 +2335,11 @@ enum phy_link_rate {
* UHBR10 - 20.0 Gbps/Lane
*/
PHY_RATE_2000 = 11,
+
+ PHY_RATE_675 = 12,
+ /**
+* Rate 12 - 6.75 Gbps/Lane
+*/
};
/**
@@ -3062,6 +3067,11 @@ enum dmub_cmd_replay_type {
* Set pseudo vtotal
*/
DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7,
+ /**
+* Set adaptive sync sdp enabled
+*/
+ DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8,
+
};
/**
@@ -3263,6 +3273,20 @@ struct dmub_cmd_replay_set_pseudo_vtotal {
*/
uint8_t pad;
};
+struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data {
+ /**
+* Panel Instance.
+* Panel isntance to identify which replay_state to use
+* Currently the support is only for 0 or 1
+*/
+ uint8_t panel_inst;
+ /**
+* enabled: set adaptive sync sdp enabled
+*/
+ uint8_t force_disabled;
+
+ uint8_t pad[2];
+};
/**
* Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
@@ -3366,6 +3390,20 @@ struct dmub_rb_cmd_replay_set_pseudo_vtotal {
struct dmub_cmd_replay_set_pseudo_vtotal data;
};
+/**
+ * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command.
+ */
+struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp {
+ /**
+* Command header.
+*/
+ struct dmub_cmd_header header;
+ /**
+* Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command.
+*/
+ struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data;
+};
+
/**
* Data passed from driver to FW in
DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command.
*/
@@ -3421,6 +3459,11 @@ union dmub_replay_cmd_set {
* Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data.
*/
struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data;
+ /**
+* Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command
data.
+*/
+ struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data
disabled_adaptive_sync_sdp_data;
+
};
/**
@@ -4096,6 +4139,10 @@ enum dmub_cmd_panel_cntl_type {
* Queries backlight info for the embedded panel.
*/
DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1,
+ /**
+* Sets the PWM Freq as per user's requirement.
+*/
+ DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2,
};
/**
@@ -4667,6 +4714,10 @@ union dmub_rb_cmd {
* Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.
*/
struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal;
+ /**
+* Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command.
+*/
+ struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp
replay_disabled_adaptive_sync_sdp;
/**
* Definition of a DMUB_CMD__PSP_ASSR_ENABLE command.
*/
--
2.43.0
[PATCH 16/25] drm/amd/display: Replace int with unsigned int
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index ee6493a9a79c..5c7e4884cac2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -495,7 +495,7 @@ bool dc_stream_remove_writeback(struct dc *dc,
struct dc_stream_state *stream,
uint32_t dwb_pipe_inst)
{
- int i = 0, j = 0;
+ unsigned int i, j;
if (stream == NULL) {
dm_error("DC: dc_stream is NULL!\n");
return false;
--
2.43.0
[PATCH 23/25] drm/amd/display: Add missing callback for init_watermarks in DCN 301
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.c
b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.c
index a046664e2031..c1959672df50 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.c
@@ -63,6 +63,7 @@ static const struct hubbub_funcs hubbub301_funcs = {
.verify_allow_pstate_change_high =
hubbub1_verify_allow_pstate_change_high,
.force_wm_propagate_to_pipes = hubbub3_force_wm_propagate_to_pipes,
.force_pstate_change_control = hubbub3_force_pstate_change_control,
+ .init_watermarks = hubbub3_init_watermarks,
.hubbub_read_state = hubbub2_read_state,
};
--
2.43.0
[PATCH 18/25] drm/amd/display: Remove unnecessary code
This commit groups many parts of the code that are redundant or not used
and drops all of them.
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dc.h| 1 -
.../gpu/drm/amd/display/dc/dce/dce_i2c_hw.c| 3 ---
.../amd/display/dc/dcn10/dcn10_link_encoder.h | 6 --
.../gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h | 18 --
.../gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c | 2 --
5 files changed, 30 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 4e36a4f9a4a8..6a88423b7188 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1006,7 +1006,6 @@ struct dc_debug_options {
unsigned int force_cositing;
};
-struct gpu_info_soc_bounding_box_v1_0;
/* Generic structure that can be used to query properties of DC. More fields
* can be added as required.
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
index 744c335718a7..ee601a6897a1 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
@@ -312,9 +312,6 @@ static bool setup_engine(
/* we have checked I2c not used by DMCU, set SW use I2C REQ to 1 to
indicate SW using it*/
REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, 1);
- /* we have checked I2c not used by DMCU, set SW use I2C REQ to 1 to
indicate SW using it*/
- REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, 1);
-
/*set SW requested I2c speed to default, if API calls in it will be
override later*/
set_speed(dce_i2c_hw, dce_i2c_hw->ctx->dc->caps.i2c_speed_in_khz);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
index d980e6bd6c66..b7a89c39f445 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
@@ -167,7 +167,6 @@ struct dcn10_link_enc_registers {
uint32_t DIO_LINKD_CNTL;
uint32_t DIO_LINKE_CNTL;
uint32_t DIO_LINKF_CNTL;
- uint32_t DIG_FIFO_CTRL0;
uint32_t DIO_CLK_CNTL;
uint32_t DIG_BE_CLK_CNTL;
};
@@ -475,9 +474,6 @@ struct dcn10_link_enc_registers {
type HPO_DP_ENC_SEL;\
type HPO_HDMI_ENC_SEL
-#define DCN32_LINK_ENCODER_REG_FIELD_LIST(type) \
- type DIG_FIFO_OUTPUT_PIXEL_MODE
-
#define DCN35_LINK_ENCODER_REG_FIELD_LIST(type) \
type DIG_BE_ENABLE;\
type DIG_RB_SWITCH_EN;\
@@ -512,7 +508,6 @@ struct dcn10_link_enc_shift {
DCN20_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
DCN30_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
DCN31_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
- DCN32_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
DCN35_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
};
@@ -521,7 +516,6 @@ struct dcn10_link_enc_mask {
DCN20_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
DCN30_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
DCN31_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
- DCN32_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
DCN35_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
};
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h
index 35a613bb08bf..08a57ea4591c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h
@@ -29,13 +29,6 @@
#include "dcn20/dcn20_dccg.h"
-#define DCCG_REG_LIST_DCN3AG() \
- DCCG_COMMON_REG_LIST_DCN_BASE(),\
- SR(PHYASYMCLK_CLOCK_CNTL),\
- SR(PHYBSYMCLK_CLOCK_CNTL),\
- SR(PHYCSYMCLK_CLOCK_CNTL)
-
-
#define DCCG_REG_LIST_DCN30() \
DCCG_REG_LIST_DCN2(),\
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
@@ -46,17 +39,6 @@
SR(PHYBSYMCLK_CLOCK_CNTL),\
SR(PHYCSYMCLK_CLOCK_CNTL)
-#define DCCG_MASK_SH_LIST_DCN3AG(mask_sh) \
- DCCG_MASK_SH_LIST_DCN2_1(mask_sh),\
- DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_EN, mask_sh),\
- DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_SRC_SEL, mask_sh),\
- DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\
- DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\
- DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\
- DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\
- DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
- DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh)
-
#define DCCG_MASK_SH_LIST_DCN3(mask_sh) \
DCCG_MASK_SH_LIST_DCN2(mask_sh),\
DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c
index 1b9d9495f76d..fae98cf52020 100644
--- a/drivers/gpu/drm/a
[PATCH 24/25] drm/amd/display: Add missing replay field
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dc_types.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h
b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 614d7c27c759..0f66d00ef80f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -1050,6 +1050,8 @@ union replay_error_status {
struct replay_config {
/* Replay feature is supported */
bool replay_supported;
+ /* Replay caps support DPCD & EDID caps*/
+ bool replay_cap_support;
/* Power opt flags that are supported */
unsigned int replay_power_opt_supported;
/* SMU optimization is supported */
--
2.43.0
[PATCH 20/25] drm/amd/display: Rework dcn10_stream_encoder header
This commit remove some unused code and also rename one of the define.
Signed-off-by: Rodrigo Siqueira
---
.../drm/amd/display/dc/dcn10/dcn10_stream_encoder.h| 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
index c429590f1298..1b96972b9d0f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
@@ -127,7 +127,6 @@ struct dcn10_stream_enc_registers {
uint32_t AFMT_60958_1;
uint32_t AFMT_60958_2;
uint32_t DIG_FE_CNTL;
- uint32_t DIG_FE_CNTL2;
uint32_t DIG_FIFO_STATUS;
uint32_t DP_MSE_RATE_CNTL;
uint32_t DP_MSE_RATE_UPDATE;
@@ -570,7 +569,7 @@ struct dcn10_stream_enc_registers {
type DP_SEC_GSP11_ENABLE;\
type DP_SEC_GSP11_LINE_NUM
-#define SE_REG_FIELD_LIST_DCN3_2(type) \
+#define SE_REG_FIELD_LIST_DCN3_1_COMMON(type) \
type DIG_FIFO_OUTPUT_PIXEL_MODE;\
type DP_PIXEL_PER_CYCLE_PROCESSING_MODE;\
type DIG_SYMCLK_FE_ON;\
@@ -599,7 +598,7 @@ struct dcn10_stream_encoder_shift {
uint8_t HDMI_ACP_SEND;
SE_REG_FIELD_LIST_DCN2_0(uint8_t);
SE_REG_FIELD_LIST_DCN3_0(uint8_t);
- SE_REG_FIELD_LIST_DCN3_2(uint8_t);
+ SE_REG_FIELD_LIST_DCN3_1_COMMON(uint8_t);
SE_REG_FIELD_LIST_DCN3_5_COMMON(uint8_t);
};
@@ -608,7 +607,7 @@ struct dcn10_stream_encoder_mask {
uint32_t HDMI_ACP_SEND;
SE_REG_FIELD_LIST_DCN2_0(uint32_t);
SE_REG_FIELD_LIST_DCN3_0(uint32_t);
- SE_REG_FIELD_LIST_DCN3_2(uint32_t);
+ SE_REG_FIELD_LIST_DCN3_1_COMMON(uint32_t);
SE_REG_FIELD_LIST_DCN3_5_COMMON(uint32_t);
};
@@ -667,9 +666,6 @@ void enc1_stream_encoder_send_immediate_sdp_message(
void enc1_stream_encoder_stop_dp_info_packets(
struct stream_encoder *enc);
-void enc1_stream_encoder_reset_fifo(
- struct stream_encoder *enc);
-
void enc1_stream_encoder_dp_blank(
struct dc_link *link,
struct stream_encoder *enc);
--
2.43.0
[PATCH 19/25] drm/amd/display: Update FMT settings for 4:2:0
From: Eric Bernstein [Why] Update FMT_CONTROL settings based on HW spec [How] Update FMT settings for 4:2:0 Signed-off-by: Eric Bernstein Reviewed-by: Rodrigo Siqueira --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 9 - drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 2 ++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c index 5838a11efd00..71e9288d60ed 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c @@ -168,6 +168,10 @@ static void opp1_set_pixel_encoding( case PIXEL_ENCODING_RGB: case PIXEL_ENCODING_YCBCR444: + REG_UPDATE_3(FMT_CONTROL, + FMT_PIXEL_ENCODING, 0, + FMT_SUBSAMPLING_MODE, 0, + FMT_CBCR_BIT_REDUCTION_BYPASS, 0); REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 0); break; case PIXEL_ENCODING_YCBCR422: @@ -177,7 +181,10 @@ static void opp1_set_pixel_encoding( FMT_CBCR_BIT_REDUCTION_BYPASS, 0); break; case PIXEL_ENCODING_YCBCR420: - REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 2); + REG_UPDATE_3(FMT_CONTROL, + FMT_PIXEL_ENCODING, 2, + FMT_SUBSAMPLING_MODE, 2, + FMT_CBCR_BIT_REDUCTION_BYPASS, 1); break; default: break; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h index 2c0ecfa5a643..c87de68a509e 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h @@ -79,6 +79,8 @@ OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh), \ OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh), \ OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh), \ + OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh), \ + OPP_SF(FMT0_FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh), \ OPP_SF(FMT0_FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh), \ OPP_SF(FMT0_FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh), \ OPP_SF(FMT0_FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh), \ -- 2.43.0
[PATCH 09/25] drm/amd/display: Rework power sequence and resource allocation logic
From: Sung Joon Kim
Rework part of the modifications made to the power sequence and resource
allocation logic.
Reviewed-by: Xi (Alex) Liu
Acked-by: Rodrigo Siqueira
Signed-off-by: Sung Joon Kim
---
.../amd/display/dc/hwss/dcn351/dcn351_init.c | 8 ++---
.../dc/resource/dcn351/dcn351_resource.c | 36 +--
.../dc/resource/dcn351/dcn351_resource.h | 6
3 files changed, 5 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
index c4944478ed91..a53092cd619b 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
@@ -116,10 +116,10 @@ static const struct hw_sequencer_funcs dcn351_funcs = {
.update_visual_confirm_color = dcn10_update_visual_confirm_color,
.apply_idle_power_optimizations = dcn35_apply_idle_power_optimizations,
.update_dsc_pg = dcn32_update_dsc_pg,
- .calc_blocks_to_gate = dcn351_calc_blocks_to_gate,
- .calc_blocks_to_ungate = dcn351_calc_blocks_to_ungate,
- .hw_block_power_up = dcn351_hw_block_power_up,
- .hw_block_power_down = dcn351_hw_block_power_down,
+ .calc_blocks_to_gate = dcn35_calc_blocks_to_gate,
+ .calc_blocks_to_ungate = dcn35_calc_blocks_to_ungate,
+ .hw_block_power_up = dcn35_hw_block_power_up,
+ .hw_block_power_down = dcn35_hw_block_power_down,
.root_clock_control = dcn35_root_clock_control,
};
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
index b29d7d47552b..3acfbbac8538 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
@@ -1728,38 +1728,6 @@ static bool dcn351_validate_bandwidth(struct dc *dc,
return out;
}
-struct pipe_ctx *dcn351_acquire_free_pipe_as_secondary_dpp_pipe(
- const struct dc_state *cur_ctx,
- struct dc_state *new_ctx,
- const struct resource_pool *pool,
- const struct pipe_ctx *opp_head_pipe)
-{
- int free_pipe_idx;
- struct pipe_ctx *free_pipe;
-
- free_pipe_idx = dcn32_find_optimal_free_pipe_as_secondary_dpp_pipe(
- &cur_ctx->res_ctx, &new_ctx->res_ctx,
- pool, opp_head_pipe);
- if (free_pipe_idx >= 0) {
- free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx];
- free_pipe->pipe_idx = free_pipe_idx;
- free_pipe->stream = opp_head_pipe->stream;
- free_pipe->stream_res.tg = opp_head_pipe->stream_res.tg;
- free_pipe->stream_res.opp = opp_head_pipe->stream_res.opp;
-
- free_pipe->plane_res.hubp = pool->hubps[free_pipe->pipe_idx];
- free_pipe->plane_res.ipp = pool->ipps[free_pipe->pipe_idx];
- free_pipe->plane_res.dpp = pool->dpps[free_pipe->pipe_idx];
- free_pipe->plane_res.mpcc_inst =
- pool->dpps[free_pipe->pipe_idx]->inst;
- } else {
- ASSERT(opp_head_pipe);
- free_pipe = NULL;
- }
-
- return free_pipe;
-}
-
static struct resource_funcs dcn351_res_pool_funcs = {
.destroy = dcn351_destroy_resource_pool,
.link_enc_create = dcn35_link_encoder_create,
@@ -1771,8 +1739,7 @@ static struct resource_funcs dcn351_res_pool_funcs = {
.calculate_wm_and_dlg = NULL,
.update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
.populate_dml_pipes = dcn351_populate_dml_pipes_from_context_fpu,
- .acquire_free_pipe_as_secondary_dpp_pipe =
dcn351_acquire_free_pipe_as_secondary_dpp_pipe,
- .acquire_free_pipe_as_secondary_opp_head =
dcn32_acquire_free_pipe_as_secondary_opp_head,
+ .acquire_free_pipe_as_secondary_dpp_pipe =
dcn20_acquire_free_pipe_for_layer,
.release_pipe = dcn20_release_pipe,
.add_stream_to_ctx = dcn30_add_stream_to_ctx,
.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
@@ -2162,7 +2129,6 @@ static bool dcn351_resource_construct(
dc->dml2_options.max_segments_per_hubp = 24;
dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/
- dc->dml2_options.map_dc_pipes_with_callbacks = true;
if (dc->config.sdpif_request_limit_words_per_umc == 0)
dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.h
b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.h
index e4553c5100f8..f3e045777a3d 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.h
+++ b/drive
[PATCH 22/25] drm/amd/display: Update DCN201 link encoder registers
Add some missing registers expansion in the dcn201_link_encoder file. Signed-off-by: Rodrigo Siqueira --- .../amd/display/dc/dcn201/dcn201_link_encoder.h| 14 +- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.h index 8b95ef251332..be25e8dc0636 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.h @@ -30,6 +30,10 @@ #define DPCS_DCN201_MASK_SH_LIST(mask_sh)\ DPCS_MASK_SH_LIST(mask_sh),\ + LE_SF(DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2, VCO_LD_VAL_OVRD, mask_sh),\ + LE_SF(DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2, VCO_LD_VAL_OVRD_EN, mask_sh),\ + LE_SF(DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3, REF_LD_VAL_OVRD, mask_sh),\ + LE_SF(DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3, REF_LD_VAL_OVRD_EN, mask_sh),\ LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL2, RDPCS_PHY_DPALT_DISABLE_ACK, mask_sh),\ LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL2, RDPCS_PHY_DPALT_DISABLE, mask_sh),\ LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL2, RDPCS_PHY_DPALT_DP4, mask_sh),\ @@ -44,7 +48,15 @@ LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_DP_REF_CLK_EN, mask_sh) #define DPCS_DCN201_REG_LIST(id) \ - DPCS_DCN2_CMN_REG_LIST(id) + DPCS_DCN2_CMN_REG_LIST(id), \ + SRI_IX(RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2, DPCSSYS_CR, id), \ + SRI_IX(RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3, DPCSSYS_CR, id), \ + SRI_IX(RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2, DPCSSYS_CR, id), \ + SRI_IX(RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3, DPCSSYS_CR, id), \ + SRI_IX(RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2, DPCSSYS_CR, id), \ + SRI_IX(RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3, DPCSSYS_CR, id), \ + SRI_IX(RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2, DPCSSYS_CR, id), \ + SRI_IX(RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3, DPCSSYS_CR, id) void dcn201_link_encoder_construct( struct dcn20_link_encoder *enc20, -- 2.43.0
[PATCH 25/25] drm/amd/display: 3.2.281
From: Aric Cyr This version brings along following fixes: * Expand dmub_cmd operations. * Update DVI configuration. * Modify power sequence. * Enable Z10 flag for IPS. * Multiple code cleanups. Acked-by: Rodrigo Siqueira Signed-off-by: Aric Cyr --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 6a88423b7188..3c33c3bcbe2c 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -53,7 +53,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.279" +#define DC_VER "3.2.281" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.43.0
[PATCH 21/25] drm/amd/display: Move REG sequence from program ogam to idle before connect
Fill ring buffer before offload. Signed-off-by: Rodrigo Siqueira --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c | 10 -- 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c index 16b5ff208d14..ea73473b970a 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c @@ -395,9 +395,12 @@ static void mpc20_program_ogam_pwl( MPCC_OGAM_LUT_DATA, rgb[i].delta_green_reg); REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].delta_blue_reg); - } + REG_SEQ_SUBMIT(); + PERF_TRACE(); + REG_SEQ_WAIT_DONE(); + PERF_TRACE(); } static void apply_DEDCN20_305_wa(struct mpc *mpc, int mpcc_id, @@ -501,11 +504,6 @@ void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id) ASSERT(!mpc_disabled); ASSERT(!mpc_idle); } - - REG_SEQ_SUBMIT(); - PERF_TRACE(); - REG_SEQ_WAIT_DONE(); - PERF_TRACE(); } static void mpc2_init_mpcc(struct mpcc *mpcc, int mpcc_inst) -- 2.43.0
[PATCH] Revert "drm/amd/display: Enable cur_rom_en even if cursor degamma is not enabled"
This reverts commit 5aba567a2988400d4e01d44493c84bed92820d8d.
The original patch introduces cursor gamma issue to multiple
Linux compositors. For this reason this commit reverts this change.
Cc: Melissa Wen
Cc: Harry Wentland
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
index ed1e2f65f5b5..f8c0cee34080 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
@@ -395,7 +395,9 @@ void dpp3_set_cursor_attributes(
if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA ||
color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) {
- cur_rom_en = 1;
+ if
(cursor_attributes->attribute_flags.bits.ENABLE_CURSOR_DEGAMMA) {
+ cur_rom_en = 1;
+ }
}
REG_UPDATE_3(CURSOR0_CONTROL,
--
2.43.0
[PATCH 2/6] Documentation/gpu: Remove ':export:' option from DCN documentation
This commit reduces, but does not fix, all the occurrences and some of the documentation warnings related to the 'no structured comments.' This was caused by the wrong use of the ':export:' option in the DCN kernel-doc, so this commit drops the usage of those options. Reported-by: Stephen Rothwell Signed-off-by: Rodrigo Siqueira --- Documentation/gpu/amdgpu/display/dcn-blocks.rst | 15 --- 1 file changed, 15 deletions(-) diff --git a/Documentation/gpu/amdgpu/display/dcn-blocks.rst b/Documentation/gpu/amdgpu/display/dcn-blocks.rst index 118aeb9fd2b4..582a5fee7f29 100644 --- a/Documentation/gpu/amdgpu/display/dcn-blocks.rst +++ b/Documentation/gpu/amdgpu/display/dcn-blocks.rst @@ -11,9 +11,6 @@ DCHUBBUB .. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h :doc: overview -.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h - :export: - .. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h :internal: @@ -23,9 +20,6 @@ HUBP .. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h :doc: overview -.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h - :export: - .. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h :internal: @@ -35,9 +29,6 @@ DPP .. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h :doc: overview -.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h - :export: - .. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h :internal: @@ -47,9 +38,6 @@ MPC .. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h :doc: overview -.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h - :export: - .. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h :internal: @@ -59,9 +47,6 @@ OPP .. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/opp.h :doc: overview -.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/opp.h - :export: - .. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/opp.h :internal: -- 2.43.0
[PATCH 1/6] drm/amd/display: Move DIO documentation to the right place
When building the kernel-doc, it complains with the below warning:
./drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h:1: warning: no
structured comments found
./drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h:1: warning: no
structured comments found
This warning was caused by the wrong use of the ':export:' and the lack
of function documentation in the file pointed under the ':internal:'.
This commit addresses those issues by relocating the overview
documentation to the correct C file, removing the ':export:' options,
and adding two simple kernel-doc to ensure that ':internal:' does not
have any warning.
Cc: Alex Deucher
Reported-by: Stephen Rothwell
Link:
https://lore.kernel.org/dri-devel/20240715085918.68f5e...@canb.auug.org.au/
Signed-off-by: Rodrigo Siqueira
---
.../gpu/amdgpu/display/dcn-blocks.rst | 7 ++---
.../amd/display/dc/link/hwss/link_hwss_dio.c | 29 +++
.../amd/display/dc/link/hwss/link_hwss_dio.h | 9 --
3 files changed, 31 insertions(+), 14 deletions(-)
diff --git a/Documentation/gpu/amdgpu/display/dcn-blocks.rst
b/Documentation/gpu/amdgpu/display/dcn-blocks.rst
index a3fbd3ea028b..118aeb9fd2b4 100644
--- a/Documentation/gpu/amdgpu/display/dcn-blocks.rst
+++ b/Documentation/gpu/amdgpu/display/dcn-blocks.rst
@@ -68,11 +68,8 @@ OPP
DIO
---
-.. kernel-doc:: drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h
+.. kernel-doc:: drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c
:doc: overview
-.. kernel-doc:: drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h
- :export:
-
-.. kernel-doc:: drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h
+.. kernel-doc:: drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c
:internal:
diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c
b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c
index 81e335280e0f..3e47a6735912 100644
--- a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c
+++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c
@@ -26,6 +26,16 @@
#include "core_types.h"
#include "link_enc_cfg.h"
+/**
+ * DOC: overview
+ *
+ * Display Input Output (DIO), is the display input and output unit in DCN. It
+ * includes output encoders to support different display output, like
+ * DisplayPort, HDMI, DVI interface, and others. It also includes the control
+ * and status channels for these interfaces.
+ */
+
+
void set_dio_throttled_vcp_size(struct pipe_ctx *pipe_ctx,
struct fixed31_32 throttled_vcp_size)
{
@@ -257,12 +267,31 @@ static const struct link_hwss dio_link_hwss = {
},
};
+/**
+ * can_use_dio_link_hwss - Check if the link_hwss is accessible
+ *
+ * @link: Reference a link struct containing one or more sinks and the
+ * connective status.
+ * @link_res: Mappable hardware resource used to enable a link.
+ *
+ * Returns:
+ * Return true if the link encoder is accessible from link.
+ */
bool can_use_dio_link_hwss(const struct dc_link *link,
const struct link_resource *link_res)
{
return link->link_enc != NULL;
}
+/**
+ * get_dio_link_hwss - Return link_hwss reference
+ *
+ * This function behaves like a get function to return the link_hwss populated
+ * in the link_hwss_dio.c file.
+ *
+ * Returns:
+ * Return the reference to the filled struct of link_hwss.
+ */
const struct link_hwss *get_dio_link_hwss(void)
{
return &dio_link_hwss;
diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h
b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h
index a1f72fe378ee..45f0e091fcb0 100644
--- a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h
+++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h
@@ -23,15 +23,6 @@
*
*/
-/**
- * DOC: overview
- *
- * Display Input Output (DIO), is the display input and output unit in DCN. It
- * includes output encoders to support different display output, like
- * DisplayPort, HDMI, DVI interface, and others. It also includes the control
- * and status channels for these interfaces.
- */
-
#ifndef __LINK_HWSS_DIO_H__
#define __LINK_HWSS_DIO_H__
--
2.43.0
[PATCH 3/6] Documentation/gpu: Adjust DCN documentation paths
When building the kernel-doc, it has the following complaints: Documentation/gpu/amdgpu/display/dcn-blocks:23: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h:3: WARNING: Duplicate C declaration, also defined at gpu/amdgpu/display/dcn-blocks:3. Declaration is '.. c:struct:: surface_flip_registers'. Documentation/gpu/amdgpu/display/dcn-blocks:35: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h:3: WARNING: Duplicate C declaration, also defined at gpu/amdgpu/display/dcn-blocks:3. Declaration is '.. c:struct:: surface_flip_registers'. This error happened due to a copy-and-paste where the same file path was duplicated multiple times to a different set of blocks. This commit addresses this issue by using the correct file path. Cc: Alex Deucher Reported-by: Stephen Rothwell Signed-off-by: Rodrigo Siqueira --- Documentation/gpu/amdgpu/display/dcn-blocks.rst | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/gpu/amdgpu/display/dcn-blocks.rst b/Documentation/gpu/amdgpu/display/dcn-blocks.rst index 582a5fee7f29..00bc0607e98c 100644 --- a/Documentation/gpu/amdgpu/display/dcn-blocks.rst +++ b/Documentation/gpu/amdgpu/display/dcn-blocks.rst @@ -8,10 +8,10 @@ and the code documentation when it is automatically generated. DCHUBBUB -.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h :doc: overview -.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h :internal: HUBP @@ -26,10 +26,10 @@ HUBP DPP --- -.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h :doc: overview -.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h :internal: MPC -- 2.43.0
[PATCH 0/6] drm/amd/display: Address kernel doc warnings
This patchset fixes many of the kernel-doc warnings caused by the display documentation. This series addresses the following warnings: ./drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h:1: warning: no structured comments found ./drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h:1: warning: no structured comments found ./drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h:1: warning: no structured comments found ./drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h:1: warning: no structured comments found ./drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h:1: warning: no structured comments found ./drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h:1: warning: no structured comments found ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:1: warning: no structured comments found ./drivers/gpu/drm/amd/display/dc/inc/hw/opp.h:1: warning: no structured comments found ./drivers/gpu/drm/amd/display/dc/inc/hw/opp.h:1: warning: no structured comments found ./drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h:1: warning: no structured comments found ./drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h:1: warning: no structured comments found /home/siqueira/Documents/Repositories/kernels/amd-next_dal-dev/Documentation/gpu/amdgpu/display/display-manager:134: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:3: WARNING: Duplicate C declaration, also defined at gpu/amdgpu/display/dcn-blocks:101. Declaration is '.. c:struct:: mpcc_blnd_cfg'. /home/siqueira/Documents/Repositories/kernels/amd-next_dal-dev/Documentation/gpu/amdgpu/display/display-manager:146: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:3: WARNING: Duplicate C declaration, also defined at gpu/amdgpu/display/dcn-blocks:3. Declaration is '.. c:enum:: mpcc_alpha_blend_mode'. /home/siqueira/Documents/Repositories/kernels/amd-next_dal-dev/Documentation/gpu/amdgpu/display/display-manager.rst:3: WARNING: Duplicate C declaration, also defined at gpu/amdgpu/display/dcn-blocks:101. Declaration is '.. c:struct:: mpcc_blnd_cfg'. /home/siqueira/Documents/Repositories/kernels/amd-next_dal-dev/Documentation/gpu/amdgpu/display/display-manager.rst:3: WARNING: Duplicate C declaration, also defined at gpu/amdgpu/display/dcn-blocks:3. Declaration is '.. c:enum:: mpcc_alpha_blend_mode'. I tested it on amd-staging-drm-next. Cc: Alex Deucher Cc: Stephen Rothwell Thanks Siqueira Rodrigo Siqueira (6): drm/amd/display: Move DIO documentation to the right place Documentation/gpu: Remove ':export:' option from DCN documentation Documentation/gpu: Adjust DCN documentation paths drm/amd/display: Add simple struct doc to remove doc build warning Documentation/gpu: Remove undocumented files from dcn-blockshubbub.h Documentation/amdgpu: Fix duplicate declaration .../gpu/amdgpu/display/dcn-blocks.rst | 35 --- .../gpu/amdgpu/display/display-manager.rst| 4 +-- drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 22 +--- drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 15 .../amd/display/dc/link/hwss/link_hwss_dio.c | 29 +++ .../amd/display/dc/link/hwss/link_hwss_dio.h | 9 - 6 files changed, 69 insertions(+), 45 deletions(-) -- 2.43.0
[PATCH 4/6] drm/amd/display: Add simple struct doc to remove doc build warning
This commit is a part of a series that addresses the following build
warning for opp:
./drivers/gpu/drm/amd/display/dc/inc/hw/opp.h:1: warning: no structured
comments found
./drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h:1: warning: no structured
comments found
This commit fixes this issue by adding a simple kernel-doc to a struct
in the opp.h and the dpp.h files.
Cc: Alex Deucher
Reported-by: Stephen Rothwell
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 22 -
drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 15 ++
2 files changed, 32 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
index 9ac7fc717a92..0150f2581ee4 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
@@ -147,16 +147,28 @@ struct cnv_color_keyer_params {
int color_keyer_blue_high;
};
-/* new for dcn2: set the 8bit alpha values based on the 2 bit alpha
- *ALPHA_2BIT_LUT. ALPHA_2BIT_LUT0 default: 0b
- *ALPHA_2BIT_LUT. ALPHA_2BIT_LUT1 default: 0b01010101
- *ALPHA_2BIT_LUT. ALPHA_2BIT_LUT2 default: 0b10101010
- *ALPHA_2BIT_LUT. ALPHA_2BIT_LUT3 default: 0b
+/**
+ * struct cnv_alpha_2bit_lut - Set the 8bit alpha values based on the 2 bit
alpha
*/
struct cnv_alpha_2bit_lut {
+ /**
+ * @lut0: ALPHA_2BIT_LUT. ALPHA_2BIT_LUT0. Default: 0b
+ */
int lut0;
+
+ /**
+* @lut1: ALPHA_2BIT_LUT. ALPHA_2BIT_LUT1. Default: 0b01010101
+*/
int lut1;
+
+ /**
+* @lut2: ALPHA_2BIT_LUT. ALPHA_2BIT_LUT2. Default: 0b10101010
+*/
int lut2;
+
+ /**
+* @lut3: ALPHA_2BIT_LUT. ALPHA_2BIT_LUT3. Default: 0b
+*/
int lut3;
};
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
index 127fb1a51654..747679cb4944 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
@@ -205,9 +205,24 @@ struct gamma_coefficients {
struct fixed31_32 user_brightness;
};
+/**
+ * struct pwl_float_data - Fixed point RGB color
+ */
struct pwl_float_data {
+ /**
+* @r: Component Red.
+*/
struct fixed31_32 r;
+
+ /**
+* @g: Component Green.
+*/
+
struct fixed31_32 g;
+
+ /**
+* @b: Component Blue.
+*/
struct fixed31_32 b;
};
--
2.43.0
[PATCH 5/6] Documentation/gpu: Remove undocumented files from dcn-blockshubbub.h
The dchubbub.h and hubp.h do not have any meaningful documentation; for this reason, this commit removes those files from the dcn-blocks documentation. Cc: Alex Deucher Reported-by: Stephen Rothwell Signed-off-by: Rodrigo Siqueira --- Documentation/gpu/amdgpu/display/dcn-blocks.rst | 6 -- 1 file changed, 6 deletions(-) diff --git a/Documentation/gpu/amdgpu/display/dcn-blocks.rst b/Documentation/gpu/amdgpu/display/dcn-blocks.rst index 00bc0607e98c..f80df596ef5c 100644 --- a/Documentation/gpu/amdgpu/display/dcn-blocks.rst +++ b/Documentation/gpu/amdgpu/display/dcn-blocks.rst @@ -11,18 +11,12 @@ DCHUBBUB .. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h :doc: overview -.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h - :internal: - HUBP .. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h :doc: overview -.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h - :internal: - DPP --- -- 2.43.0
[PATCH 6/6] Documentation/amdgpu: Fix duplicate declaration
Address the below kernel doc warning: Documentation/gpu/amdgpu/display/display-manager:134: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:3: WARNING: Duplicate C declaration, also defined at gpu/amdgpu/display/dcn-blocks:101. Declaration is '.. c:struct:: mpcc_blnd_cfg'. Documentation/gpu/amdgpu/display/display-manager:146: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:3: WARNING: Duplicate C declaration, also defined at gpu/amdgpu/display/dcn-blocks:3. Declaration is '.. c:enum:: mpcc_alpha_blend_mode'. To address the above warnings, this commit uses the 'no-identifiers' option in the dcn-blocks to avoid duplication with the previous use of this function doc in the display-manager file. Finally, replaces the deprecated ':function:' in favor of ':identifiers:'. Cc: Alex Deucher Reported-by: Stephen Rothwell Signed-off-by: Rodrigo Siqueira --- Documentation/gpu/amdgpu/display/dcn-blocks.rst | 1 + Documentation/gpu/amdgpu/display/display-manager.rst | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/gpu/amdgpu/display/dcn-blocks.rst b/Documentation/gpu/amdgpu/display/dcn-blocks.rst index f80df596ef5c..5e34366f6dbe 100644 --- a/Documentation/gpu/amdgpu/display/dcn-blocks.rst +++ b/Documentation/gpu/amdgpu/display/dcn-blocks.rst @@ -34,6 +34,7 @@ MPC .. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h :internal: + :no-identifiers: mpcc_blnd_cfg mpcc_alpha_blend_mode OPP --- diff --git a/Documentation/gpu/amdgpu/display/display-manager.rst b/Documentation/gpu/amdgpu/display/display-manager.rst index 67a811e6891f..b269ff3f7a54 100644 --- a/Documentation/gpu/amdgpu/display/display-manager.rst +++ b/Documentation/gpu/amdgpu/display/display-manager.rst @@ -132,7 +132,7 @@ The DRM blend mode and its elements are then mapped by AMDGPU display manager (MPC), as follows: .. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h - :functions: mpcc_blnd_cfg + :identifiers: mpcc_blnd_cfg Therefore, the blending configuration for a single MPCC instance on the MPC tree is defined by :c:type:`mpcc_blnd_cfg`, where @@ -144,7 +144,7 @@ alpha and plane alpha values. It sets one of the three modes for :c:type:`MPCC_ALPHA_BLND_MODE`, as described below. .. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h - :functions: mpcc_alpha_blend_mode + :identifiers: mpcc_alpha_blend_mode DM then maps the elements of `enum mpcc_alpha_blend_mode` to those in the DRM blend formula, as follows: -- 2.43.0
[PATCH 00/39] DC Patches July 25, 2024
This DC patchset brings improvements in multiple areas. In summary, we have: - SPL improvements. - Address coverity issues. - DML2 fixes. - Code cleanup. - DIO and DCCG refactor. - Improve the PSR state. Cc: Daniel Wheeler Thanks Siqueira Alex Hung (7): drm/amd/display: Fix possible overflow in integer multiplication drm/amd/display: Check null pointers before using them drm/amd/display: Check stream_status before it is used drm/amd/display: Avoid overflow assignment in link_dp_cts drm/amd/display: Check null values from functions drm/amd/display: Initialize get_bytes_per_element's default to 1 drm/amd/display: Check UnboundedRequestEnabled's value Alvin Lee (2): drm/amd/display: Add option to disable unbounded req in DML21 drm/amd/display: For FAMS2 don't program P-State force from driver Aric Cyr (1): drm/amd/display: 3.2.294 Bhuvanachandra Pinninti (1): drm/amd/display: Refactor for dio Charlene Liu (2): drm/amd/display: restore immediate_disable_crtc for w/a drm/amd/display: sync dmub output event type. Chris Park (1): drm/amd/display: Add two dmmuy I2C entry for GPIO port mapping issue Cruise (2): drm/amd/display: Add logs for debugging outbox drm/amd/display: Get link index for AUX reply notification Daniel Sa (1): drm/amd/display: Underflow Seen on DCN401 eGPU Hansen Dsouza (2): drm/amd/display: Add new enable and disable functions drm/amd/display: Add new enable and disable functions for DCN35 Ilya Bakoulin (1): drm/amd/display: Use correct cm_helper function Leo Li (2): drm/amd/display: Let drm_crtc_vblank_on/off manage interrupts drm/amd/display: Run idle optimizations at end of vblank handler Meenakshikumar Somasundaram (1): drm/amd/display: Enable aux transfer path via dmub for dp tunneling Nicholas Kazlauskas (3): drm/amd/display: Request 0MHz dispclk for zero display case drm/amd/display: Add seamless boot support for more DIG operation modes drm/amd/display: Use gpuvm_min_page_size_kbytes for DML2 surfaces Rodrigo Siqueira (9): drm/amd/display: Re-order enum in a header file drm/amd/display: Setup two pixel per container drm/amd/display: Replace dm_execute_dmub_cmd with dc_wake_and_execute_dmub_cmd drm/amd/display: Add missing DET segments programming drm/amd/display: Remove duplicated code drm/amd/display: Add missing mcache registers drm/amd/display: Add dcc propagation value drm/amd/display: Add missing registers for dcn32 drm/amd/display: Remove unused code Samson Tam (1): drm/amd/display: roll back quality EASF and ISHARP and dc dependency changes Sung Lee (1): drm/amd/display: Fix Cursor Offset in Scaled Scenarios Tom Chung (2): drm/amd/display: Add a missing PSR state drm/amd/display: Reset VRR config during resume .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 46 +- .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c| 60 +- drivers/gpu/drm/amd/display/dc/Makefile |1 - .../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c |4 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 14 +- .../gpu/drm/amd/display/dc/core/dc_resource.c |2 + drivers/gpu/drm/amd/display/dc/core/dc_stat.c |1 + drivers/gpu/drm/amd/display/dc/dc.h |2 +- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c |3 + drivers/gpu/drm/amd/display/dc/dc_dp_types.h |2 +- .../gpu/drm/amd/display/dc/dc_spl_translate.c | 50 +- .../gpu/drm/amd/display/dc/dc_spl_translate.h |1 - drivers/gpu/drm/amd/display/dc/dc_types.h |1 + .../amd/display/dc/dccg/dcn35/dcn35_dccg.c| 266 ++- drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 10 +- drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c |2 + .../gpu/drm/amd/display/dc/dce/dmub_replay.c |3 +- .../gpu/drm/amd/display/dc/dcn301/Makefile|2 +- .../gpu/drm/amd/display/dc/dcn314/Makefile| 10 - drivers/gpu/drm/amd/display/dc/dio/Makefile | 18 + .../dcn301/dcn301_dio_link_encoder.c |0 .../dcn301/dcn301_dio_link_encoder.h |0 .../dcn314/dcn314_dio_stream_encoder.c|0 .../dcn314/dcn314_dio_stream_encoder.h|0 .../dc/dio/dcn321/dcn321_dio_link_encoder.c |1 - .../dc/dio/dcn35/dcn35_dio_stream_encoder.c | 20 +- .../dc/dml/dcn20/display_rq_dlg_calc_20v2.c |2 +- .../dc/dml/dcn21/display_rq_dlg_calc_21.c |2 +- .../dc/dml2/dml21/dml21_translation_helper.c | 13 +- .../src/dml2_core/dml2_core_dcn4_calcs.c |2 +- .../dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c |8 + .../display/dc/dml2/dml2_translation_helper.c | 20 +- .../drm/amd/display/dc/dml2/dml2_wrapper.c|2 +- .../display/dc/dpp/dcn401/dcn401_dpp_dscl.c | 568 +++--- .../dc/gpio/dcn401/hw_factory_dcn401.c| 16 +- .../amd/display/dc/hubp/dcn401/dcn401_hubp.c |5 +- .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c |2 + .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 30 +- .../amd/display/dc/hwss/dcn401/dcn401
[PATCH 02/39] drm/amd/display: Let drm_crtc_vblank_on/off manage interrupts
From: Leo Li
[Why]
We manage interrupts for CRTCs in two places:
1. In manage_dm_interrupts(), when CRTC get enabled or disabled
2. When drm_vblank_get/put() starts or kills the vblank counter, calling
into amdgpu_dm_crtc_set_vblank()
The interrupts managed by these twp places should be identical.
[How]
Since manage_dm_interrupts() already use drm_crtc_vblank_on/off(), just
move all CRTC interrupt management into amdgpu_dm_crtc_set_vblank().
This has the added benefit of disabling all CRTC and HUBP interrupts
when there are no vblank requestors.
Note that there is a TODO item - unchanged from when it was first
introduced - to properly identify the HUBP instance from the OTG
instance, rather than just assume direct mapping.
Signed-off-by: Leo Li
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 36 +-
.../amd/display/amdgpu_dm/amdgpu_dm_crtc.c| 48 +--
2 files changed, 47 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 1a8fc566e24d..4d36a66917c6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -8246,42 +8246,10 @@ static void manage_dm_interrupts(struct amdgpu_device
*adev,
struct amdgpu_crtc *acrtc,
bool enable)
{
- /*
-* We have no guarantee that the frontend index maps to the same
-* backend index - some even map to more than one.
-*
-* TODO: Use a different interrupt or check DC itself for the mapping.
-*/
- int irq_type =
- amdgpu_display_crtc_idx_to_irq_type(
- adev,
- acrtc->crtc_id);
-
- if (enable) {
+ if (enable)
drm_crtc_vblank_on(&acrtc->base);
- amdgpu_irq_get(
- adev,
- &adev->pageflip_irq,
- irq_type);
-#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
- amdgpu_irq_get(
- adev,
- &adev->vline0_irq,
- irq_type);
-#endif
- } else {
-#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
- amdgpu_irq_put(
- adev,
- &adev->vline0_irq,
- irq_type);
-#endif
- amdgpu_irq_put(
- adev,
- &adev->pageflip_irq,
- irq_type);
+ else
drm_crtc_vblank_off(&acrtc->base);
- }
}
static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
index 99014339aaa3..1fe038616d9f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
@@ -286,11 +286,14 @@ static inline int amdgpu_dm_crtc_set_vblank(struct
drm_crtc *crtc, bool enable)
struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
struct amdgpu_display_manager *dm = &adev->dm;
struct vblank_control_work *work;
+ int irq_type;
int rc = 0;
if (acrtc->otg_inst == -1)
goto skip;
+ irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
+
if (enable) {
/* vblank irq on -> Only need vupdate irq in vrr mode */
if (amdgpu_dm_crtc_vrr_active(acrtc_state))
@@ -303,13 +306,52 @@ static inline int amdgpu_dm_crtc_set_vblank(struct
drm_crtc *crtc, bool enable)
if (rc)
return rc;
- rc = (enable)
- ? amdgpu_irq_get(adev, &adev->crtc_irq, acrtc->crtc_id)
- : amdgpu_irq_put(adev, &adev->crtc_irq, acrtc->crtc_id);
+ /* crtc vblank or vstartup interrupt */
+ if (enable) {
+ rc = amdgpu_irq_get(adev, &adev->crtc_irq, irq_type);
+ drm_dbg_vbl(crtc->dev, "Get crtc_irq ret=%d\n", rc);
+ } else {
+ rc = amdgpu_irq_put(adev, &adev->crtc_irq, irq_type);
+ drm_dbg_vbl(crtc->dev, "Put crtc_irq ret=%d\n", rc);
+ }
if (rc)
return rc;
+ /*
+* hubp surface flip interrupt
+*
+* We have no guarantee that the frontend index maps to the same
+* backend index - some even map to more than one.
+*
+* TODO: Use a different interrupt or check DC itself for the mapping.
+*/
+ if (enable) {
+ rc = amdgpu_irq_get(adev, &adev->pageflip_irq, irq_type);
+ drm_
[PATCH 03/39] drm/amd/display: Run idle optimizations at end of vblank handler
From: Leo Li
[Why & How]
1. After allowing idle optimizations, hw programming is disallowed.
2. Before hw programming, we need to disallow idle optimizations.
Otherwise, in scenario 1, we will immediately kick hw out of idle
optimizations with register access.
Scenario 2 is less of a concern, since any register access will kick
hw out of idle optimizations. But we'll do it early for correctness.
Signed-off-by: Leo Li
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
index 1fe038616d9f..a2cf2c066a76 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
@@ -251,9 +251,10 @@ static void amdgpu_dm_crtc_vblank_control_worker(struct
work_struct *work)
else if (dm->active_vblank_irq_count)
dm->active_vblank_irq_count--;
- dc_allow_idle_optimizations(dm->dc, dm->active_vblank_irq_count == 0);
-
- DRM_DEBUG_KMS("Allow idle optimizations (MALL): %d\n",
dm->active_vblank_irq_count == 0);
+ if (dm->active_vblank_irq_count > 0) {
+ DRM_DEBUG_KMS("Allow idle optimizations (MALL): false\n");
+ dc_allow_idle_optimizations(dm->dc, false);
+ }
/*
* Control PSR based on vblank requirements from OS
@@ -272,6 +273,11 @@ static void amdgpu_dm_crtc_vblank_control_worker(struct
work_struct *work)
vblank_work->stream->link->replay_settings.replay_feature_enabled);
}
+ if (dm->active_vblank_irq_count == 0) {
+ DRM_DEBUG_KMS("Allow idle optimizations (MALL): true\n");
+ dc_allow_idle_optimizations(dm->dc, true);
+ }
+
mutex_unlock(&dm->dc_lock);
dc_stream_release(vblank_work->stream);
--
2.43.0
[PATCH 05/39] drm/amd/display: Request 0MHz dispclk for zero display case
From: Nicholas Kazlauskas [Why] If we aren't entering RCG/IPS2 or CLKSTOP is not supported by PMFW then we should be requesting a dispclk value of 0MHz to PMFW. Currenly we run at max clock since there's an assumption in APU clock table formulation where we can run at any DISPCLK at any state so the real clock value ends up as 1200Mhz - the maximum. [How] Set to 0 instead of the minimum value in the state array. Signed-off-by: Nicholas Kazlauskas Reviewed-by: Duncan Ma Signed-off-by: Rodrigo Siqueira --- drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c index d5dcc8b77281..866b0abcff1b 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c @@ -575,7 +575,7 @@ static bool dml2_validate_and_build_resource(const struct dc *in_dc, struct dc_s unsigned int lowest_state_idx = 0; out_clks.p_state_supported = true; - out_clks.dispclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dispclk_mhz * 1000; + out_clks.dispclk_khz = 0; /* No requirement, and lowest index will generally be maximum dispclk. */ out_clks.dcfclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dcfclk_mhz * 1000; out_clks.fclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].fabricclk_mhz * 1000; out_clks.uclk_mts = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dram_speed_mts; -- 2.43.0
[PATCH 04/39] drm/amd/display: Add two dmmuy I2C entry for GPIO port mapping issue
From: Chris Park
[Why]
When only 4 I2C is declared, two dummies are required to correctly map
GPIO port.
[How]
Add one more I2C dummy entry to match GPIO port.
Signed-off-by: Chris Park
Reviewed-by: Alvin Lee
Signed-off-by: Rodrigo Siqueira
---
.../display/dc/gpio/dcn401/hw_factory_dcn401.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c
b/drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c
index 46415cab23ab..928abca18a18 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c
@@ -86,7 +86,13 @@ static const struct ddc_registers ddc_data_regs_dcn[] = {
ddc_data_regs_dcn2(2),
ddc_data_regs_dcn2(3),
ddc_data_regs_dcn2(4),
-// ddc_data_regs_dcn2(5),
+ {
+ // add a dummy entry for cases no such port
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},
+ .ddc_setup = 0,
+ .phy_aux_cntl = 0,
+ .dc_gpio_aux_ctrl_5 = 0
+ },
{
// add a dummy entry for cases no such port
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},
@@ -107,7 +113,13 @@ static const struct ddc_registers ddc_clk_regs_dcn[] = {
ddc_clk_regs_dcn2(2),
ddc_clk_regs_dcn2(3),
ddc_clk_regs_dcn2(4),
-// ddc_clk_regs_dcn2(5),
+ {
+ // add a dummy entry for cases no such port
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},
+ .ddc_setup = 0,
+ .phy_aux_cntl = 0,
+ .dc_gpio_aux_ctrl_5 = 0
+ },
{
// add a dummy entry for cases no such port
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},
--
2.43.0
[PATCH 06/39] drm/amd/display: Refactor for dio
From: Bhuvanachandra Pinninti
Moved files to respective folders to improve DIO code.
Signed-off-by: Bhuvanachandra Pinninti
Reviewed-by: Martin Leung
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/Makefile| 1 -
drivers/gpu/drm/amd/display/dc/dcn301/Makefile | 2 +-
drivers/gpu/drm/amd/display/dc/dcn314/Makefile | 10 --
drivers/gpu/drm/amd/display/dc/dio/Makefile| 18 ++
.../{ => dio}/dcn301/dcn301_dio_link_encoder.c | 0
.../{ => dio}/dcn301/dcn301_dio_link_encoder.h | 0
.../dcn314/dcn314_dio_stream_encoder.c | 0
.../dcn314/dcn314_dio_stream_encoder.h | 0
.../dc/dio/dcn321/dcn321_dio_link_encoder.c| 1 -
.../dc/dio/dcn35/dcn35_dio_stream_encoder.c| 1 -
10 files changed, 19 insertions(+), 14 deletions(-)
delete mode 100644 drivers/gpu/drm/amd/display/dc/dcn314/Makefile
rename drivers/gpu/drm/amd/display/dc/{ =>
dio}/dcn301/dcn301_dio_link_encoder.c (100%)
rename drivers/gpu/drm/amd/display/dc/{ =>
dio}/dcn301/dcn301_dio_link_encoder.h (100%)
rename drivers/gpu/drm/amd/display/dc/{ =>
dio}/dcn314/dcn314_dio_stream_encoder.c (100%)
rename drivers/gpu/drm/amd/display/dc/{ =>
dio}/dcn314/dcn314_dio_stream_encoder.h (100%)
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile
b/drivers/gpu/drm/amd/display/dc/Makefile
index 80069651def3..8992e697759f 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -35,7 +35,6 @@ DC_LIBS += dcn201
DC_LIBS += dcn30
DC_LIBS += dcn301
DC_LIBS += dcn31
-DC_LIBS += dcn314
DC_LIBS += dml
DC_LIBS += dml2
endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/Makefile
b/drivers/gpu/drm/amd/display/dc/dcn301/Makefile
index dc37dbf870df..fb4814ab3f05 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/Makefile
@@ -3,7 +3,7 @@
#
# Makefile for dcn30.
-DCN301 = dcn301_dio_link_encoder.o dcn301_panel_cntl.o
+DCN301 = dcn301_panel_cntl.o
AMD_DAL_DCN301 = $(addprefix $(AMDDALPATH)/dc/dcn301/,$(DCN301))
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/Makefile
b/drivers/gpu/drm/amd/display/dc/dcn314/Makefile
deleted file mode 100644
index 15fdcf7c6466..
--- a/drivers/gpu/drm/amd/display/dc/dcn314/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: MIT
-# Copyright © 2024 Advanced Micro Devices, Inc. All rights reserved.
-#
-# Makefile for dcn314.
-
-DCN314 = dcn314_dio_stream_encoder.o
-
-AMD_DAL_DCN314 = $(addprefix $(AMDDALPATH)/dc/dcn314/,$(DCN314))
-
-AMD_DISPLAY_FILES += $(AMD_DAL_DCN314)
diff --git a/drivers/gpu/drm/amd/display/dc/dio/Makefile
b/drivers/gpu/drm/amd/display/dc/dio/Makefile
index 67840e474d7a..0dfd480976f7 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dio/Makefile
@@ -51,6 +51,15 @@ AMD_DAL_DIO_DCN30 = $(addprefix
$(AMDDALPATH)/dc/dio/dcn30/,$(DIO_DCN30))
AMD_DISPLAY_FILES += $(AMD_DAL_DIO_DCN30)
+###
+# DCN301
+###
+DIO_DCN301 = dcn301_dio_link_encoder.o
+
+AMD_DAL_DIO_DCN301 = $(addprefix $(AMDDALPATH)/dc/dio/dcn301/,$(DIO_DCN301))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_DIO_DCN301)
+
###
# DCN31
###
@@ -60,6 +69,15 @@ AMD_DAL_DIO_DCN31 = $(addprefix
$(AMDDALPATH)/dc/dio/dcn31/,$(DIO_DCN31))
AMD_DISPLAY_FILES += $(AMD_DAL_DIO_DCN31)
+###
+# DCN314
+###
+DIO_DCN314 = dcn314_dio_stream_encoder.o
+
+AMD_DAL_DIO_DCN314 = $(addprefix $(AMDDALPATH)/dc/dio/dcn314/,$(DIO_DCN314))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_DIO_DCN314)
+
###
# DCN32
###
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dio_link_encoder.c
b/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dio_link_encoder.c
rename to drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dio_link_encoder.h
b/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dio_link_encoder.h
rename to drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c
b/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
similarity inde
[PATCH 07/39] drm/amd/display: Add option to disable unbounded req in DML21
From: Alvin Lee
Use debug option for disabling unbounded req in DML21
Signed-off-by: Alvin Lee
Reviewed-by: Austin Zheng
Signed-off-by: Rodrigo Siqueira
---
.../drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c | 5 +
1 file changed, 5 insertions(+)
diff --git
a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
index 0f34688e4058..65776602648d 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
@@ -959,6 +959,11 @@ bool dml21_map_dc_state_into_dml_display_cfg(const struct
dc *in_dc, struct dc_s
dml_dispcfg->minimize_det_reallocation = true;
dml_dispcfg->overrides.enable_subvp_implicit_pmo = true;
+ if (in_dc->debug.disable_unbounded_requesting) {
+ dml_dispcfg->overrides.hw.force_unbounded_requesting.enable =
true;
+ dml_dispcfg->overrides.hw.force_unbounded_requesting.value =
false;
+ }
+
for (stream_index = 0; stream_index < context->stream_count;
stream_index++) {
disp_cfg_stream_location =
map_stream_to_dml21_display_cfg(dml_ctx, context->streams[stream_index]);
--
2.43.0
[PATCH 08/39] drm/amd/display: Fix possible overflow in integer multiplication
From: Alex Hung [WHAT & HOW] Integer multiplies integer may overflow in context that expects an expression of unsigned long long (64 bits). This can be fixed by casting integer to unsigned long long to force 64 bits results. This fixes 2 OVERFLOW_BEFORE_WIDEN issues reported by Coverity. Signed-off-by: Alex Hung Reviewed-by: Rodrigo Siqueira Signed-off-by: Rodrigo Siqueira --- .../amd/display/dc/resource/dcn32/dcn32_resource_helpers.c| 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c index 47c8a9fbe754..f5a4e97c40ce 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c @@ -663,7 +663,7 @@ bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context) subvp_disallow |= disallow_subvp_in_active_plus_blank(pipe); refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 + - pipe->stream->timing.v_total * pipe->stream->timing.h_total - (uint64_t)1); + pipe->stream->timing.v_total * (unsigned long long)pipe->stream->timing.h_total - (uint64_t)1); refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total); refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total); } @@ -724,7 +724,7 @@ bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int subvp_disallow |= disallow_subvp_in_active_plus_blank(pipe); refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 + - pipe->stream->timing.v_total * pipe->stream->timing.h_total - (uint64_t)1); + pipe->stream->timing.v_total * (unsigned long long)pipe->stream->timing.h_total - (uint64_t)1); refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total); refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total); } -- 2.43.0
[PATCH 09/39] drm/amd/display: Check null pointers before using them
From: Alex Hung
[WHAT & HOW]
dc_link is null checked previously in the same function, indicating it
might be null as reported by Coverity.
This fixes 1 FORWARD_NULL issue reported by Coverity.
Signed-off-by: Alex Hung
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 4d36a66917c6..54e665227e8b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -12083,7 +12083,8 @@ void amdgpu_dm_update_freesync_caps(struct
drm_connector *connector,
}
}
- as_type =
dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link);
+ if (amdgpu_dm_connector->dc_link)
+ as_type =
dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link);
if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
--
2.43.0
[PATCH 11/39] drm/amd/display: restore immediate_disable_crtc for w/a
From: Charlene Liu
[why]
immediate_disable_crtc does not reset ODM. if switching to disable_crtc
which will disable ODM as well. i.e. need to restore ODM mem cfg at
reenable it at end of w/a.
Signed-off-by: Charlene Liu
Reviewed-by: Xi (Alex) Liu
Signed-off-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 4 ++--
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c| 8 ++--
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
index 2d5bd5c7ab94..e075b2720f96 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
@@ -149,8 +149,8 @@ static void dcn35_disable_otg_wa(struct clk_mgr
*clk_mgr_base, struct dc_state *
!pipe->stream->link_enc) && !stream_changed_otg_dig_on)
{
/* This w/a should not trigger when we have a dig
active */
if (disable) {
- if (pipe->stream_res.tg &&
pipe->stream_res.tg->funcs->disable_crtc)
-
pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg);
+ if (pipe->stream_res.tg &&
pipe->stream_res.tg->funcs->immediate_disable_crtc)
+
pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
reset_sync_context_for_pipe(dc, context, i);
} else {
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
index 6bbbf313b2bb..4b6446ed4ce4 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
@@ -149,7 +149,9 @@ static bool optc31_disable_crtc(struct timing_generator
*optc)
return true;
}
-
+/*
+ * Immediate_Disable_Crtc - this is to temp disable Timing generator without
reset ODM.
+ */
bool optc31_immediate_disable_crtc(struct timing_generator *optc)
{
struct optc *optc1 = DCN10TG_FROM_TG(optc);
@@ -162,10 +164,12 @@ bool optc31_immediate_disable_crtc(struct
timing_generator *optc)
VTG0_ENABLE, 0);
/* CRTC disabled, so disable clock. */
- REG_WAIT(OTG_CLOCK_CONTROL,
+ if (optc->ctx->dce_environment != DCE_ENV_DIAG)
+ REG_WAIT(OTG_CLOCK_CONTROL,
OTG_BUSY, 0,
1, 10);
+
/* clear the false state */
optc1_clear_optc_underflow(optc);
--
2.43.0
[PATCH 10/39] drm/amd/display: Check stream_status before it is used
From: Alex Hung
[WHAT & HOW]
dc_state_get_stream_status can return null, and therefore null must be
checked before stream_status is used.
This fixes 1 NULL_RETURNS issue reported by Coverity.
Signed-off-by: Alex Hung
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index b8a6c062426d..ed811352506e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3748,7 +3748,7 @@ static void commit_planes_for_stream_fast(struct dc *dc,
surface_count,
stream,
context);
- } else {
+ } else if (stream_status) {
build_dmub_cmd_list(dc,
srf_updates,
surface_count,
--
2.43.0
[PATCH 13/39] drm/amd/display: Add a missing PSR state
From: Tom Chung
[Why & How]
Add a missing PSR state to make the dmub_psr_get_state() return a
correct PSR state.
Signed-off-by: Tom Chung
Reviewed-by: Sun peng Li
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dc_types.h | 1 +
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h
b/drivers/gpu/drm/amd/display/dc/dc_types.h
index c550e8997033..97279b080f3e 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -590,6 +590,7 @@ enum dc_psr_state {
PSR_STATE5c,
PSR_STATE_HWLOCK_MGR,
PSR_STATE_POLLVUPDATE,
+ PSR_STATE_RELEASE_HWLOCK_MGR_FULL_FRAME,
PSR_STATE_INVALID = 0xFF
};
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index 0f3d15126a1e..cae18f8c1c9a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -94,6 +94,8 @@ static enum dc_psr_state convert_psr_state(uint32_t raw_state)
state = PSR_STATE_HWLOCK_MGR;
else if (raw_state == 0x61)
state = PSR_STATE_POLLVUPDATE;
+ else if (raw_state == 0x62)
+ state = PSR_STATE_RELEASE_HWLOCK_MGR_FULL_FRAME;
else
state = PSR_STATE_INVALID;
--
2.43.0
[PATCH 12/39] drm/amd/display: sync dmub output event type.
From: Charlene Liu
[why]
dmubfw added a new event type, update amdgpu to avoid "notify type 6
invalid"
Signed-off-by: Charlene Liu
Reviewed-by: Chris Park
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 54e665227e8b..f2d5a180f293 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -877,6 +877,7 @@ static void dm_dmub_outbox1_low_irq(void *interrupt_params)
"HPD_IRQ",
"SET_CONFIGC_REPLY",
"DPIA_NOTIFICATION",
+ "HPD_SENSE_NOTIFY",
};
do {
--
2.43.0
[PATCH 14/39] drm/amd/display: Reset VRR config during resume
From: Tom Chung
[Why]
After resume the system, the new_crtc_state->vrr_infopacket does not
synchronize with the current state. It will affect the
update_freesync_state_on_stream() does not update the state correctly.
The previous patch causes a PSR SU regression that cannot let panel go
into self-refresh mode.
[How]
Reset the VRR config during resume to force update the VRR config later.
Fixes: f8ebe6341a6a ("drm/amd/display: Reset freesync config before update new
state")
Signed-off-by: Tom Chung
Reviewed-by: Sun peng Li
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index f2d5a180f293..293f93d1976c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -176,6 +176,7 @@ MODULE_FIRMWARE(FIRMWARE_DCN_401_DMUB);
static int amdgpu_dm_init(struct amdgpu_device *adev);
static void amdgpu_dm_fini(struct amdgpu_device *adev);
static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct
amdgpu_dm_connector *aconnector);
+static void reset_freesync_config_for_crtc(struct dm_crtc_state
*new_crtc_state);
static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
{
@@ -3213,8 +3214,11 @@ static int dm_resume(void *handle)
drm_connector_list_iter_end(&iter);
/* Force mode set in atomic commit */
- for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
+ for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
new_crtc_state->active_changed = true;
+ dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
+ reset_freesync_config_for_crtc(dm_new_crtc_state);
+ }
/*
* atomic_check is expected to create the dc states. We need to release
--
2.43.0
[PATCH 16/39] drm/amd/display: Use correct cm_helper function
From: Ilya Bakoulin
Need to use cm3_helper function with DCN401 to avoid cases where high
RGB component values can get set to zero if using the TF curve generated
by cm_helper.
Signed-off-by: Ilya Bakoulin
Reviewed-by: Alvin Lee
Signed-off-by: Rodrigo Siqueira
---
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 22 +--
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index 0fa610590245..8e1ca709d304 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -497,6 +497,7 @@ void dcn401_populate_mcm_luts(struct dc *dc,
enum MCM_LUT_XABLE lut3d_xable = MCM_LUT_DISABLE;
enum MCM_LUT_XABLE lut1d_xable = MCM_LUT_DISABLE;
bool is_17x17x17 = true;
+ bool rval;
dcn401_get_mcm_lut_xable_from_pipe_ctx(dc, pipe_ctx, &shaper_xable,
&lut3d_xable, &lut1d_xable);
@@ -506,11 +507,10 @@ void dcn401_populate_mcm_luts(struct dc *dc,
if (mcm_luts.lut1d_func->type == TF_TYPE_HWPWL)
m_lut_params.pwl = &mcm_luts.lut1d_func->pwl;
else if (mcm_luts.lut1d_func->type ==
TF_TYPE_DISTRIBUTED_POINTS) {
- cm_helper_translate_curve_to_hw_format(
- dc->ctx,
+ rval = cm3_helper_translate_curve_to_hw_format(
mcm_luts.lut1d_func,
&dpp_base->regamma_params, false);
- m_lut_params.pwl = &dpp_base->regamma_params;
+ m_lut_params.pwl = rval ? &dpp_base->regamma_params :
NULL;
}
if (m_lut_params.pwl) {
if (mpc->funcs->populate_lut)
@@ -527,11 +527,10 @@ void dcn401_populate_mcm_luts(struct dc *dc,
m_lut_params.pwl = &mcm_luts.shaper->pwl;
else if (mcm_luts.shaper->type == TF_TYPE_DISTRIBUTED_POINTS) {
ASSERT(false);
- cm_helper_translate_curve_to_hw_format(
- dc->ctx,
+ rval = cm3_helper_translate_curve_to_hw_format(
mcm_luts.shaper,
&dpp_base->regamma_params, true);
- m_lut_params.pwl = &dpp_base->regamma_params;
+ m_lut_params.pwl = rval ? &dpp_base->regamma_params :
NULL;
}
if (m_lut_params.pwl) {
if (mpc->funcs->populate_lut)
@@ -669,6 +668,7 @@ bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx,
struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
bool result = true;
const struct pwl_params *lut_params = NULL;
+ bool rval;
mpc->funcs->set_movable_cm_location(mpc,
MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id);
pipe_ctx->plane_state->mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE;
@@ -677,10 +677,9 @@ bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx,
if (plane_state->blend_tf.type == TF_TYPE_HWPWL)
lut_params = &plane_state->blend_tf.pwl;
else if (plane_state->blend_tf.type ==
TF_TYPE_DISTRIBUTED_POINTS) {
- cm_helper_translate_curve_to_hw_format(plane_state->ctx,
- &plane_state->blend_tf,
+ rval =
cm3_helper_translate_curve_to_hw_format(&plane_state->blend_tf,
&dpp_base->regamma_params, false);
- lut_params = &dpp_base->regamma_params;
+ lut_params = rval ? &dpp_base->regamma_params : NULL;
}
result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id);
lut_params = NULL;
@@ -693,10 +692,9 @@ bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx,
else if (plane_state->in_shaper_func.type ==
TF_TYPE_DISTRIBUTED_POINTS) {
// TODO: dpp_base replace
ASSERT(false);
- cm_helper_translate_curve_to_hw_format(plane_state->ctx,
- &plane_state->in_shaper_func,
+ rval =
cm3_helper_translate_curve_to_hw_format(&plane_state->in_shaper_func,
&dpp_base->shaper_params, true);
- lut_params = &dpp_base->shaper_params;
+ lut_params = rval ? &dpp_base->shaper_params : NULL;
}
result = mpc->funcs->program_shaper(mpc, lut_params, mpcc_id);
--
2.43.0
[PATCH 15/39] drm/amd/display: Add seamless boot support for more DIG operation modes
From: Nicholas Kazlauskas
[Why]
When pre-OS firmware enables display support for displays that operate
the DIG in 2 pixels per cycle processing modes the inferred pixel rate
from get_pixel_clk_frequency_100hz does not account for the true pixel
rate since we're outputting 2 per cycle past the stream encoder.
This causes seamless boot validation to abort early.
[How]
Add a new stream encoder function for getting pixels per cycle from the
stream encoder. If the pixels per cycle is greater than 1 and the driver
policy is to enable 2 pixels per cycle for post-OS then allow seamless
boot to continue.
Signed-off-by: Nicholas Kazlauskas
Reviewed-by: Duncan Ma
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 12 ++--
.../dc/dio/dcn35/dcn35_dio_stream_encoder.c | 19 +++
.../amd/display/dc/inc/hw/stream_encoder.h| 1 +
3 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index ed811352506e..143415d600ac 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1823,10 +1823,18 @@ bool dc_validate_boot_timing(const struct dc *dc,
tg->funcs->get_optc_source(tg,
&numOdmPipes, &id_src[0],
&id_src[1]);
- if (numOdmPipes == 2)
+ if (numOdmPipes == 2) {
pix_clk_100hz *= 2;
- if (numOdmPipes == 4)
+ } else if (numOdmPipes == 4) {
pix_clk_100hz *= 4;
+ } else if (se && se->funcs->get_pixels_per_cycle) {
+ uint32_t pixels_per_cycle =
se->funcs->get_pixels_per_cycle(se);
+
+ if (pixels_per_cycle != 1 &&
!dc->debug.enable_dp_dig_pixel_rate_div_policy)
+ return false;
+
+ pix_clk_100hz *= pixels_per_cycle;
+ }
// Note: In rare cases, HW pixclk may differ from crtc's pixclk
// slightly due to rounding issues in 10 kHz units.
diff --git
a/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
b/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
index 19e50fbf908d..6ab2a218b769 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
@@ -422,6 +422,24 @@ void enc35_enable_fifo(struct stream_encoder *enc)
REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1);
}
+static uint32_t enc35_get_pixels_per_cycle(struct stream_encoder *enc)
+{
+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+ uint32_t value;
+
+ REG_GET(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, &value);
+
+ switch (value) {
+ case 0:
+ return 1;
+ case 1:
+ return 2;
+ default:
+ ASSERT_CRITICAL(false);
+ return 1;
+ }
+}
+
static const struct stream_encoder_funcs dcn35_str_enc_funcs = {
.dp_set_odm_combine =
enc314_dp_set_odm_combine,
@@ -474,6 +492,7 @@ static const struct stream_encoder_funcs
dcn35_str_enc_funcs = {
.disable_fifo = enc35_disable_fifo,
.is_fifo_enabled = enc35_is_fifo_enabled,
.map_stream_to_link = enc35_stream_encoder_map_to_link,
+ .get_pixels_per_cycle = enc35_get_pixels_per_cycle,
};
void dcn35_dio_stream_encoder_construct(
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
index 6fe42120738d..fe7f3137f228 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
@@ -273,6 +273,7 @@ struct stream_encoder_funcs {
void (*disable_fifo)(struct stream_encoder *enc);
bool (*is_fifo_enabled)(struct stream_encoder *enc);
void (*map_stream_to_link)(struct stream_encoder *enc, uint32_t
stream_enc_inst, uint32_t link_enc_inst);
+ uint32_t (*get_pixels_per_cycle)(struct stream_encoder *enc);
};
struct hpo_dp_stream_encoder_state {
--
2.43.0
[PATCH 17/39] drm/amd/display: Avoid overflow assignment in link_dp_cts
From: Alex Hung
sampling_rate is an uint8_t but is assigned an unsigned int, and thus it
can overflow. As a result, sampling_rate is changed to uint32_t.
Similarly, LINK_QUAL_PATTERN_SET has a size of 2 bits, and it should
only be assigned to a value less or equal than 4.
This fixes 2 INTEGER_OVERFLOW issues reported by Coverity.
Signed-off-by: Alex Hung
Reviewed-by: Wenjing Liu
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 2 +-
drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c | 3 ++-
drivers/gpu/drm/amd/display/include/dpcd_defs.h | 1 +
3 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
index 519c3df78ee5..95c275bf649b 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
@@ -727,7 +727,7 @@ struct dp_audio_test_data_flags {
struct dp_audio_test_data {
struct dp_audio_test_data_flags flags;
- uint8_t sampling_rate;
+ uint32_t sampling_rate;
uint8_t channel_count;
uint8_t pattern_type;
uint8_t pattern_period[8];
diff --git a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
index df3781081da7..32d5a4b14333 100644
--- a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
+++ b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
@@ -775,7 +775,8 @@ bool dp_set_test_pattern(
core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET,
&training_pattern.raw,
sizeof(training_pattern));
- training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
+ if (pattern <= PHY_TEST_PATTERN_END_DP11)
+ training_pattern.v1_3.LINK_QUAL_PATTERN_SET =
pattern;
core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET,
&training_pattern.raw,
sizeof(training_pattern));
diff --git a/drivers/gpu/drm/amd/display/include/dpcd_defs.h
b/drivers/gpu/drm/amd/display/include/dpcd_defs.h
index aee5170f5fb2..c246235e4afe 100644
--- a/drivers/gpu/drm/amd/display/include/dpcd_defs.h
+++ b/drivers/gpu/drm/amd/display/include/dpcd_defs.h
@@ -76,6 +76,7 @@ enum dpcd_phy_test_patterns {
PHY_TEST_PATTERN_D10_2,
PHY_TEST_PATTERN_SYMBOL_ERROR,
PHY_TEST_PATTERN_PRBS7,
+ PHY_TEST_PATTERN_END_DP11 = PHY_TEST_PATTERN_PRBS7,
PHY_TEST_PATTERN_80BIT_CUSTOM,/* For DP1.2 only */
PHY_TEST_PATTERN_CP2520_1,
PHY_TEST_PATTERN_CP2520_2,
--
2.43.0
[PATCH 19/39] drm/amd/display: Add logs for debugging outbox
From: Cruise
The DP tunnel AUX reply is received through Outbox1. Print the Outbox1
status if an issue occurs.
Signed-off-by: Cruise
Reviewed-by: Nicholas Kazlauskas
Reviewed-by: Wayne Lin
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 3 +++
drivers/gpu/drm/amd/display/dmub/dmub_srv.h| 3 +++
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c | 4
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c | 4
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c | 4
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c | 4
6 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index fb3391854eed..41270fade5f2 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -979,6 +979,9 @@ void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv
*dc_dmub_srv)
DC_LOG_DEBUG("inbox0_rptr: %08x", diag_data.inbox0_rptr);
DC_LOG_DEBUG("inbox0_wptr: %08x", diag_data.inbox0_wptr);
DC_LOG_DEBUG("inbox0_size: %08x", diag_data.inbox0_size);
+ DC_LOG_DEBUG("outbox1_rptr : %08x", diag_data.outbox1_rptr);
+ DC_LOG_DEBUG("outbox1_wptr : %08x", diag_data.outbox1_wptr);
+ DC_LOG_DEBUG("outbox1_size : %08x", diag_data.outbox1_size);
DC_LOG_DEBUG("is_enabled : %d", diag_data.is_dmcub_enabled);
DC_LOG_DEBUG("is_soft_reset : %d",
diag_data.is_dmcub_soft_reset);
DC_LOG_DEBUG("is_secure_reset: %d",
diag_data.is_dmcub_secure_reset);
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index 6589bb9aea6b..cd70453aeae0 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -330,6 +330,9 @@ struct dmub_diagnostic_data {
uint32_t inbox0_rptr;
uint32_t inbox0_wptr;
uint32_t inbox0_size;
+ uint32_t outbox1_rptr;
+ uint32_t outbox1_wptr;
+ uint32_t outbox1_size;
uint32_t gpint_datain0;
struct dmub_srv_debug timeout_info;
uint8_t is_dmcub_enabled : 1;
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
index 662c34e9495c..d9f31b191c69 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
@@ -449,6 +449,10 @@ void dmub_dcn31_get_diagnostic_data(struct dmub_srv *dmub,
struct dmub_diagnosti
diag_data->inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);
diag_data->inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);
+ diag_data->outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR);
+ diag_data->outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR);
+ diag_data->outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE);
+
REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
diag_data->is_dmcub_enabled = is_dmub_enabled;
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
index e1da270502cc..9600b7f858b0 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
@@ -459,6 +459,10 @@ void dmub_dcn32_get_diagnostic_data(struct dmub_srv *dmub,
struct dmub_diagnosti
diag_data->inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);
diag_data->inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);
+ diag_data->outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR);
+ diag_data->outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR);
+ diag_data->outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE);
+
REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
diag_data->is_dmcub_enabled = is_dmub_enabled;
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
index 916ed022e96b..746696b6f09a 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
@@ -502,6 +502,10 @@ void dmub_dcn35_get_diagnostic_data(struct dmub_srv *dmub,
struct dmub_diagnosti
diag_data->inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);
diag_data->inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);
+ diag_data->outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR);
+ diag_data->outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR);
+ diag_data->outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE);
+
REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
diag_data->is_dmcub_enabled = is_dmub_enabled;
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
index c
[PATCH 18/39] drm/amd/display: Add new enable and disable functions
From: Hansen Dsouza
Add new enable and disable functions based on DCCG spec.
Signed-off-by: Hansen Dsouza
Reviewed-by: Muhammad Ahmed
Signed-off-by: Rodrigo Siqueira
---
.../amd/display/dc/dccg/dcn35/dcn35_dccg.c| 212 ++
1 file changed, 212 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
index b698b773338a..7d88b0ae241c 100644
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
@@ -732,6 +732,206 @@ static void dccg35_set_symclk_fe_src_new(struct dccg
*dccg, enum physymclk_fe_so
}
}
+static uint32_t dccg35_is_fe_rcg(struct dccg *dccg, int inst)
+{
+ uint32_t enable = 0;
+ struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+ switch (inst) {
+ case 0:
+ REG_GET(DCCG_GATE_DISABLE_CNTL5,
+ SYMCLKA_FE_ROOT_GATE_DISABLE, &enable);
+ break;
+ case 1:
+ REG_GET(DCCG_GATE_DISABLE_CNTL5,
+ SYMCLKB_FE_ROOT_GATE_DISABLE, &enable);
+ break;
+ case 2:
+ REG_GET(DCCG_GATE_DISABLE_CNTL5,
+ SYMCLKC_FE_ROOT_GATE_DISABLE, &enable);
+ break;
+ case 3:
+ REG_GET(DCCG_GATE_DISABLE_CNTL5,
+ SYMCLKD_FE_ROOT_GATE_DISABLE, &enable);
+ break;
+ case 4:
+ REG_GET(DCCG_GATE_DISABLE_CNTL5,
+ SYMCLKE_FE_ROOT_GATE_DISABLE, &enable);
+ break;
+ default:
+ BREAK_TO_DEBUGGER();
+ break;
+ }
+ return enable;
+}
+
+static uint32_t dccg35_is_symclk32_se_rcg(struct dccg *dccg, int inst)
+{
+ uint32_t disable_l1 = 0;
+ uint32_t disable_l2 = 0;
+ struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+ switch (inst) {
+ case 0:
+ REG_GET_2(DCCG_GATE_DISABLE_CNTL3,
+ SYMCLK32_SE0_GATE_DISABLE, &disable_l1,
+ SYMCLK32_ROOT_SE0_GATE_DISABLE, &disable_l2);
+ break;
+ case 1:
+ REG_GET_2(DCCG_GATE_DISABLE_CNTL3,
+ SYMCLK32_SE1_GATE_DISABLE, &disable_l1,
+ SYMCLK32_ROOT_SE1_GATE_DISABLE, &disable_l2);
+ break;
+ case 2:
+ REG_GET_2(DCCG_GATE_DISABLE_CNTL3,
+ SYMCLK32_SE2_GATE_DISABLE, &disable_l1,
+ SYMCLK32_ROOT_SE2_GATE_DISABLE, &disable_l2);
+ break;
+ case 3:
+ REG_GET_2(DCCG_GATE_DISABLE_CNTL3,
+ SYMCLK32_SE3_GATE_DISABLE, &disable_l1,
+ SYMCLK32_ROOT_SE3_GATE_DISABLE, &disable_l2);
+ break;
+ default:
+ BREAK_TO_DEBUGGER();
+ return 0;
+ }
+
+ /* return true if either block level or DCCG level gating is active */
+ return (disable_l1 | disable_l2);
+}
+
+static void dccg35_enable_symclk_fe_new(
+ struct dccg *dccg,
+ int inst,
+ enum physymclk_fe_source src)
+{
+ dccg35_set_physymclk_fe_rcg(dccg, inst, false);
+ dccg35_set_symclk_fe_src_new(dccg, src, inst);
+}
+
+static void dccg35_disable_symclk_fe_new(
+ struct dccg *dccg,
+ int inst)
+{
+ dccg35_set_symclk_fe_src_new(dccg, PHYSYMCLK_FE_REFCLK, inst);
+ dccg35_set_physymclk_fe_rcg(dccg, inst, true);
+}
+
+static void dccg35_enable_symclk_be_new(
+ struct dccg *dccg,
+ int inst,
+ enum physymclk_source src)
+{
+ dccg35_set_physymclk_rcg(dccg, inst, false);
+ dccg35_set_physymclk_src_new(dccg, inst, src);
+}
+
+static void dccg35_disable_symclk_be_new(
+ struct dccg *dccg,
+ int inst)
+{
+ int i;
+
+ /* Switch from functional clock to refclock */
+ dccg35_set_physymclk_src_new(dccg, inst, PHYSYMCLK_REFCLK);
+
+ /* Check if any other SE connected LE and disable them */
+ for (i = 0; i < 4; i++) {
+ /* Make sure FE is not already in RCG */
+ if (dccg35_is_fe_rcg(dccg, i) == 0) {
+ if (dccg35_is_symclk_fe_src_functional_be(dccg, i,
inst))
+ dccg35_disable_symclk_fe_new(dccg, i);
+ }
+ }
+ /* Safe to RCG SYMCLK*/
+ dccg35_set_physymclk_rcg(dccg, inst, true);
+}
+
+static void dccg35_enable_symclk32_se_new(
+ struct dccg *dccg,
+ int inst,
+ enum symclk32_se_clk_source src)
+{
+ dccg35_set_symclk32_se_rcg(dccg, inst, false);
+ dccg35_set_symclk32_se_src_new(dccg, inst, src);
+}
+
+static void dccg35_disable_symclk32_se_new(
+ struct dccg *dccg,
+
[PATCH 20/39] drm/amd/display: Check null values from functions
From: Alex Hung
Functions get_per_method_common_meta and get_expanded_strategy_list can
return null and thus it is necessary to check their returned values
before dereferencing.
This fixes 3 NULL_RETURNS issues reported by Coverity.
Signed-off-by: Alex Hung
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
---
.../dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c | 8
1 file changed, 8 insertions(+)
diff --git
a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
index dddb21818f8a..9331a8fe77c9 100644
---
a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
+++
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
@@ -1199,12 +1199,17 @@ static bool is_timing_group_schedulable(
/* init allow start and end lines for timing group */
stream_method_fams2_meta = get_per_method_common_meta(pmo,
pstate_strategy->per_stream_pstate_method[base_stream_idx], base_stream_idx);
+ if (!stream_method_fams2_meta)
+ return false;
+
group_fams2_meta->allow_start_otg_vline =
stream_method_fams2_meta->allow_start_otg_vline;
group_fams2_meta->allow_end_otg_vline =
stream_method_fams2_meta->allow_end_otg_vline;
group_fams2_meta->period_us = stream_method_fams2_meta->period_us;
for (i = base_stream_idx + 1; i <
display_cfg->display_config.num_streams; i++) {
if
(is_bit_set_in_bitfield(pmo->scratch.pmo_dcn4.synchronized_timing_group_masks[timing_group_idx],
i)) {
stream_method_fams2_meta =
get_per_method_common_meta(pmo, pstate_strategy->per_stream_pstate_method[i],
i);
+ if (!stream_method_fams2_meta)
+ return false;
if (group_fams2_meta->allow_start_otg_vline <
stream_method_fams2_meta->allow_start_otg_vline) {
/* set group allow start to larger otg vline */
@@ -1768,6 +1773,9 @@ bool pmo_dcn4_fams2_init_for_pstate_support(struct
dml2_pmo_init_for_pstate_supp
build_synchronized_timing_groups(pmo, display_config);
strategy_list = get_expanded_strategy_list(&pmo->init_data,
display_config->display_config.num_streams);
+ if (!strategy_list)
+ return false;
+
strategy_list_size = get_num_expanded_strategies(&pmo->init_data,
display_config->display_config.num_streams);
if (strategy_list_size == 0)
--
2.43.0
[PATCH 25/39] drm/amd/display: Underflow Seen on DCN401 eGPU
From: Daniel Sa
[WHY]
In dcn401 we read clock values before FW is loaded. These incorrect
values cause the driver to believe that we are running higher clocks
than what we actually have. This then causes corruption/underflow for
the eGPU.
[HOW]
When new values are read from HW, update internal structures to
propagate the new/correct value. Fixes issue
Signed-off-by: Daniel Sa
Reviewed-by: Alvin Lee
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index 8e1ca709d304..ceaaa8df3641 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -221,6 +221,7 @@ void dcn401_init_hw(struct dc *dc)
int edp_num;
uint32_t backlight = MAX_BACKLIGHT_LEVEL;
uint32_t user_level = MAX_BACKLIGHT_LEVEL;
+ int current_dchub_ref_freq = 0;
if (dc->clk_mgr && dc->clk_mgr->funcs &&
dc->clk_mgr->funcs->init_clocks) {
dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
@@ -264,6 +265,8 @@ void dcn401_init_hw(struct dc *dc)
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
&res_pool->ref_clocks.dccg_ref_clock_inKhz);
+ current_dchub_ref_freq =
res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;
+
(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
res_pool->ref_clocks.dccg_ref_clock_inKhz,
&res_pool->ref_clocks.dchub_ref_clock_inKhz);
@@ -433,8 +436,9 @@ void dcn401_init_hw(struct dc *dc)
dc->caps.dmub_caps.mclk_sw =
dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver > 0;
dc->caps.dmub_caps.fams_ver =
dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;
dc->debug.fams2_config.bits.enable &=
dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver == 2;
- if (!dc->debug.fams2_config.bits.enable &&
dc->res_pool->funcs->update_bw_bounding_box) {
- /* update bounding box if FAMS2 disabled */
+ if ((!dc->debug.fams2_config.bits.enable &&
dc->res_pool->funcs->update_bw_bounding_box)
+ || res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000 !=
current_dchub_ref_freq) {
+ /* update bounding box if FAMS2 disabled, or if dchub
clk has changed */
if (dc->clk_mgr)
dc->res_pool->funcs->update_bw_bounding_box(dc,
dc->clk_mgr->bw_params);
--
2.43.0
[PATCH 22/39] drm/amd/display: Use gpuvm_min_page_size_kbytes for DML2 surfaces
From: Nicholas Kazlauskas
[Why]
It's currently hard coded to 256 when it should be using the SOC
provided values. This can result in corruption with linear surfaces
where we prefetch more PTE than the buffer can hold.
[How]
Update the min page size correctly for the plane.
Signed-off-by: Nicholas Kazlauskas
Reviewed-by: Jun Lei
Signed-off-by: Rodrigo Siqueira
---
.../display/dc/dml2/dml2_translation_helper.c | 20 +--
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
index 25d4ef040173..7e39873832bf 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
@@ -954,7 +954,9 @@ static void get_scaler_data_for_plane(const struct
dc_plane_state *in, struct dc
memcpy(out, &temp_pipe->plane_res.scl_data, sizeof(*out));
}
-static void populate_dummy_dml_plane_cfg(struct dml_plane_cfg_st *out,
unsigned int location, const struct dc_stream_state *in)
+static void populate_dummy_dml_plane_cfg(struct dml_plane_cfg_st *out,
unsigned int location,
+const struct dc_stream_state *in,
+const struct soc_bounding_box_st *soc)
{
dml_uint_t width, height;
@@ -971,7 +973,7 @@ static void populate_dummy_dml_plane_cfg(struct
dml_plane_cfg_st *out, unsigned
out->CursorBPP[location] = dml_cur_32bit;
out->CursorWidth[location] = 256;
- out->GPUVMMinPageSizeKBytes[location] = 256;
+ out->GPUVMMinPageSizeKBytes[location] = soc->gpuvm_min_page_size_kbytes;
out->ViewportWidth[location] = width;
out->ViewportHeight[location] = height;
@@ -1008,7 +1010,9 @@ static void populate_dummy_dml_plane_cfg(struct
dml_plane_cfg_st *out, unsigned
out->ScalerEnabled[location] = false;
}
-static void populate_dml_plane_cfg_from_plane_state(struct dml_plane_cfg_st
*out, unsigned int location, const struct dc_plane_state *in, struct dc_state
*context)
+static void populate_dml_plane_cfg_from_plane_state(struct dml_plane_cfg_st
*out, unsigned int location,
+ const struct dc_plane_state
*in, struct dc_state *context,
+ const struct
soc_bounding_box_st *soc)
{
struct scaler_data *scaler_data = kzalloc(sizeof(*scaler_data),
GFP_KERNEL);
if (!scaler_data)
@@ -1019,7 +1023,7 @@ static void
populate_dml_plane_cfg_from_plane_state(struct dml_plane_cfg_st *out
out->CursorBPP[location] = dml_cur_32bit;
out->CursorWidth[location] = 256;
- out->GPUVMMinPageSizeKBytes[location] = 256;
+ out->GPUVMMinPageSizeKBytes[location] = soc->gpuvm_min_page_size_kbytes;
out->ViewportWidth[location] = scaler_data->viewport.width;
out->ViewportHeight[location] = scaler_data->viewport.height;
@@ -1332,7 +1336,8 @@ void map_dc_state_into_dml_display_cfg(struct
dml2_context *dml2, struct dc_stat
disp_cfg_plane_location = dml_dispcfg->num_surfaces++;
populate_dummy_dml_surface_cfg(&dml_dispcfg->surface,
disp_cfg_plane_location, context->streams[i]);
- populate_dummy_dml_plane_cfg(&dml_dispcfg->plane,
disp_cfg_plane_location, context->streams[i]);
+ populate_dummy_dml_plane_cfg(&dml_dispcfg->plane,
disp_cfg_plane_location,
+context->streams[i],
&dml2->v20.dml_core_ctx.soc);
dml_dispcfg->plane.BlendingAndTiming[disp_cfg_plane_location] =
disp_cfg_stream_location;
@@ -1348,7 +1353,10 @@ void map_dc_state_into_dml_display_cfg(struct
dml2_context *dml2, struct dc_stat
ASSERT(disp_cfg_plane_location >= 0 &&
disp_cfg_plane_location <= __DML2_WRAPPER_MAX_STREAMS_PLANES__);
populate_dml_surface_cfg_from_plane_state(dml2->v20.dml_core_ctx.project,
&dml_dispcfg->surface, disp_cfg_plane_location,
context->stream_status[i].plane_states[j]);
-
populate_dml_plane_cfg_from_plane_state(&dml_dispcfg->plane,
disp_cfg_plane_location, context->stream_status[i].plane_states[j], context);
+ populate_dml_plane_cfg_from_plane_state(
+ &dml_dispcfg->plane,
disp_cfg_plane_location,
+
context->stream_status[i].plane_states[j], context,
+ &dml2->v20.dml_core_ctx.soc);
if (stream_mall_type == SUBVP_MAIN) {
dml_dispcfg->plane.UseMALLForPStateChange[disp_cfg_plane_location] =
dml_use_mall_pstate_change_sub_viewport;
--
2.43.0
[PATCH 24/39] drm/amd/display: Enable aux transfer path via dmub for dp tunneling
From: Meenakshikumar Somasundaram
[Why]
Aux transfer retries path does not support dp tunneling.
[How]
Based on ddc pin check, aux will be issued in legacy path or dmub.
Signed-off-by: Meenakshikumar Somasundaram
Reviewed-by: Eric Yang
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
index b8996d285f00..bb4ac5042c80 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
@@ -735,7 +735,15 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
(unsigned int) payload->mot);
if (payload->write)
dce_aux_log_payload(" write", payload->data,
payload->length, 16);
- ret = dce_aux_transfer_raw(ddc, payload, &operation_result);
+
+ /* Check whether aux to be processed via dmub or dcn directly */
+ if (ddc->ctx->dc->debug.enable_dmub_aux_for_legacy_ddc
+ || ddc->ddc_pin == NULL) {
+ ret = dce_aux_transfer_dmub_raw(ddc, payload,
&operation_result);
+ } else {
+ ret = dce_aux_transfer_raw(ddc, payload,
&operation_result);
+ }
+
DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
LOG_FLAG_I2cAux_DceAux,
"dce_aux_transfer_with_retries:
link_index=%u: END: retry %d of %d: address=0x%04x length=%u write=%d mot=%d:
ret=%d operation_result=%d payload->reply=%u",
--
2.43.0
[PATCH 29/39] drm/amd/display: Setup two pixel per container
SPL has a control field for controlling the two pixels per container that is not in use yet. This commit adds a proper initialization for this feature. Reviewed-by: Aurabindo Pillai Signed-off-by: Rodrigo Siqueira --- drivers/gpu/drm/amd/display/dc/dc_spl_translate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c index bcc596724a4f..8f85a1db5eba 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c +++ b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c @@ -128,6 +128,7 @@ void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl spl_in->basic_out.always_scale = pipe_ctx->stream->ctx->dc->debug.always_scale; // Make spl input basic output info alpha_en field point to plane res scl_data lb_params alpha_en spl_in->basic_out.alpha_en = pipe_ctx->plane_res.scl_data.lb_params.alpha_en; + spl_in->basic_out.use_two_pixels_per_container = pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing); // Make spl input basic input info scaling quality field point to plane state scaling_quality populate_spltaps_from_taps(&spl_in->scaling_quality, &plane_state->scaling_quality); // Translate edge adaptive scaler preference -- 2.43.0
[PATCH 27/39] drm/amd/display: Get link index for AUX reply notification
From: Cruise
The link index wasn't updated for the AUX reply notification. Get link
index based on DPIA instance for AUX reply notification.
Signed-off-by: Cruise
Reviewed-by: Meenakshikumar Somasundaram
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc_stat.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stat.c
b/drivers/gpu/drm/amd/display/dc/core/dc_stat.c
index cd6570a1e20e..fe9f99f1bdf9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stat.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stat.c
@@ -61,6 +61,7 @@ void dc_stat_get_dmub_notification(const struct dc *dc,
struct dmub_notification
/* For HPD/HPD RX, convert dpia port index into link index */
if (notify->type == DMUB_NOTIFICATION_HPD ||
notify->type == DMUB_NOTIFICATION_HPD_IRQ ||
+ notify->type == DMUB_NOTIFICATION_AUX_REPLY ||
notify->type == DMUB_NOTIFICATION_DPIA_NOTIFICATION ||
notify->type == DMUB_NOTIFICATION_SET_CONFIG_REPLY) {
notify->link_index =
--
2.43.0
[PATCH 21/39] drm/amd/display: Initialize get_bytes_per_element's default to 1
From: Alex Hung
Variables, used as denominators and maybe not assigned to other values,
should not be 0. bytes_per_element_y & bytes_per_element_c are
initialized by get_bytes_per_element() which should never return 0.
This fixes 10 DIVIDE_BY_ZERO issues reported by Coverity.
Signed-off-by: Alex Hung
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c | 2 +-
.../gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git
a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
index 3d95bfa5aca2..ae5251041728 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
@@ -78,7 +78,7 @@ static void calculate_ttu_cursor(struct display_mode_lib
*mode_lib,
static unsigned int get_bytes_per_element(enum source_format_class
source_format, bool is_chroma)
{
- unsigned int ret_val = 0;
+ unsigned int ret_val = 1;
if (source_format == dm_444_16) {
if (!is_chroma)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
index 98502a4f0567..9e1c18b90805 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
@@ -53,7 +53,7 @@ static void calculate_ttu_cursor(
static unsigned int get_bytes_per_element(enum source_format_class
source_format, bool is_chroma)
{
- unsigned int ret_val = 0;
+ unsigned int ret_val = 1;
if (source_format == dm_444_16) {
if (!is_chroma)
--
2.43.0
[PATCH 28/39] drm/amd/display: Re-order enum in a header file
Move the lb_memory_config close to the pixel format enums to improve the
code readability.
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/dc/spl/dc_spl_types.h | 32 +--
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h
b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h
index caaa9ced2ec4..36d10b0f2eed 100644
--- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h
+++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h
@@ -10,22 +10,6 @@
#ifndef __DC_SPL_TYPES_H__
#define __DC_SPL_TYPES_H__
-enum lb_memory_config {
- /* Enable all 3 pieces of memory */
- LB_MEMORY_CONFIG_0 = 0,
-
- /* Enable only the first piece of memory */
- LB_MEMORY_CONFIG_1 = 1,
-
- /* Enable only the second piece of memory */
- LB_MEMORY_CONFIG_2 = 2,
-
- /* Only applicable in 4:2:0 mode, enable all 3 pieces of memory and the
-* last piece of chroma memory used for the luma storage
-*/
- LB_MEMORY_CONFIG_3 = 3
-};
-
struct spl_size {
uint32_t width;
uint32_t height;
@@ -87,6 +71,22 @@ enum spl_pixel_format {
SPL_PIXEL_FORMAT_UNKNOWN
};
+enum lb_memory_config {
+ /* Enable all 3 pieces of memory */
+ LB_MEMORY_CONFIG_0 = 0,
+
+ /* Enable only the first piece of memory */
+ LB_MEMORY_CONFIG_1 = 1,
+
+ /* Enable only the second piece of memory */
+ LB_MEMORY_CONFIG_2 = 2,
+
+ /* Only applicable in 4:2:0 mode, enable all 3 pieces of memory and the
+* last piece of chroma memory used for the luma storage
+*/
+ LB_MEMORY_CONFIG_3 = 3
+};
+
/* Rotation angle */
enum spl_rotation_angle {
SPL_ROTATION_ANGLE_0 = 0,
--
2.43.0
[PATCH 23/39] drm/amd/display: Add new enable and disable functions for DCN35
From: Hansen Dsouza
Add new enable and disable functions based on DCCG spec.
Signed-off-by: Hansen Dsouza
Reviewed-by: Muhammad Ahmed
Signed-off-by: Rodrigo Siqueira
---
.../amd/display/dc/dccg/dcn35/dcn35_dccg.c| 54 ++-
1 file changed, 53 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
index 7d88b0ae241c..bd3757de51c9 100644
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
@@ -932,6 +932,53 @@ static void dccg35_disable_dpp_new(
dccg35_set_dppclk_rcg(dccg, inst, true);
}
+static void dccg35_disable_dscclk_new(struct dccg *dccg,
+ int
inst)
+{
+ dccg35_set_dsc_clk_src_new(dccg, inst, DSC_CLK_REF_CLK);
+ dccg35_set_dsc_clk_rcg(dccg, inst, true);
+}
+
+static void dccg35_enable_dscclk_new(struct dccg *dccg,
+int
inst,
+enum
dsc_clk_source src)
+{
+ dccg35_set_dsc_clk_rcg(dccg, inst, false);
+ dccg35_set_dsc_clk_src_new(dccg, inst, src);
+}
+
+static void dccg35_enable_dtbclk_p_new(struct dccg *dccg,
+ enum
dtbclk_source src,
+ int
inst)
+{
+ dccg35_set_dtbclk_p_rcg(dccg, inst, false);
+ dccg35_set_dtbclk_p_src_new(dccg, src, inst);
+}
+
+static void dccg35_disable_dtbclk_p_new(struct dccg *dccg,
+
enum dtbclk_source src,
+
int inst)
+{
+ dccg35_set_dtbclk_p_src_new(dccg, DTBCLK_REFCLK, inst);
+ dccg35_set_dtbclk_p_rcg(dccg, inst, true);
+}
+
+static void dccg35_enable_dpstreamclk_new(struct dccg *dccg,
+
enum dtbclk_source src,
+
int inst)
+{
+ dccg35_set_dpstreamclk_src_new(dccg, DP_STREAM_REFCLK, inst);
+ dccg35_set_dpstreamclk_rcg(dccg, inst, true);
+}
+
+static void dccg35_disable_dpstreamclk_new(struct dccg *dccg,
+
enum dtbclk_source src,
+
int inst)
+{
+ dccg35_set_dpstreamclk_rcg(dccg, inst, false);
+ dccg35_set_dtbclk_p_src_new(dccg, src, inst);
+}
+
static void dccg35_trigger_dio_fifo_resync(struct dccg *dccg)
{
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
@@ -1965,7 +2012,12 @@ struct dccg *dccg35_create(
(void)&dccg35_disable_symclk32_le_new;
(void)&dccg35_enable_dpp_new;
(void)&dccg35_disable_dpp_new;
-
+ (void)&dccg35_disable_dscclk_new;
+ (void)&dccg35_enable_dscclk_new;
+ (void)&dccg35_enable_dtbclk_p_new;
+ (void)&dccg35_disable_dtbclk_p_new;
+ (void)&dccg35_enable_dpstreamclk_new;
+ (void)&dccg35_disable_dpstreamclk_new;
base = &dccg_dcn->base;
base->ctx = ctx;
base->funcs = &dccg35_funcs;
--
2.43.0
[PATCH 30/39] drm/amd/display: Replace dm_execute_dmub_cmd with dc_wake_and_execute_dmub_cmd
In the commit c2cec7a872b6 ("drm/amd/display: Wake DMCUB before sending
a command for replay feature"), replaced dm_execute_dmub_cmd with
dc_wake_and_execute_dmub_cmd in multiple areas, but due to merge issues
the replacement of this function in the dmub_replay_copy_settings was
missed. This commit replaces the old dm_execute_dmub_cmd with
dc_wake_and_execute_dmub_cmd.
Fixes: c2cec7a872b6 ("drm/amd/display: Wake DMCUB before sending a command for
replay feature")
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
index 44df9e2351c2..14f935961672 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
@@ -187,8 +187,7 @@ static bool dmub_replay_copy_settings(struct dmub_replay
*dmub,
else
copy_settings_data->flags.bitfields.force_wakeup_by_tps3 = 0;
-
- dm_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
+ dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
return true;
}
--
2.43.0
[PATCH 26/39] drm/amd/display: Check UnboundedRequestEnabled's value
From: Alex Hung
CalculateSwathAndDETConfiguration_params_st's UnboundedRequestEnabled is
a pointer (i.e. dml_bool_t *UnboundedRequestEnabled), and thus
p->UnboundedRequestEnabled checks its address, not bool value.
To check value, *p->UnboundedRequestEnabled is used instead.
This fixes 1 REVERSE_INULL issue reported by Coverity.
Signed-off-by: Alex Hung
Reviewed-by: Rodrigo Siqueira
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
.../display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
index 5ba38d51382f..df0911aa251d 100644
---
a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
+++
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
@@ -3851,7 +3851,7 @@ static void CalculateSwathAndDETConfiguration(struct
dml2_core_internal_scratch
*p->hw_debug5 = false;
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
- if (!(p->mrq_present) && (!p->UnboundedRequestEnabled) &&
(TotalActiveDPP == 1)
+ if (!(p->mrq_present) && (!(*p->UnboundedRequestEnabled)) &&
(TotalActiveDPP == 1)
&&
p->display_cfg->plane_descriptors[k].surface.dcc.enable
&& ((p->rob_buffer_size_kbytes * 1024 * (p->mrq_present
? MAXIMUMCOMPRESSION : 1)
+ *p->CompressedBufferSizeInkByte *
MAXIMUMCOMPRESSION * 1024) > TTUFIFODEPTH * (RoundedUpSwathSizeBytesY[k] +
RoundedUpSwathSizeBytesC[k])))
--
2.43.0
[PATCH 31/39] drm/amd/display: Fix Cursor Offset in Scaled Scenarios
From: Sung Lee [WHY] Cursor position code had improper offsets in scaled modes. [HOW] Adjust cursor scaling to account for cursor offsets properly. Reviewed-by: Rodrigo Siqueira Signed-off-by: Sung Lee Signed-off-by: Rodrigo Siqueira --- drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c index eb0da6c6b87c..846c183fe3a8 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c @@ -725,8 +725,8 @@ void hubp401_cursor_set_position( CURSOR_ENABLE, cur_en); REG_SET_2(CURSOR_POSITION, 0, - CURSOR_X_POSITION, pos->x, - CURSOR_Y_POSITION, pos->y); + CURSOR_X_POSITION, x_pos, + CURSOR_Y_POSITION, y_pos); REG_SET_2(CURSOR_HOT_SPOT, 0, CURSOR_HOT_SPOT_X, pos->x_hotspot, -- 2.43.0
[PATCH 32/39] drm/amd/display: For FAMS2 don't program P-State force from driver
From: Alvin Lee
P-State force programming is handled entirely by FW in FAMS2. Remove
any programming from driver side to prevent incorrect programming from
driver side (which may override FW programming)
Signed-off-by: Alvin Lee
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c | 1 -
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c | 1 -
2 files changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
index 846c183fe3a8..b1ebf5053b4f 100644
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
@@ -990,7 +990,6 @@ static struct hubp_funcs dcn401_hubp_funcs = {
.hubp_soft_reset = hubp31_soft_reset,
.hubp_set_flip_int = hubp401_set_flip_int,
.hubp_in_blank = hubp401_in_blank,
- .hubp_update_force_pstate_disallow =
hubp32_update_force_pstate_disallow,
.phantom_hubp_post_enable = hubp32_phantom_hubp_post_enable,
.hubp_update_mall_sel = hubp401_update_mall_sel,
.hubp_prepare_subvp_buffering = hubp32_prepare_subvp_buffering,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
index 2533f16510ba..457f4167e848 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
@@ -132,7 +132,6 @@ static const struct hwseq_private_funcs
dcn401_private_funcs = {
.dccg_init = dcn20_dccg_init,
.set_mcm_luts = dcn401_set_mcm_luts,
.program_mall_pipe_config = dcn32_program_mall_pipe_config,
- .update_force_pstate = dcn32_update_force_pstate,
.update_mall_sel = dcn32_update_mall_sel,
.calculate_dccg_k1_k2_values = NULL,
.apply_single_controller_ctx_to_hw =
dce110_apply_single_controller_ctx_to_hw,
--
2.43.0
[PATCH 36/39] drm/amd/display: Add dcc propagation value
Initialize the field dcc_meta_propagation_delay_us with 10 ms.
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
index 9fcdf06d6aa4..3e76732ac0dc 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
@@ -723,6 +723,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.min_prefetch_in_strobe_ns = 6, // 60us
.disable_unbounded_requesting = false,
.enable_legacy_fast_update = false,
+ .dcc_meta_propagation_delay_us = 10,
.fams2_config = {
.bits = {
.enable = true,
--
2.43.0
[PATCH 35/39] drm/amd/display: Add missing mcache registers
Add missing register programming for mcache in DCN401. Reviewed-by: Aurabindo Pillai Signed-off-by: Rodrigo Siqueira --- .../gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h index 106008593464..514d1ce20df9 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h @@ -138,7 +138,9 @@ void dcn401_prepare_mcache_programming(struct dc *dc, struct dc_state *context); SRI_ARR(DCHUBP_MALL_CONFIG, HUBP, id), \ SRI_ARR(DCHUBP_VMPG_CONFIG, HUBP, id), \ SRI_ARR(UCLK_PSTATE_FORCE, HUBPREQ, id), \ - HUBP_3DLUT_FL_REG_LIST_DCN401(id) + HUBP_3DLUT_FL_REG_LIST_DCN401(id), \ + SRI_ARR(DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE, HUBP, id), \ + SRI_ARR(DCHUBP_MCACHEID_CONFIG, HUBP, id) /* ABM */ #define ABM_DCN401_REG_LIST_RI(id)\ -- 2.43.0
[PATCH 34/39] drm/amd/display: Remove duplicated code
DCN_MINIMUM_DISPCLK_Khz and DCN_MINIMUM_DPPCLK_Khz is declared twice. This commit removes that duplication. Reviewed-by: Aurabindo Pillai Signed-off-by: Rodrigo Siqueira --- drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h index c55d7279fe51..2d06067ff36d 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h @@ -29,9 +29,6 @@ #include "dc.h" #include "dm_pp_smu.h" -#define DCN_MINIMUM_DISPCLK_Khz 10 -#define DCN_MINIMUM_DPPCLK_Khz 10 - /* Constants */ #define DDR4_DRAM_WIDTH 64 #define WM_A 0 -- 2.43.0
[PATCH 37/39] drm/amd/display: Add missing registers for dcn32
Add missing debug registers for DCN32. Reviewed-by: Aurabindo Pillai Signed-off-by: Rodrigo Siqueira --- .../gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h index fee67fbab8e2..7901792afb7b 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h @@ -505,6 +505,8 @@ unsigned int dcn32_calculate_mall_ways_from_bytes(const struct dc *dc, unsigned SRI_ARR(CM_POST_CSC_B_C11_C12, CM, id), \ SRI_ARR(CM_POST_CSC_B_C33_C34, CM, id), \ SRI_ARR(CM_MEM_PWR_CTRL, CM, id), SRI_ARR(CM_CONTROL, CM, id), \ + SRI_ARR(CM_TEST_DEBUG_INDEX, CM, id), \ + SRI_ARR(CM_TEST_DEBUG_DATA, CM, id), \ SRI_ARR(FORMAT_CONTROL, CNVC_CFG, id), \ SRI_ARR(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \ SRI_ARR(CURSOR0_CONTROL, CNVC_CUR, id), \ @@ -761,6 +763,7 @@ unsigned int dcn32_calculate_mall_ways_from_bytes(const struct dc *dc, unsigned SRI_ARR(DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, DSCC, id), \ SRI_ARR(DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, DSCC, id), \ SRI_ARR(DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, DSCC, id), \ + SRI_ARR(DSCC_TEST_DEBUG_BUS_ROTATE, DSCC, id), \ SRI_ARR(DSCCIF_CONFIG0, DSCCIF, id), \ SRI_ARR(DSCCIF_CONFIG1, DSCCIF, id), \ SRI_ARR(DSCRM_DSC_FORWARD_CONFIG, DSCRM, id) @@ -1185,6 +1188,8 @@ unsigned int dcn32_calculate_mall_ways_from_bytes(const struct dc *dc, unsigned SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL), \ SR(DCHUBBUB_ARB_DRAM_STATE_CNTL), SR(DCHUBBUB_ARB_SAT_LEVEL), \ SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND), SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ + SR(DCHUBBUB_TEST_DEBUG_INDEX), \ + SR(DCHUBBUB_TEST_DEBUG_DATA), \ SR(DCHUBBUB_SOFT_RESET), SR(DCHUBBUB_CRC_CTRL), \ SR(DCN_VM_FB_LOCATION_BASE), SR(DCN_VM_FB_LOCATION_TOP), \ SR(DCN_VM_FB_OFFSET), SR(DCN_VM_AGP_BOT), SR(DCN_VM_AGP_TOP), \ -- 2.43.0
[PATCH 39/39] drm/amd/display: 3.2.294
From: Aric Cyr This version brings along the following: - SPL improvements. - Address coverity issues. - DML2 fixes. - Code cleanup. - DIO and DCCG refactor. - Improve the PSR state. Signed-off-by: Aric Cyr Reviewed-by: Rodrigo Siqueira Signed-off-by: Rodrigo Siqueira --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 4077c1ddb9c1..250d5d48c2d3 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -55,7 +55,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.293" +#define DC_VER "3.2.294" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.43.0
[PATCH 38/39] drm/amd/display: Remove unused code
Remove function pointers that were never used.
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/inc/hw/transform.h | 10 --
1 file changed, 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
index 28da1dddf0a0..45262cba675e 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
@@ -245,16 +245,6 @@ struct transform_funcs {
void (*set_cursor_attributes)(
struct transform *xfm_base,
const struct dc_cursor_attributes *attr);
-
- bool (*transform_program_blnd_lut)(
- struct transform *xfm,
- const struct pwl_params *params);
- bool (*transform_program_shaper_lut)(
- struct transform *xfm,
- const struct pwl_params *params);
- bool (*transform_program_3dlut)(
- struct transform *xfm,
- struct tetrahedral_params *params);
};
const uint16_t *get_filter_2tap_16p(void);
--
2.43.0
