[PATCH 08/25] drm/amd/display: Enable Z10 flag for IPS FSM

[Rodrigo Siqueira]

From: Sung Joon Kim <sungjoon....@amd.com>

[why]
IPS FSM requires Z10 flag to be enabled to do save and restore the
registers properly.

[how]
Enable Z10 and use the correct function to determine Z10 capability

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlaus...@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.sique...@amd.com>
Signed-off-by: Sung Joon Kim <sungjoon....@amd.com>
---
 .../gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c  | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c 
b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
index cc1a44a890b5..b29d7d47552b 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
@@ -758,7 +758,7 @@ static const struct dc_debug_options debug_defaults_drv = {
        //must match enable_single_display_2to1_odm_policy to support dynamic 
ODM transitions
        .enable_double_buffered_dsc_pg_support = true,
        .enable_dp_dig_pixel_rate_div_policy = 1,
-       .disable_z10 = true,
+       .disable_z10 = false,
        .ignore_pg = true,
        .psp_disabled_wa = true,
        .ips2_eval_delay_us = 2000,
@@ -1722,7 +1722,7 @@ static bool dcn351_validate_bandwidth(struct dc *dc,
                return out;
 
        DC_FP_START();
-       dcn351_decide_zstate_support(dc, context);
+       dcn35_decide_zstate_support(dc, context);
        DC_FP_END();
 
        return out;
-- 
2.43.0