From: Nicholas Kazlauskas <nicholas.kazlaus...@amd.com>
[Why]
If we aren't entering RCG/IPS2 or CLKSTOP is not supported by PMFW then
we should be requesting a dispclk value of 0MHz to PMFW.
Currenly we run at max clock since there's an assumption in APU clock
table formulation where we can run at any DISPCLK at any state so the
real clock value ends up as 1200Mhz - the maximum.
[How]
Set to 0 instead of the minimum value in the state array.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlaus...@amd.com>
Reviewed-by: Duncan Ma <duncan...@amd.com>
Signed-off-by: Rodrigo Siqueira <rodrigo.sique...@amd.com>
---
drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
index d5dcc8b77281..866b0abcff1b 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
@@ -575,7 +575,7 @@ static bool dml2_validate_and_build_resource(const struct
dc *in_dc, struct dc_s
unsigned int lowest_state_idx = 0;
out_clks.p_state_supported = true;
- out_clks.dispclk_khz = (unsigned
int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dispclk_mhz *
1000;
+ out_clks.dispclk_khz = 0; /* No requirement, and lowest index
will generally be maximum dispclk. */
out_clks.dcfclk_khz = (unsigned
int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dcfclk_mhz *
1000;
out_clks.fclk_khz = (unsigned
int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].fabricclk_mhz *
1000;
out_clks.uclk_mts = (unsigned
int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dram_speed_mts;
--
2.43.0
