The Turing+ register address space spans over that range, so increase it
as future patches will access more registers.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/nova-core/driver.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/nova-core/driver.rs b/driver
On 5/20/25 17:16, Jens Wiklander wrote:
> Export the dma-buf heap functions declared in .
That is what this patch does and that should be obvious by looking at it. You
need to explain why you do this.
Looking at the rest of the series it's most likely ok, but this commit message
should really b
Since we will need to allocate lots of distinct memory chunks to be
shared between GPU and CPU, introduce a type dedicated to that. It is a
light wrapper around CoherentAllocation.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/nova-core/dma.rs | 61 ++
Upon reset, the GPU executes the GFW (GPU Firmware) in order to
initialize its base parameters such as clocks. The driver must ensure
that this step is completed before using the hardware.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/nova-core/gfw.rs | 37 ++
This macro is pretty complex, and most rules are just helper, so add a
delimiter to indicate when users only interested in using it can stop
reading.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/nova-core/regs/macros.rs | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/nova-c
On 20/05/2025 23:23, Dmitry Baryshkov wrote:
>>
>> There is no checkpatch --strict warning here exactly for the reason I
>> was saying. For readability there should be no empty line after because
>> such statements are expected to be together. I don't mind of course
>> adding one, so I will impleme
On Tue, 20 May 2025 18:43:59 +0100
Adrián Larumbe wrote:
> Perfcnt samples buffer is not exposed to UM, but we would like to keep
> a tag on it as a potential debug aid.
>
> PRIME imported GEM buffers are UM exposed, but since the usual Panfrost
> UM driver code path is not followed in their cre
Move to using the new API devm_drm_panel_alloc() to allocate the
panel.
Reviewed-by: Neil Armstrong
Signed-off-by: Anusha Srivatsa
---
v3: none.
v2: none.
---
drivers/gpu/drm/panel/panel-orisetech-ota5601a.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers
On Wed, May 21, 2025 at 6:11 AM Anusha Srivatsa wrote:
> Move to using the new API devm_drm_panel_alloc() to allocate the
> panel.
>
> Reviewed-by: Neil Armstrong
> Signed-off-by: Anusha Srivatsa
Reviewed-by: Linus Walleij
Yours,
Linus Walleij
Hello Javesh,
At 2025-05-21 15:32:35, "Jayesh Choudhary" wrote:
>Now that we have DBANC framework, remove the connector initialisation code
>as that piece of code is not called if DRM_BRIDGE_ATTACH_NO_CONNECTOR flag
>is used. Only TI K3 platforms consume this driver and tidss (their display
>co
Sorry for the delayed reply.
On 5/19/25 11:04, Philipp Stanner wrote:
>>>
>
> Also, if someone preallocates and does not consume the
> slot
> will that
> confuse the iteration in drm_sched_job_dependency()?
No it doesn't. The xarray is filtering NULL an
Hello Jayesh,
At 2025-05-21 16:15:33, "Andy Yan" wrote:
>
>
>Hello Javesh,
>
>At 2025-05-21 15:32:35, "Jayesh Choudhary" wrote:
>>Now that we have DBANC framework, remove the connector initialisation code
>>as that piece of code is not called if DRM_BRIDGE_ATTACH_NO_CONNECTOR flag
>>is used. On
There are several Panel Replay capability register in DPCD. Read them
all for later use.
v2:
- avoid using hardcoded indices
- read all Panel Replay capability registers
Signed-off-by: Jouni Högander
Reviewed-by: Ankit Nautiyal
---
.../drm/i915/display/intel_display_types.h| 4 +++-
d
Add PHY_CMN1_CONTROL register and its definitions to configure port LFPS
sending.
Bspec: 68962
Signed-off-by: Jouni Högander
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/inte
Wrong mask is used in PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION and
PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION.
Fixes: 295099580f04 ("drm/i915/psr: Add missing ALPM AUX-Less register
definitions")
Signed-off-by: Jouni Högander
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/
Add function to configre LFPS sending for Panel Replay according to link
training sequence in HAS document.
This assumes we are using AUX Less always if it's supported by the sink and
the source.
v2:
- drop HAS reference
- replay kerneldoc comment with a generic comment
- check display vers
Allow Panel Replay with VRR. All VRR modes are supposed to work with
Panel Replay.
Bspec: 68920, 68925
Signed-off-by: Jouni Högander
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_psr.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/
Currently we spread ugly PSR details into ALPM code to check if AUXLess
ALPM is needed. Prepare to hide these details to PSR code by adding new
interface for checking if AUXLess ALPM is needed.
v2: remove kerneldoc comment
Signed-off-by: Jouni Högander
Reviewed-by: Ankit Nautiyal
---
drivers/g
Add PR_ALPM_CTL register definition and bits for it.
Bspec: 71014
Signed-off-by: Jouni Högander
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_psr_regs.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h
b/drivers/
It is specified in Bspec where port alpm configuration is supposed to be
performed. Change accordingly.
v2:
- drop HAS reference
- ensure PORT_ALPM registers are not writen on older platform
Bspec: 68849
Signed-off-by: Jouni Högander
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/dis
we need to know if AUXLess ALPM is used when preparing for link
training. Add new interface for this and use it in existing code where
possible.
v2: remove kerneldoc comment
Signed-off-by: Jouni Högander
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_alpm.c | 10 --
This patch set is adding missing configuration to have Panel Replay
and Adaptive Sync enabled simultaneously. Also some issues identified
while debugging are fixed:
1. Source PORT ALPM configuration has to made during modeset.
2. PHY_CMN1_CONTROL is not written according to HAS document
3. Wrong r
PR_ALPM_CTL register contains configurations related to Adaptive sync
sdp. Configure these if Adaptive Sync SDP is supported.
v2: avoid using hardcoded indices
Bspec: 71014
Signed-off-by: Jouni Högander
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_alpm.c | 14
Add PANEL REPLAY CAPABILITY register (0xb1) bits.
v2: comment about DP2.1 changed as DP2.1a
Signed-off-by: Jouni Högander
---
include/drm/display/drm_dp.h | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
i
Add new definition for size of Panel Replay DPCD capability registers
area. Rename existing definitions to group capability registers together.
Signed-off-by: Jouni Högander
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_psr.c | 8
include/drm/display/drm_dp.h
On Tue, May 20, 2025 at 01:32:41PM -0300, André Almeida wrote:
> When a device get wedged, it might be caused by a guilty application.
> For userspace, knowing which task was the cause can be useful for some
> situations, like for implementing a policy, logs or for giving a chance
> for the composi
> Subject: Re: [PATCH v10 03/10] mtd: intel-dg: implement access functions
>
> On Thu, May 15, 2025 at 04:33:38PM +0300, Alexander Usyskin wrote:
> > Implement read(), erase() and write() functions.
>
> ...
>
> > +__maybe_unused
> > +static unsigned int idg_nvm_get_region(const struct intel_dg_n
Add support for the KDC KD116N3730A05, pleace the EDID here for
subsequent reference.
00 ff ff ff ff ff ff 00 2c 83 20 12 00 00 00 00
30 22 01 04 95 1a 0e 78 03 3a 75 9b 5d 5b 96 28
19 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
01 01 01 01 01 01 09 1e 56 dc 50 00 28 30 30 20
36 00 00 90 10 00 00
When the unit tests were implemented, each scheduler job got its own,
distinct lock. This is not how dma_fence context locking rules are to be
implemented. All jobs belonging to the same fence context (in this case:
scheduler) should share a lock for their dma_fences. This is to comply
to various d
On Tue, 20 May 2025 22:03:31 -0500, Anusha Srivatsa wrote:
> Convert drivers to use the API - devm_drm_panel_alloc().
> There are a lot of occurences of the panel allocation across the
> subsystem. Much thanks to Maxime for the semanic patch which actually
> gives a list of panels allocated unsafel
Reserve a page of system memory so sysmembar can perform a read on it if
a system write occurred since the last flush. Do this early as it can be
required to e.g. reset the GPU falcons.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/nova-core/gpu.rs | 45 ++
On Wed May 21, 2025 at 8:44 AM CEST, Alexandre Courbot wrote:
> We will use this error in the nova-core driver.
>
> Signed-off-by: Alexandre Courbot
> ---
> rust/kernel/error.rs | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Benno Lossin
---
Cheers,
Benno
Now that we have DBANC framework, remove the connector initialisation code
as that piece of code is not called if DRM_BRIDGE_ATTACH_NO_CONNECTOR flag
is used. Only TI K3 platforms consume this driver and tidss (their display
controller) has this flag set. So this legacy support can be dropped.
Sig
Reduce the log level for cdns_mhdp_dpcd_read and cdns_mhdp_dpcd_write
errors in cdns_mhdp_transfer function as in case of failure, there is
flooding of these prints along with other indicators like EDID failure
logs which are fairly intuitive in themselves rendering these error logs
useless.
Also,
After adding DBANC framework, mhdp->connector is not initialised during
bridge calls. But the asyncronous work scheduled depends on the connector.
We cannot get to drm_atomic_state in these asyncronous calls running on
worker threads. So we need to store the data that we need in mhdp bridge
structu
Hello All,
These 3 patches does some fixup for the cdns-mhdp8546 bridge.
- First of all, it removes the legacy !DRM_BRIDGE_ATTACH_NO_CONNECTOR
usecase.
- Then it fixes possible NULL POINTER in cdns_mhdp_modeset_retry_fn
function call where the connector mutex is called. Since we cannot
use t
On 5/21/25 06:17, wangtao wrote:
>>> Reducing CPU overhead/power consumption is critical for mobile devices.
>>> We need simpler and more efficient dmabuf direct I/O support.
>>>
>>> As Christian evaluated sendfile performance based on your data, could
>>> you confirm whether the cache was cleared?
On Tue, 2025-05-20 at 17:15 +0100, Tvrtko Ursulin wrote:
>
> On 19/05/2025 10:04, Philipp Stanner wrote:
> > On Mon, 2025-05-19 at 09:51 +0100, Tvrtko Ursulin wrote:
> > >
> > > On 16/05/2025 18:16, Philipp Stanner wrote:
> > > > On Fri, 2025-05-16 at 15:30 +0100, Tvrtko Ursulin wrote:
> > > > >
Hello Tomi,
On 28/01/25 11:27, Jayesh Choudhary wrote:
Hello Tomi, Alexander,
On 24/01/25 13:38, Alexander Stein wrote:
Hi,
Am Donnerstag, 23. Januar 2025, 17:20:34 CET schrieb Tomi Valkeinen:
Hi,
On 16/01/2025 13:16, Jayesh Choudhary wrote:
For the cases we have DRM_BRIDGE_ATTACH_NO_CONNE
Hi Hugo,
Thanks for the patch.
For some reason, your cover letter is not showing link to this patch
[1] https://lore.kernel.org/all/20250520164034.3453315-1-h...@hugovil.com/
> -Original Message-
> From: Hugo Villeneuve
> Sent: 20 May 2025 18:11
> Subject: [PATCH 1/2] drm: rcar-du: rzg2
On 5/21/25 04:23, Dave Airlie wrote:
>>
>> So in the GPU case, you'd charge on allocation, free objects into a
>> cgroup-specific pool, and shrink using a cgroup-specific LRU
>> list. Freed objects can be reused by this cgroup, but nobody else.
>> They're reclaimed through memory pressure inside th
Some of the firmwares need to be patched at load-time with a signature.
Add a couple of types and traits that sub-modules can use to implement
this behavior, while ensuring that the correct kind of signature is
applied to the firmware.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/nova-core/d
On Tue, May 20, 2025 at 12:26:54PM GMT, Tomeu Vizoso wrote:
> Add the bindings for the Neural Processing Unit IP from Rockchip.
>
> v2:
> - Adapt to new node structure (one node per core, each with its own
> IOMMU)
> - Several misc. fixes from Sebastian Reichel
>
> v3:
> - Split register block
On Tue, 20 May 2025 18:44:01 +0100
Adrián Larumbe wrote:
> This change is essentially a Panfrost port of commit a3707f53eb3f
> ("drm/panthor: show device-wide list of DRM GEM objects over DebugFS").
>
> The DebugFS file is almost the same as in Panthor, minus the GEM object
> usage flags, since
On 5/20/2025 5:32 PM, Dave Airlie wrote:
> On Wed, 21 May 2025 at 04:13, Joel Fernandes wrote:
>>
>>
>>
>> On 5/20/2025 11:36 AM, Danilo Krummrich wrote:
> If you want a helper type with Options while parsing that's totally fine,
> but
> the final result can clearly be without Opti
Hi Eero,
On Wed, 21 May 2025 at 01:59, Eero Tamminen wrote:
> On 23.1.2023 17.10, Geert Uytterhoeven wrote:
> > On Mon, Jan 23, 2023 at 4:09 PM John Paul Adrian Glaubitz
> > wrote:
> >> On 11/25/22 21:31, Geert Uytterhoeven wrote:
> >>> This RFC patch series adds a DRM driver for the good old At
From: Ernest Van Hoecke
AUO G156HAN03.0 EDID:
00 ff ff ff ff ff ff 00 06 af ed 30 00 00 00 00
1a 1c 01 04 a5 22 13 78 02 05 b5 94 59 59 92 28
1d 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
01 01 01 01 01 01 78 37 80 b4 70 38 2e 40 6c 30
aa 00 58 c1 10 00 00 18 00 00 00 0f 00 00 00 00
00 00 00 0
On Wed, May 21, 2025 at 03:44:56PM +0900, Alexandre Courbot wrote:
> These properties are very useful to have and should be accessible.
>
> Signed-off-by: Alexandre Courbot
> ---
> rust/kernel/dma.rs | 18 ++
> 1 file changed, 18 insertions(+)
>
> diff --git a/rust/kernel/dma.rs
Hi Geert,
On 23.1.2023 17.10, Geert Uytterhoeven wrote:
On Mon, Jan 23, 2023 at 4:09 PM John Paul Adrian Glaubitz
wrote:
On 11/25/22 21:31, Geert Uytterhoeven wrote:
This RFC patch series adds a DRM driver for the good old Atari
ST/TT/Falcon hardware. It was developed and tested (only) on th
On 20/05/2025 16:01, Joonas Lahtinen wrote:
(+ Tvrtko, Rodrigo and Jani)
Quoting Krzysztof Niemiec (2025-05-19 18:34:14)
Hi,
This series introduces a way for applications to read local memory
information via files in the sysfs. So far the only way to do this was
via i915_query ioctl. This is
On 5/20/2025 10:23 PM, Jouni Högander wrote:
Add function to configre LFPS sending for Panel Replay according to link
training sequence in HAS document.
This assumes we are using AUX Less always if it's supported by the sink and
the source.
v2:
- drop HAS reference
- replay kerneldoc co
On Wed, May 21, 2025 at 03:45:03PM +0900, Alexandre Courbot wrote:
> Some registers (notably scratch registers) don't have a definitive
> purpose, but need to be interpreted differently depending on context.
>
> Expand the register!() macro to support a syntax indicating that a
> register type sho
On 5/15/25 18:17, Tvrtko Ursulin wrote:
>
> On 15/05/2025 16:00, Christian König wrote:
>> Sometimes drivers need to be able to submit multiple jobs which depend on
>> each other to different schedulers at the same time, but using
>> drm_sched_job_add_dependency() can't fail any more after the fir
On 21/05/2025 11:04, Philipp Stanner wrote:
When the unit tests were implemented, each scheduler job got its own,
distinct lock. This is not how dma_fence context locking rules are to be
implemented. All jobs belonging to the same fence context (in this case:
scheduler) should share a lock for
On 16/5/25 02:53, Zhi Wang wrote:
On Thu, 15 May 2025 16:44:47 +
Zhi Wang wrote:
On 15.5.2025 13.29, Alexey Kardashevskiy wrote:
On 13/5/25 20:03, Zhi Wang wrote:
On Mon, 12 May 2025 11:06:17 -0300
Jason Gunthorpe wrote:
On Mon, May 12, 2025 at 07:30:21PM +1000, Alexey Kardashevs
> -Original Message-
> From: Christian König
> Sent: Wednesday, May 21, 2025 3:36 PM
> To: wangtao ; T.J. Mercier
>
> Cc: sumit.sem...@linaro.org; benjamin.gaign...@collabora.com;
> brian.star...@arm.com; jstu...@google.com; linux-me...@vger.kernel.org;
> dri-devel@lists.freedesktop.org
On 5/9/2025 9:31 PM, Dmitry Baryshkov wrote:
On 09/05/2025 09:18, Jyothi Kumar Seerapu wrote:
Hi Dimitry, Thanks for providing the review comments.
On 5/6/2025 5:16 PM, Dmitry Baryshkov wrote:
On Tue, May 06, 2025 at 04:48:44PM +0530, Jyothi Kumar Seerapu wrote:
The I2C driver gets an inte
On 5/21/2025 3:02 PM, Jouni Högander wrote:
Add PANEL REPLAY CAPABILITY register (0xb1) bits.
v2: comment about DP2.1 changed as DP2.1a
Signed-off-by: Jouni Högander
---
include/drm/display/drm_dp.h | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/include/drm
Hi all,
After merging the drm tree, today's linux-next build (htmldocs) produced
this warning:
Error: Cannot open file drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c
Introduced by commit
c472d828348c ("drm/nouveau/gsp: move subdev/engine impls to
subdev/gsp/rm/r535/")
--
Cheers,
Stephen Ro
Hi Laurent,
Thanks for your feedback.
> From: Laurent Pinchart
> Sent: 20 May 2025 15:24
> Subject: Re: [PATCH v5 08/12] drm: renesas: rz-du: mipi_dsi: Use mHz for
> D-PHY frequency calculations
>
> Hi Prabhakar,
>
> Thank you for the patch.
>
> On Mon, May 12, 2025 at 07:23:26PM +0100, Prab
Hi Andy,
On 2025/5/21 20:09, Andy Yan wrote:
Hi Chaoyi，
At 2025-05-07 11:51:48, "Chaoyi Chen" wrote:
From: Chaoyi Chen
Convert it to drm bridge driver, it will be convenient for us to
migrate the connector part to the display driver later.
Tested with RK3399 EVB IND board.
Signed-off-by:
Hi,
On Thu, May 8, 2025 at 4:54 AM Jayesh Choudhary wrote:
>
> By default, HPD was disabled on SN65DSI86 bridge. When the driver was
> added (commit "a095f15c00e27"), the HPD_DISABLE bit was set in pre-enable
> call which was moved to other function calls subsequently.
> Later on, commit "c312b0d
Hi Biju,
On Wed, 21 May 2025 07:43:08 +
Biju Das wrote:
> Hi Hugo,
>
> Thanks for the patch.
>
> For some reason, your cover letter is not showing link to this patch
> [1] https://lore.kernel.org/all/20250520164034.3453315-1-h...@hugovil.com/
My server had problems, and only sent the cove
Currently we expose the ability to retrieve an SGTable for an shmem gem
object using gem::shmem::Objectsg_table(). However, this only gives us a
borrowed reference. This being said - retrieving an SGTable is a fallible
operation, and as such it's reasonable that a driver may want to hold
onto a
Hi,
On Wed, May 21, 2025 at 2:37 AM Langyan Ye
wrote:
>
> Add support for the KDC KD116N3730A05, pleace the EDID here for
> subsequent reference.
>
> 00 ff ff ff ff ff ff 00 2c 83 20 12 00 00 00 00
> 30 22 01 04 95 1a 0e 78 03 3a 75 9b 5d 5b 96 28
> 19 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
It's unclear why I originally wrote in the description of
`prepare_to_enable` that "This is not specified in a standard way on
eDP timing diagrams" and then also wrote "It is effectively the time
from HPD going high till you can turn on the backlight." It seems
pretty clear that it's (T4+T5+T6+T8)-
From: Dave Airlie
This device pointer is nearly always available without storing
an extra copy for each tt in the system.
Just noticed this while reading over the xe shrinker code.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/xe/tests/xe_bo.c | 4 +--
drivers/gpu/drm/xe/xe_bo.c | 59
On 2025-05-17 07:51, Xaver Hugl wrote:
> Am Do., 15. Mai 2025 um 22:00 Uhr schrieb Leandro Ribeiro
> :
>>
>>
>>
>> On 5/15/25 15:39, Daniel Stone wrote:
>>> Hi,
>>>
>>> On Thu, 15 May 2025 at 19:02, Harry Wentland wrote:
On 2025-05-15 13:19, Daniel Stone wrote:
> Yeah, the Weston patch
Hi Marco,
Thank you for the patch.
On Thu, May 15, 2025 at 07:36:43PM +0200, Marco Felsch wrote:
> Make use of __free(device_node) to simplify the of_node_put() error
> handling paths. No functional changes.
>
> Signed-off-by: Marco Felsch
Reviewed-by: Laurent Pinchart
> ---
> Changelog:
> v
On Thu, May 15, 2025 at 04:33:38PM +0300, Alexander Usyskin wrote:
> Implement read(), erase() and write() functions.
...
> +__maybe_unused
> +static ssize_t idg_write(struct intel_dg_nvm *nvm, u8 region,
> + loff_t to, size_t len, const unsigned char *buf)
> +{
> + size_
kzalloc() already zero-initializes the destination buffers, making
strscpy() sufficient for safely copying the names. The additional
NUL-padding performed by strscpy_pad() is unnecessary.
If the destination buffer has a fixed length, strscpy() automatically
determines its size using sizeof() when
Hi Geert,
Thank you for the review.
On Tue, May 20, 2025 at 3:55 PM Geert Uytterhoeven wrote:
>
> Hi Prabhakar,
>
> On Mon, 12 May 2025 at 20:23, Prabhakar wrote:
> > From: Lad Prabhakar
> >
> > Update the RZ/G2L MIPI DSI driver to calculate HSFREQ using the actual
> > VCLK rate instead of the
> -Original Message-
> From: Lad, Prabhakar
> Sent: Wednesday, May 21, 2025 2:05 PM
> Subject: Re: [PATCH v5 05/12] drm: renesas: rz-du: mipi_dsi: Use VCLK for
> HSFREQ calculation
>
> Hi Laurent,
>
> Thank you for the review.
>
> On Tue, May 20, 2025 at 3:16 PM Laurent Pinchart
> wr
On Wed, May 21, 2025 at 03:58:48PM +0530, Jyothi Kumar Seerapu wrote:
>
>
> On 5/9/2025 9:31 PM, Dmitry Baryshkov wrote:
> > On 09/05/2025 09:18, Jyothi Kumar Seerapu wrote:
> > > Hi Dimitry, Thanks for providing the review comments.
> > >
> > > On 5/6/2025 5:16 PM, Dmitry Baryshkov wrote:
> > >
Hi Laurent,
Thank you for the review.
On Tue, May 20, 2025 at 3:28 PM Laurent Pinchart
wrote:
>
> Hi Prabhakar,
>
> Thank you for the patch.
>
> On Mon, May 12, 2025 at 07:23:28PM +0100, Prabhakar wrote:
> > From: Lad Prabhakar
> >
> > Introduce the `dphy_late_init` callback in `rzg2l_mipi_dsi_
Hi Laurent,
Thank you for the review.
On Tue, May 20, 2025 at 3:05 PM Laurent Pinchart
wrote:
>
> Hi Prabhakar,
>
> Thank you for the patch.
>
> On Mon, May 12, 2025 at 07:23:22PM +0100, Prabhakar wrote:
> > From: Lad Prabhakar
> >
> > Simplify the high-speed clock frequency (HSFREQ) calculatio
On 20/05/2025 23:29, Dmitry Baryshkov wrote:
On Tue, May 20, 2025 at 09:57:38AM +0200, neil.armstr...@linaro.org wrote:
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_ACTIVE_CFG feature bit with the
On Wed, May 21, 2025 at 03:44:58PM +0900, Alexandre Courbot wrote:
> nova-core will need to use SZ_1M, so make the remaining constants
> available.
>
> Signed-off-by: Alexandre Courbot
Reviewed-by: Boqun Feng
Regards,
Boqun
> ---
> rust/kernel/sizes.rs | 24
> 1 file
On Mon, May 19, 2025 at 03:50:19PM +0100, Ashley Smith wrote:
> This fixes a bug where if we timeout after a suspend and the termination
> fails, due to waiting on a fence that will never be signalled for
> example, we do not resume the group correctly. The fix forces a reset
> for groups that are
From: Leonardo da Silva Gomes
Adjust the dcn31_apg construct function name from
'apg31_construct' to 'dcn31_apg_construct'.
This helps the ftrace to detect the file by the function name.
Signed-off-by: Leonardo da Silva Gomes
Co-developed-by: Derick Frias
Signed-off-by: Derick Frias
---
driv
amdgpu CRIU requires an amdgpu CRIU ioctl. This ioctl
has a similar interface to the amdkfd CRIU ioctl.
The objects that can be checkpointed and restored are bos and vm
mappings. Because a single amdgpu bo can have multiple mappings.
the mappings are recorded separately.
The ioctl has two modes:
The kfd CRIU checkpoint ioctl would return an error if trying
to checkpoint a process with no kfd buffer objects.
This is a normal case and should not be an error.
Signed-off-by: David Francis
---
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
di
(previous patches were incorrectly called v3 but were actually the 4th version)
This patch series adds support for CRIU checkpointing of processes that
share memory with the amdgpu dmabuf interface.
In this v5, the drm interfaces have been changed from creating buffer objects
with specified gem h
Hi Laurent,
Thank you for the review.
On Tue, May 20, 2025 at 3:22 PM Laurent Pinchart
wrote:
>
> Hi Prabhakar,
>
> Thank you for the patch.
>
> On Mon, May 12, 2025 at 07:23:24PM +0100, Prabhakar wrote:
> > From: Lad Prabhakar
> >
> > In preparation for adding support for the Renesas RZ/V2H(P)
Hi Jared,
On Thu, Apr 24, 2025 at 09:11:24AM -0700, Jared Kangas wrote:
> > > struct cma_heap {
> > > struct dma_heap *heap;
> > > @@ -394,15 +395,26 @@ static int __init __add_cma_heap(struct cma *cma,
> > > const char *name)
> > > static int __init add_default_cma_heap(void)
> > > {
> > >
This patchset implements a request made by Xaver Hugl about wedge events:
"I'd really like to have the PID of the client that triggered the GPU
reset, so that we can kill it if multiple resets are triggered in a
row (or switch to software rendering if it's KWin itself) and show a
user-friendly not
Add a section about "Task information" for the wedge API.
Reviewed-by: Krzysztof Karas
Reviewed-by: Raag Jadav
Signed-off-by: André Almeida
---
v5:
- Change app to task in the text as well
v4:
- Change APP to TASK
v3:
- Change "app that caused ..." to "app involved ..."
- Clarify that devco
When a device get wedged, it might be caused by a guilty application.
For userspace, knowing which task was the cause can be useful for some
situations, like for implementing a policy, logs or for giving a chance
for the compositor to let the user know what task caused the problem.
This is an optio
To notify userspace about which task (if any) made the device get in a
wedge state, make use of drm_wedge_task_info parameter, filling it with
the task PID and name.
Signed-off-by: André Almeida
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 19 +--
drivers/gpu/drm/amd/amdgpu/a
On Wed May 21, 2025 at 9:43 PM JST, Boqun Feng wrote:
> On Wed, May 21, 2025 at 03:44:56PM +0900, Alexandre Courbot wrote:
>> These properties are very useful to have and should be accessible.
>>
>> Signed-off-by: Alexandre Courbot
>> ---
>> rust/kernel/dma.rs | 18 ++
>> 1 file
Hi Dave & Sima,
Here goes another drm-intel-next-fixes PR towards 6.16-rc1.
Thunderbolt disconnect fix for MTL/ARL/LNL, DDI port clock fix for PTL+ and WQ
allocation error check for display init code.
Regards, Joonas
PS. CI results were for one patch more, which I reverted during review
of the
On Wed, May 21, 2025 at 9:13 AM Christian König
wrote:
>
> On 5/20/25 17:16, Jens Wiklander wrote:
> > Export the dma-buf heap functions declared in .
>
> That is what this patch does and that should be obvious by looking at it. You
> need to explain why you do this.
>
> Looking at the rest of th
From: Dave Airlie
This reduces this struct from 16 to 8 bytes, and it gets embedded
into a lot of things.
Signed-off-by: Dave Airlie
---
include/linux/iosys-map.h | 30 --
1 file changed, 8 insertions(+), 22 deletions(-)
diff --git a/include/linux/iosys-map.h b/inc
From: Dave Airlie
This avoids directly accessing the iosys_map internals using new interfaces.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/drm_cache.c | 28 +--
drivers/gpu/drm/drm_fbdev_shmem.c | 4 +--
drivers/gpu/drm/drm_format_helper.c
From: Dave Airlie
This uses the new accessors to avoid touch iosys_map internals.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/xe/display/intel_fbdev_fb.c | 2 +-
drivers/gpu/drm/xe/xe_bo.c | 8
drivers/gpu/drm/xe/xe_eu_stall.c| 2 +-
drivers/gpu/drm/
From: Dave Airlie
This adds accessors inlines to the iosys-map. The intent is to
roll the iomem flag into the lower bits of the vaddr eventually.
First just add accessors to move all current in-tree users over to.
Signed-off-by: Dave Airlie
---
include/linux/iosys-map.h | 53 +
From: Dave Airlie
Now hide the current implementation details, to catch any new
users entering the tree and trying to trick us up.
Signed-off-by: Dave Airlie
---
include/linux/iosys-map.h | 48 +++
1 file changed, 24 insertions(+), 24 deletions(-)
diff --gi
Hi David,
kernel test robot noticed the following build warnings:
[auto build test WARNING on drm/drm-next]
[also build test WARNING on next-20250521]
[cannot apply to drm-exynos/exynos-drm-next linus/master v6.15-rc7]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And
Hi Pierre-Eric,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-xe/drm-xe-next]
[also build test ERROR on next-20250521]
[cannot apply to lwn/docs-next linus/master v6.15-rc7]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when
On 21/05/2025 18:10, Krzysztof Niemiec wrote:
On 2025-05-21 at 09:06:43 GMT, Tvrtko Ursulin wrote:
On 20/05/2025 16:01, Joonas Lahtinen wrote:
(+ Tvrtko, Rodrigo and Jani)
Quoting Krzysztof Niemiec (2025-05-19 18:34:14)
Hi,
This series introduces a way for applications to read local memor
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