From: Zhao Liu <zhao1....@intel.com>
For hybrid cpu topology, Intel exposes these CPUIDs [1]:
1. Set CPUID.07H.0H:EDX.Hybrid[bit 15]. With setting as 1, the processor
is identified as a hybrid part.
2. Have CPUID.1AH leaf. Set core type and native model ID in
CPUID.1AH:EAX. Because the native model ID is currently useless for
the software, no need to emulate.
For hybrid related CPUIDs, especially CPUID.07H.0H:EDX.Hybrid[bit 15],
there's no need to expose this feature in feature_word_info[] to allow
user to set directly, because hybrid features depend on the specific
core type information, and this information needs to be gathered
together with hybrid cpu topology.
[1]: SDM, vol.2, Ch.3, 3.2 Instructions (A-L), CPUID-CPU Identification
Co-Developed-by: Zhuocheng Ding <zhuocheng.d...@intel.com>
Signed-off-by: Zhuocheng Ding <zhuocheng.d...@intel.com>
Signed-off-by: Zhao Liu <zhao1....@intel.com>
---
target/i386/cpu.c | 43 +++++++++++++++++++++++++++++++++++++++++++
target/i386/cpu.h | 2 ++
2 files changed, 45 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 266e981b79e2..a0aaaf996222 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -620,6 +620,10 @@ static CPUCacheInfo legacy_l3_cache = {
#define INTEL_AMX_TMUL_MAX_K 0x10
#define INTEL_AMX_TMUL_MAX_N 0x40
+/* CPUID Leaf 0x1A constants: */
+#define INTEL_HYBRID_TYPE_ATOM 0x20
+#define INTEL_HYBRID_TYPE_CORE 0x40
+
void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
uint32_t vendor2, uint32_t vendor3)
{
@@ -5416,6 +5420,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
}
*edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
+ if (env->hybrid_core_type != INVALID_HYBRID_TYPE &&
+ (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) {
+ *edx |= CPUID_7_0_EDX_HYBRID;
+ }
+
/*
* SGX cannot be emulated in software. If hardware does not
* support enabling SGX and/or SGX flexible launch control,
@@ -5671,6 +5680,31 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
}
break;
}
+ case 0x1A:
+ /* Hybrid Information Enumeration */
+ *eax = 0;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0;
+ if (env->hybrid_core_type != INVALID_HYBRID_TYPE &&
+ (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) {
+ /*
+ * CPUID.1AH:EAX.[bits 23-0] indicates "native model ID of the
+ * core". Since this field currently is useless for software,
+ * no need to emulate.
+ */
+ switch (env->hybrid_core_type) {
+ case INTEL_ATOM_TYPE:
+ *eax = INTEL_HYBRID_TYPE_ATOM << 24;
+ break;
+ case INTEL_CORE_TYPE:
+ *eax = INTEL_HYBRID_TYPE_CORE << 24;
+ break;
+ default:
+ abort();
+ }
+ }
+ break;
case 0x1D: {
/* AMX TILE */
*eax = 0;
@@ -6314,6 +6348,15 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
}
}
+ /*
+ * Intel CPU topology with hybrid cores support requires CPUID.1AH.
+ * And CPUID.07H.0H:EDX.Hybrid[bit 15] is also required.
+ */
+ if (env->hybrid_core_type != INVALID_HYBRID_TYPE &&
+ (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) {
+ x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1A);
+ }
+
/*
* Intel CPU topology with multi-dies support requires CPUID[0x1F].
* For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index bb4e370f9768..8fd7b0c55ae8 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -877,6 +877,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
#define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8)
/* SERIALIZE instruction */
#define CPUID_7_0_EDX_SERIALIZE (1U << 14)
+/* Hybrid */
+#define CPUID_7_0_EDX_HYBRID (1U << 15)
/* TSX Suspend Load Address Tracking instruction */
#define CPUID_7_0_EDX_TSX_LDTRK (1U << 16)
/* Architectural LBRs */
--
2.34.1
