This is the Arm specific changes required to reduce the
amount of translation for address space randomization.
Changes for v5:
* Minor updates for patch review, mostly using target_long
for pc displacements.
r~
Based-on: 20220930212622.108363-1-richard.hender...@linaro.org
("[PATCH v6 00/18] tcg: CPUTLBEntryFull and TARGET_TB_PCREL")
Richard Henderson (9):
target/arm: Introduce curr_insn_len
target/arm: Change gen_goto_tb to work on displacements
target/arm: Change gen_*set_pc_im to gen_*update_pc
target/arm: Change gen_exception_insn* to work on displacements
target/arm: Remove gen_exception_internal_insn pc argument
target/arm: Change gen_jmp* to work on displacements
target/arm: Introduce gen_pc_plus_diff for aarch64
target/arm: Introduce gen_pc_plus_diff for aarch32
target/arm: Enable TARGET_TB_PCREL
target/arm/cpu-param.h | 1 +
target/arm/translate-a32.h | 2 +-
target/arm/translate.h | 35 ++++-
target/arm/cpu.c | 23 ++--
target/arm/translate-a64.c | 174 +++++++++++++++----------
target/arm/translate-m-nocp.c | 6 +-
target/arm/translate-mve.c | 2 +-
target/arm/translate-vfp.c | 10 +-
target/arm/translate.c | 235 +++++++++++++++++++++-------------
9 files changed, 303 insertions(+), 185 deletions(-)
--
2.34.1
