On 24 December 2011 00:54, Rob Herring <rob.herr...@calxeda.com> wrote: > Mark, > > On 12/22/2011 12:20 PM, Mark Langsdorf wrote: >> From: Rob Herring <rob.herr...@calxeda.com> >> >> Signed-off-by: Rob Herring <rob.herr...@calxeda.com> >> Signed-off-by: Mark Langsdorf <mark.langsd...@calxeda.com> >> --- >> hw/a9mpcore.c | 2 +- >> 1 files changed, 1 insertions(+), 1 deletions(-) >> >> diff --git a/hw/a9mpcore.c b/hw/a9mpcore.c >> index 875ae98..93b0498 100644 >> --- a/hw/a9mpcore.c >> +++ b/hw/a9mpcore.c >> @@ -13,7 +13,7 @@ >> /* Configuration for arm_gic.c: >> * number of external IRQ lines, max number of CPUs, how to ID current CPU >> */ >> -#define GIC_NIRQ 96 >> +#define GIC_NIRQ 160 >> #define NCPU 4 > > This needs to be run-time. The value gets put in a register and read by > the OS. It breaks platforms expecting 96 irqs.
Also the hardware maximum for the A9 is 256, so bumping the compile time maximum to only 160 wouldn't make sense. (The GIC architectural limit is 1020 interrupts.) FYI: In the long term the place I would like to get to is to have the GIC be a properly separated out qdev device, rather than a bit of code which is #included by various different source files which do this kind of compile-time configuration for it. Having the private peripheral qdev devices be subclasses of the GIC is also a bit of a workaround for limitations of our current device object model which I hope QOM will let us rearrange. -- PMM
