On 6/14/22 21:08, Bin Meng wrote:
From: Bin Meng <bin.m...@windriver.com>
When watchpoint is hit, the breakpoint exception should update tval
to point to the faulting virtual address.
Signed-off-by: Bin Meng <bin.m...@windriver.com>
---
target/riscv/cpu.h | 1 +
target/riscv/cpu_helper.c | 6 ++++++
target/riscv/debug.c | 2 ++
3 files changed, 9 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7d6397acdf..fdcba8978b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -289,6 +289,7 @@ struct CPUArchState {
/* trigger module */
target_ulong trigger_cur;
+ bool wp_hit;
It would be better to not add this, which duplicates cs->watchpoint_hit.
In riscv_cpu_debug_excp_handler, raise a synthetic exception number
(RISCV_EXCP_WATCHPOINT?), then set tval in the same switch as the others.
r~
