From: Bin Meng <bin.m...@windriver.com>
When watchpoint is hit, the breakpoint exception should update tval
to point to the faulting virtual address.
Signed-off-by: Bin Meng <bin.m...@windriver.com>
---
target/riscv/cpu.h | 1 +
target/riscv/cpu_helper.c | 6 ++++++
target/riscv/debug.c | 2 ++
3 files changed, 9 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7d6397acdf..fdcba8978b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -289,6 +289,7 @@ struct CPUArchState {
/* trigger module */
target_ulong trigger_cur;
+ bool wp_hit;
type2_trigger_t type2_trig[TRIGGER_TYPE2_NUM];
/* machine specific rdtime callback */
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 4a6700c890..f1564ce51e 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1345,6 +1345,12 @@ void riscv_cpu_do_interrupt(CPUState *cs)
target_ulong htval = 0;
target_ulong mtval2 = 0;
+ /* only update tval for watchpoint */
+ if (cause == RISCV_EXCP_BREAKPOINT && env->wp_hit) {
+ env->wp_hit = false;
+ tval = env->badaddr;
+ }
+
if (cause == RISCV_EXCP_SEMIHOST) {
if (env->priv >= PRV_S) {
env->gpr[xA0] = do_common_semihosting(cs);
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index fc6e13222f..89b12c6bef 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -407,6 +407,8 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs,
CPUWatchpoint *wp)
if ((wp->flags & flags) && (wp->vaddr == addr)) {
/* check U/S/M bit against current privilege level */
if ((ctrl >> 3) & BIT(env->priv)) {
+ env->wp_hit = true;
+ env->badaddr = addr;
return true;
}
}
--
2.34.1
