This patchset implements RISC-V Float-Point in Integer Registers extensions(Version 1.0.0-rc), which includes Zfinx, Zdinx, Zhinx and Zhinxmin extension.
Specification: https://github.com/riscv/riscv-zfinx/blob/main/zfinx-1.0.0-rc.pdf The port is available here: https://github.com/plctlab/plct-qemu/tree/plct-zfinx-upstream To test this implementation, specify cpu argument with 'Zfinx =true,Zdinx=true,Zhinx=true,Zhinxmin=true' with 'g=false,f=false,d=false,Zfh=false,Zfhmin-false' This implementation can pass gcc tests, ci result can be found in https://ci.rvperf.org/job/plct-qemu-zfinx-upstream/. liweiwei (6): target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} target/riscv: add support for unique fpr read/write with support for zfinx target/riscv: add support for zfinx target/riscv: add support for zdinx target/riscv: add support for zhinx/zhinxmin target/riscv: expose zfinx, zdinx, zhinx{min} properties roms/SLOF | 2 +- target/riscv/cpu.c | 16 + target/riscv/cpu.h | 4 + target/riscv/fpu_helper.c | 120 ++++---- target/riscv/helper.h | 4 +- target/riscv/insn_trans/trans_rvd.c.inc | 252 +++++++++++----- target/riscv/insn_trans/trans_rvf.c.inc | 330 ++++++++++++++------- target/riscv/insn_trans/trans_rvzfh.c.inc | 342 +++++++++++++++------- target/riscv/internals.h | 12 +- target/riscv/translate.c | 177 +++++++++++ 10 files changed, 914 insertions(+), 345 deletions(-) -- 2.17.1
