This is a partial patch set attempting to set things in the
right direction for both the UXL and RV128 patch sets.
r~
Changes for v5:
* Fix cpu_dump, which asserted for -accel qtest.
Instead of filtering CSRs explicitly in cpu_dump,
let the riscv_csr_operations predicate do the job.
This means we won't dump S-mode registers when RVS
is not enabled, much like we currently filter on RVH.
Changes for v4:
* Use riscv_csrrw_debug for cpu_dump.
This fixes the issue that Alistair pointed out wrt the
MSTATUS.SD bit not being correct in the dump; note that
gdbstub already uses riscv_csrrw_debug, and so did not
have a problem.
* Align the registers in cpu_dump.
Changes for v3:
* Fix CONFIG_ typo.
* Fix ctzw typo.
* Mark get_xlen unused (clang werror)
* Compute MSTATUS_SD on demand.
Changes for v2:
* Set mxl/sxl/uxl at reset.
* Set sxl/uxl in write_mstatus.
Richard Henderson (16):
target/riscv: Move cpu_get_tb_cpu_state out of line
target/riscv: Create RISCVMXL enumeration
target/riscv: Split misa.mxl and misa.ext
target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
target/riscv: Add MXL/SXL/UXL to TB_FLAGS
target/riscv: Use REQUIRE_64BIT in amo_check64
target/riscv: Properly check SEW in amo_op
target/riscv: Replace is_32bit with get_xl/get_xlen
target/riscv: Replace DisasContext.w with DisasContext.ol
target/riscv: Use gen_arith_per_ol for RVM
target/riscv: Adjust trans_rev8_32 for riscv64
target/riscv: Use gen_unary_per_ol for RVB
target/riscv: Use gen_shift*_per_ol for RVB, RVI
target/riscv: Align gprs and fprs in cpu_dump
target/riscv: Use riscv_csrrw_debug for cpu_dump
target/riscv: Compute mstatus.sd on demand
target/riscv/cpu.h | 73 +++------
target/riscv/cpu_bits.h | 8 +-
hw/riscv/boot.c | 2 +-
linux-user/elfload.c | 2 +-
linux-user/riscv/cpu_loop.c | 2 +-
semihosting/arm-compat-semi.c | 2 +-
target/riscv/cpu.c | 203 ++++++++++++++----------
target/riscv/cpu_helper.c | 92 ++++++++++-
target/riscv/csr.c | 104 +++++++-----
target/riscv/gdbstub.c | 10 +-
target/riscv/machine.c | 10 +-
target/riscv/monitor.c | 4 +-
target/riscv/translate.c | 174 +++++++++++++++-----
target/riscv/insn_trans/trans_rvb.c.inc | 140 ++++++++--------
target/riscv/insn_trans/trans_rvi.c.inc | 44 ++---
target/riscv/insn_trans/trans_rvm.c.inc | 36 ++++-
target/riscv/insn_trans/trans_rvv.c.inc | 29 ++--
17 files changed, 581 insertions(+), 354 deletions(-)
--
2.25.1
