On Wed, Oct 20, 2021 at 2:18 AM Richard Henderson <richard.hender...@linaro.org> wrote: > > Allocate 8 columns per register name. > > Reviewed-by: LIU Zhiwei <zhiwei_...@c-sky.com> > Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> This probably isn't required though as there is already a similar patch in my tree: https://github.com/alistair23/qemu/tree/riscv-to-apply.next Alistair > --- > target/riscv/cpu.c | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 4e1920d5f0..f352c2b74c 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -240,7 +240,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, > int flags) > qemu_fprintf(f, " %s %d\n", "V = ", > riscv_cpu_virt_enabled(env)); > } > #endif > - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); > + qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", "pc", env->pc); > #ifndef CONFIG_USER_ONLY > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", > (target_ulong)env->mstatus); > @@ -290,15 +290,16 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, > int flags) > #endif > > for (i = 0; i < 32; i++) { > - qemu_fprintf(f, " %s " TARGET_FMT_lx, > + qemu_fprintf(f, " %-8s " TARGET_FMT_lx, > riscv_int_regnames[i], env->gpr[i]); > if ((i & 3) == 3) { > qemu_fprintf(f, "\n"); > } > } > + > if (flags & CPU_DUMP_FPU) { > for (i = 0; i < 32; i++) { > - qemu_fprintf(f, " %s %016" PRIx64, > + qemu_fprintf(f, " %-8s %016" PRIx64, > riscv_fpr_regnames[i], env->fpr[i]); > if ((i & 3) == 3) { > qemu_fprintf(f, "\n"); > -- > 2.25.1 > >
