This patch implement branch instruction translation.
This includes:
- BEQ, BNE, BLT[U], BGE[U]
- BEQZ, BNEZ
- B
- BL
- JIRL
- BCEQZ, BCNEZ
Signed-off-by: Song Gao <gaos...@loongson.cn>
---
target/loongarch/insns.decode | 30 +++++
target/loongarch/trans.inc.c | 249 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 279 insertions(+)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index ea776c2..077063e 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -38,6 +38,9 @@
%ca 15:3
%fcsrd 0:5
%fcsrs 5:5
+%offs21 0:s5 10:16
+%offs16 10:s16
+%offs 0:s10 10:16
#
# Argument sets
@@ -74,6 +77,11 @@
&fmt_rdcj rd cj
&fmt_fdrjrk fd rj rk
&fmt_fdrjsi12 fd rj si12
+&fmt_rjoffs21 rj offs21
+&fmt_cjoffs21 cj offs21
+&fmt_rdrjoffs16 rd rj offs16
+&fmt_offs offs
+&fmt_rjrdoffs16 rj rd offs16
#
# Formats
@@ -110,6 +118,11 @@
@fmt_rdcj .... ........ ..... ..... .. ... ..... &fmt_rdcj
%rd %cj
@fmt_fdrjrk .... ........ ..... ..... ..... ..... &fmt_fdrjrk
%fd %rj %rk
@fmt_fdrjsi12 .... ...... ............ ..... ..... &fmt_fdrjsi12
%fd %rj %si12
+@fmt_rjoffs21 .... .. ................ ..... ..... &fmt_rjoffs21
%rj %offs21
+@fmt_cjoffs21 .... .. ................ .. ... ..... &fmt_cjoffs21
%cj %offs21
+@fmt_rdrjoffs16 .... .. ................ ..... ..... &fmt_rdrjoffs16
%rd %rj %offs16
+@fmt_offs .... .. .......................... &fmt_offs
%offs
+@fmt_rjrdoffs16 .... .. ................ ..... ..... &fmt_rjrdoffs16
%rj %rd %offs16
#
# Fixed point arithmetic operation instruction
@@ -448,3 +461,20 @@ fstgt_s 0011 10000111 01100 ..... ..... .....
@fmt_fdrjrk
fstgt_d 0011 10000111 01101 ..... ..... ..... @fmt_fdrjrk
fstle_s 0011 10000111 01110 ..... ..... ..... @fmt_fdrjrk
fstle_d 0011 10000111 01111 ..... ..... ..... @fmt_fdrjrk
+
+#
+# Branch instructions
+#
+beqz 0100 00 ................ ..... ..... @fmt_rjoffs21
+bnez 0100 01 ................ ..... ..... @fmt_rjoffs21
+bceqz 0100 10 ................ 00 ... ..... @fmt_cjoffs21
+bcnez 0100 10 ................ 01 ... ..... @fmt_cjoffs21
+jirl 0100 11 ................ ..... ..... @fmt_rdrjoffs16
+b 0101 00 .......................... @fmt_offs
+bl 0101 01 .......................... @fmt_offs
+beq 0101 10 ................ ..... ..... @fmt_rjrdoffs16
+bne 0101 11 ................ ..... ..... @fmt_rjrdoffs16
+blt 0110 00 ................ ..... ..... @fmt_rjrdoffs16
+bge 0110 01 ................ ..... ..... @fmt_rjrdoffs16
+bltu 0110 10 ................ ..... ..... @fmt_rjrdoffs16
+bgeu 0110 11 ................ ..... ..... @fmt_rjrdoffs16
diff --git a/target/loongarch/trans.inc.c b/target/loongarch/trans.inc.c
index 8adfdd3..0c67c54 100644
--- a/target/loongarch/trans.inc.c
+++ b/target/loongarch/trans.inc.c
@@ -5285,3 +5285,252 @@ static bool trans_fstle_d(DisasContext *ctx,
arg_fstle_d *a)
}
#undef DECL_ARG2
+
+/* Branch Instructions translation */
+static bool trans_beqz(DisasContext *ctx, arg_beqz *a)
+{
+ TCGv t0, t1;
+ int bcond_flag = 0;
+
+ t0 = tcg_temp_new();
+ t1 = tcg_const_i64(0);
+
+ if (a->rj != 0) {
+ gen_load_gpr(t0, a->rj);
+ bcond_flag = 1;
+ }
+
+ if (bcond_flag == 0) {
+ ctx->hflags |= LOONGARCH_HFLAG_B;
+ } else {
+ tcg_gen_setcond_tl(TCG_COND_EQ, bcond, t0, t1);
+ ctx->hflags |= LOONGARCH_HFLAG_BC;
+ }
+ ctx->btarget = ctx->base.pc_next + (a->offs21 << 2);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+
+ return true;
+}
+
+static bool trans_bnez(DisasContext *ctx, arg_bnez *a)
+{
+ TCGv t0, t1;
+
+ t0 = tcg_temp_new();
+ t1 = tcg_const_i64(0);
+
+ if (a->rj != 0) {
+ gen_load_gpr(t0, a->rj);
+ tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1);
+ ctx->hflags |= LOONGARCH_HFLAG_BC;
+ }
+ ctx->btarget = ctx->base.pc_next + (a->offs21 << 2);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+
+ return true;
+}
+
+static bool trans_bceqz(DisasContext *ctx, arg_bceqz *a)
+{
+ TCGv t0, t1;
+ TCGv_i32 cj;
+
+ cj = tcg_const_i32(a->cj);
+ t0 = tcg_temp_new();
+ t1 = tcg_const_i64(0);
+
+ gen_helper_movcf2reg(t0, cpu_env, cj);
+ tcg_gen_setcond_tl(TCG_COND_EQ, bcond, t0, t1);
+ ctx->hflags |= LOONGARCH_HFLAG_BC;
+ ctx->btarget = ctx->base.pc_next + (a->offs21 << 2);
+
+ tcg_temp_free_i32(cj);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+
+ return true;
+}
+
+static bool trans_bcnez(DisasContext *ctx, arg_bcnez *a)
+{
+ TCGv t0, t1;
+ TCGv_i32 cj;
+
+ cj = tcg_const_i32(a->cj);
+ t0 = tcg_temp_new();
+ t1 = tcg_const_i64(0);
+
+ gen_helper_movcf2reg(t0, cpu_env, cj);
+ tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1);
+ ctx->hflags |= LOONGARCH_HFLAG_BC;
+ ctx->btarget = ctx->base.pc_next + (a->offs21 << 2);
+
+ tcg_temp_free_i32(cj);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+
+ return true;
+}
+
+static bool trans_b(DisasContext *ctx, arg_b *a)
+{
+ ctx->hflags |= LOONGARCH_HFLAG_B;
+ ctx->btarget = ctx->base.pc_next + (a->offs << 2);
+
+ return true;
+}
+
+static bool trans_bl(DisasContext *ctx, arg_bl *a)
+{
+ ctx->btarget = ctx->base.pc_next + (a->offs << 2);
+ tcg_gen_movi_tl(cpu_gpr[1], ctx->base.pc_next + 4);
+ ctx->hflags |= LOONGARCH_HFLAG_B;
+ gen_branch(ctx, 4);
+
+ return true;
+}
+
+static bool trans_blt(DisasContext *ctx, arg_blt *a)
+{
+ TCGv t0, t1;
+
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+
+ gen_load_gpr(t0, a->rj);
+ gen_load_gpr(t1, a->rd);
+
+ tcg_gen_setcond_tl(TCG_COND_LT, bcond, t0, t1);
+ ctx->hflags |= LOONGARCH_HFLAG_BC;
+ ctx->btarget = ctx->base.pc_next + (a->offs16 << 2);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+
+ return true;
+}
+
+static bool trans_bge(DisasContext *ctx, arg_bge *a)
+{
+ TCGv t0, t1;
+
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+
+ gen_load_gpr(t0, a->rj);
+ gen_load_gpr(t1, a->rd);
+
+ tcg_gen_setcond_tl(TCG_COND_GE, bcond, t0, t1);
+ ctx->hflags |= LOONGARCH_HFLAG_BC;
+ ctx->btarget = ctx->base.pc_next + (a->offs16 << 2);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+
+ return true;
+}
+
+static bool trans_bltu(DisasContext *ctx, arg_bltu *a)
+{
+ TCGv t0, t1;
+
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+
+ gen_load_gpr(t0, a->rj);
+ gen_load_gpr(t1, a->rd);
+
+ tcg_gen_setcond_tl(TCG_COND_LTU, bcond, t0, t1);
+ ctx->hflags |= LOONGARCH_HFLAG_BC;
+ ctx->btarget = ctx->base.pc_next + (a->offs16 << 2);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+
+ return true;
+}
+
+static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
+{
+ TCGv t0, t1;
+
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+
+ gen_load_gpr(t0, a->rj);
+ gen_load_gpr(t1, a->rd);
+
+ tcg_gen_setcond_tl(TCG_COND_GEU, bcond, t0, t1);
+ ctx->hflags |= LOONGARCH_HFLAG_BC;
+ ctx->btarget = ctx->base.pc_next + (a->offs16 << 2);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+
+ return true;
+}
+
+static bool trans_beq(DisasContext *ctx, arg_beq *a)
+{
+ TCGv t0, t1;
+ int bcond_flag = 0;
+
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+
+ if (a->rj != a->rd) {
+ gen_load_gpr(t0, a->rj);
+ gen_load_gpr(t1, a->rd);
+ bcond_flag = 1;
+ }
+
+ if (bcond_flag == 0) {
+ ctx->hflags |= LOONGARCH_HFLAG_B;
+ } else {
+ tcg_gen_setcond_tl(TCG_COND_EQ, bcond, t0, t1);
+ ctx->hflags |= LOONGARCH_HFLAG_BC;
+ }
+ ctx->btarget = ctx->base.pc_next + (a->offs16 << 2);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+
+ return true;
+}
+
+static bool trans_bne(DisasContext *ctx, arg_bne *a)
+{
+ TCGv t0, t1;
+
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+
+ if (a->rj != a->rd) {
+ gen_load_gpr(t0, a->rj);
+ gen_load_gpr(t1, a->rd);
+ tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1);
+ ctx->hflags |= LOONGARCH_HFLAG_BC;
+ }
+ ctx->btarget = ctx->base.pc_next + (a->offs16 << 2);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+
+ return true;
+}
+
+static bool trans_jirl(DisasContext *ctx, arg_jirl *a)
+{
+ gen_base_offset_addr(btarget, a->rj, a->offs16 << 2);
+ if (a->rd != 0) {
+ tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->base.pc_next + 4);
+ }
+ ctx->hflags |= LOONGARCH_HFLAG_BR;
+ gen_branch(ctx, 4);
+
+ return true;
+}
--
1.8.3.1
