On Sat, 17 Jul 2021 at 23:18, Richard Henderson <richard.hender...@linaro.org> wrote: > > The actual number of bytes advanced need not be 100% exact, > but we should not cross a page when the insn would not. > > If rvc is enabled, the minimum insn size is 2. > > Signed-off-by: Richard Henderson <richard.hender...@linaro.org> > --- > target/riscv/translate.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index deda0c8a44..5527f37ada 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -973,7 +973,7 @@ static bool riscv_tr_breakpoint_check(DisasContextBase > *dcbase, CPUState *cpu, > [tb->pc, tb->pc + tb->size) in order to for it to be > properly cleared -- thus we increment the PC here so that > the logic setting tb->size below does the right thing. */ > - ctx->base.pc_next += 4; > + ctx->base.pc_next += 2; > return true; > }
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> (What goes wrong if we just say "always use a TB size of 1 regardless of target arch" rather than having the arch return the worst case minimum insn length?) thanks -- PMM
