On Sat, 17 Jul 2021 at 23:18, Richard Henderson <richard.hender...@linaro.org> wrote: > > The actual number of bytes advanced need not be 100% exact, > but we should not cross a page when the insn would not. > > If mips16 or mips32e are enabled, the minimum insn size is 2. > > Signed-off-by: Richard Henderson <richard.hender...@linaro.org> > --- > target/mips/tcg/translate.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c > index fd980ea966..ef00fbd2ac 100644 > --- a/target/mips/tcg/translate.c > +++ b/target/mips/tcg/translate.c > @@ -16192,7 +16192,7 @@ static bool mips_tr_breakpoint_check(DisasContextBase > *dcbase, CPUState *cs, > * properly cleared -- thus we increment the PC here so that > * the logic setting tb->size below does the right thing. > */ > - ctx->base.pc_next += 4; > + ctx->base.pc_next += 2; > return true; > } >
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> thanks -- PMM
