On Sat, 17 Jul 2021 at 23:18, Richard Henderson <richard.hender...@linaro.org> wrote: > > Since 0b00b0c1e05b, tb->size must not be zero. > Advance pc so that the breakpoint covers the insn at the bp. > > Signed-off-by: Richard Henderson <richard.hender...@linaro.org> > --- > target/avr/translate.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/avr/translate.c b/target/avr/translate.c > index 8237a03c23..d768063d65 100644 > --- a/target/avr/translate.c > +++ b/target/avr/translate.c > @@ -2950,6 +2950,7 @@ static bool avr_tr_breakpoint_check(DisasContextBase > *dcbase, CPUState *cs, > DisasContext *ctx = container_of(dcbase, DisasContext, base); > > gen_breakpoint(ctx); > + ctx->base.pc_next += 2; /* advance by minimum insn len so tb->size != 0 > */ > return true; > }
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> thanks -- PMM
