Re: [PATCH v1 1/5] target/riscv: Expose interrupt pending bits as GPIO lines

[Bin Meng]

On Fri, Jul 9, 2021 at 11:30 AM Alistair Francis
<alistair.fran...@wdc.com> wrote:
>
> Expose the 12 interrupt pending bits in MIP as GPIO lines.
>
> Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
> ---
>  target/riscv/cpu.c | 30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
>

Reviewed-by: Bin Meng <bmeng...@gmail.com>