On 7/9/21 5:31 AM, Alistair Francis wrote: > Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V > CPU GPIO lines to set the external MIP bits. > > Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> > --- > include/hw/intc/sifive_plic.h | 4 ++++ > hw/intc/sifive_plic.c | 38 ++++++++++++++++++++++++++++------- > hw/riscv/microchip_pfsoc.c | 2 +- > hw/riscv/shakti_c.c | 3 ++- > hw/riscv/sifive_e.c | 2 +- > hw/riscv/sifive_u.c | 2 +- > hw/riscv/virt.c | 3 ++- > 7 files changed, 42 insertions(+), 12 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
