V2:
- Renmae the enum
- Rebase on master
- Fix a few incorrect returns
Alistair Francis (5):
target/riscv: Convert the RISC-V exceptions to an enum
target/riscv: Use the RISCVException enum for CSR predicates
target/riscv: Fix 32-bit HS mode access permissions
target/riscv: Use the RISCVException enum for CSR operations
target/riscv: Use RISCVException enum for CSR access
target/riscv/cpu.h | 28 +-
target/riscv/cpu_bits.h | 44 +--
target/riscv/cpu.c | 2 +-
target/riscv/cpu_helper.c | 4 +-
target/riscv/csr.c | 740 ++++++++++++++++++++++----------------
target/riscv/gdbstub.c | 8 +-
target/riscv/op_helper.c | 18 +-
7 files changed, 492 insertions(+), 352 deletions(-)
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2.31.0
