restrict zcr_el1, zcr_el2, zcr_no_el2, zcr_el3 reginfo,
as well as related SVE functions.
Signed-off-by: Claudio Fontana <cfont...@suse.de>
---
target/arm/cpu.h | 7 -------
target/arm/tcg/cpu-sve.h | 7 +++++++
linux-user/syscall.c | 4 ++++
target/arm/cpu-exceptions-aa64.c | 1 +
target/arm/tcg/cpregs.c | 10 ++++++++--
target/arm/tcg/helper-a64.c | 1 +
target/arm/tcg/helper.c | 1 +
7 files changed, 22 insertions(+), 9 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index ba41053111..662ac5ee62 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1047,9 +1047,6 @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f,
CPUState *cs,
#ifdef TARGET_AARCH64
int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
-void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
-void aarch64_sve_change_el(CPUARMState *env, int old_el,
- int new_el, bool el0_a64);
static inline bool is_a64(CPUARMState *env)
{
@@ -1081,10 +1078,6 @@ static inline uint64_t *sve_bswap64(uint64_t *dst,
uint64_t *src, int nr)
}
#else
-static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { }
-static inline void aarch64_sve_change_el(CPUARMState *env, int o,
- int n, bool a)
-{ }
#define is_a64(env) (false)
diff --git a/target/arm/tcg/cpu-sve.h b/target/arm/tcg/cpu-sve.h
index 49f6ad021b..fc53b26998 100644
--- a/target/arm/tcg/cpu-sve.h
+++ b/target/arm/tcg/cpu-sve.h
@@ -21,4 +21,11 @@ uint32_t tcg_cpu_sve_disable_lens(unsigned long *sve_vq_map,
bool tcg_cpu_sve_validate_lens(unsigned long *sve_vq_map, uint32_t max_vq,
Error **errp);
+/* tcg/helper.c */
+
+void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
+
+void aarch64_sve_change_el(CPUARMState *env, int old_el,
+ int new_el, bool el0_a64);
+
#endif /* TCG_CPU_SVE_H */
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 1e508576c7..9dbfe6fdc0 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -134,6 +134,10 @@
#include "fd-trans.h"
#include "tcg/tcg.h"
+#ifdef TARGET_AARCH64
+#include "tcg/cpu-sve.h"
+#endif /* TARGET_AARCH64 */
+
#ifndef CLONE_IO
#define CLONE_IO 0x80000000 /* Clone io context */
#endif
diff --git a/target/arm/cpu-exceptions-aa64.c b/target/arm/cpu-exceptions-aa64.c
index 5ac52d0a58..ac42cb8626 100644
--- a/target/arm/cpu-exceptions-aa64.c
+++ b/target/arm/cpu-exceptions-aa64.c
@@ -21,6 +21,7 @@
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "cpu.h"
+#include "tcg/cpu-sve.h"
#include "internals.h"
#include "sysemu/tcg.h"
diff --git a/target/arm/tcg/cpregs.c b/target/arm/tcg/cpregs.c
index a72c9378b2..7376fad2eb 100644
--- a/target/arm/tcg/cpregs.c
+++ b/target/arm/tcg/cpregs.c
@@ -5792,6 +5792,10 @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
REGINFO_SENTINEL
};
+#ifdef TARGET_AARCH64
+
+#include "tcg/cpu-sve.h"
+
static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -5844,6 +5848,8 @@ static const ARMCPRegInfo zcr_el3_reginfo = {
.writefn = zcr_write, .raw_writefn = raw_write
};
+#endif /* TARGET_AARCH64 */
+
static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -7573,6 +7579,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
define_arm_cp_regs(cpu, vhe_reginfo);
}
+#ifdef TARGET_AARCH64
if (cpu_isar_feature(aa64_sve, cpu)) {
define_one_arm_cp_reg(cpu, &zcr_el1_reginfo);
if (arm_feature(env, ARM_FEATURE_EL2)) {
@@ -7585,7 +7592,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}
}
-#ifdef TARGET_AARCH64
if (cpu_isar_feature(aa64_pauth, cpu)) {
define_arm_cp_regs(cpu, pauth_reginfo);
}
@@ -7615,7 +7621,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
define_arm_cp_regs(cpu, mte_tco_ro_reginfo);
define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
}
-#endif
+#endif /* TARGET_AARCH64 */
if (cpu_isar_feature(any_predinv, cpu)) {
define_arm_cp_regs(cpu, predinv_reginfo);
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
index b75ce80473..157a5bb549 100644
--- a/target/arm/tcg/helper-a64.c
+++ b/target/arm/tcg/helper-a64.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "cpu.h"
+#include "tcg/cpu-sve.h"
#include "cpu-exceptions-aa64.h"
#include "exec/gdbstub.h"
#include "exec/helper-proto.h"
diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c
index 493f5b066d..2e8b122cc4 100644
--- a/target/arm/tcg/helper.c
+++ b/target/arm/tcg/helper.c
@@ -16,6 +16,7 @@
#include <zlib.h> /* For crc32 */
#include "arm_ldst.h"
#include "cpu-mmu.h"
+#include "tcg/cpu-sve.h"
#include "cpregs.h"
#include "tcg-cpu.h"
--
2.26.2
