On Wed, Mar 03, 2021 at 18:06:46 +0000, Peter Maydell wrote: > On Wed, 3 Mar 2021 at 17:48, Leif Lindholm <l...@nuviainc.com> wrote: > > It would be good if we could get 6.0 closer to SBSA compliance. > > How far away are we at the moment ? > > > Would it be worth the effort to make this controllable per cpu model? > > I don't have a strong opinion on whether we should, but if we do then the > right way to implement that would be to have the PMCR reset value > as a reset_pmcr_el0 field in struct ARMCPU (like the existing reset_fpsid, > reset_sctlr, etc) that gets set per-CPU to whatever the CPU's value for > it is; and then instead of using a PMCR_NUM_COUNTERS value, > extract the PMCR.N field when needed. The hardest part would be > going through all the CPU TRMs to find out the correct reset value.
That makes sense. I guess we could also phase the transition by using the default value if zero? Regards, Leif
