This implements the CXL device status registers from 8.2.8.3.1 in the
CXL 2.0 specification. It is capability ID 0001h.
v2: Use the reg alignment helper (Jonathan)
Add stubbed device_reg_init_common() (Ben)
Signed-off-by: Ben Widawsky <ben.widaw...@intel.com>
---
hw/cxl/cxl-device-utils.c | 38 ++++++++++++++++++++++++++++++++++++-
include/hw/cxl/cxl_device.h | 16 ++++++++++++++++
2 files changed, 53 insertions(+), 1 deletion(-)
diff --git a/hw/cxl/cxl-device-utils.c b/hw/cxl/cxl-device-utils.c
index d1b1371e66..b86e5466bd 100644
--- a/hw/cxl/cxl-device-utils.c
+++ b/hw/cxl/cxl-device-utils.c
@@ -32,6 +32,32 @@ static uint64_t caps_reg_read(void *opaque, hwaddr offset,
unsigned size)
return ldn_le_p(cxl_dstate->caps_reg_state + offset, size);
}
+static uint64_t dev_reg_read(void *opaque, hwaddr offset, unsigned size)
+{
+ uint64_t retval = 0;
+
+ if (cxl_device_check_register_alignment(offset, size)) {
+ qemu_log_mask(LOG_UNIMP, "Unaligned register read\n");
+ return 0;
+ }
+
+ return ldn_le_p(&retval, size);
+}
+
+static const MemoryRegionOps dev_ops = {
+ .read = dev_reg_read,
+ .write = NULL,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 8,
+ },
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 8,
+ },
+};
+
static const MemoryRegionOps caps_ops = {
.read = caps_reg_read,
.write = NULL,
@@ -55,18 +81,28 @@ void cxl_device_register_block_init(Object *obj,
CXLDeviceState *cxl_dstate)
memory_region_init_io(&cxl_dstate->caps, obj, &caps_ops, cxl_dstate,
"cap-array", CXL_DEVICE_REGISTERS_OFFSET - 0);
+ memory_region_init_io(&cxl_dstate->device, obj, &dev_ops, cxl_dstate,
+ "device-status", CXL_DEVICE_REGISTERS_LENGTH);
memory_region_add_subregion(&cxl_dstate->device_registers, 0,
&cxl_dstate->caps);
+ memory_region_add_subregion(&cxl_dstate->device_registers,
+ CXL_DEVICE_REGISTERS_OFFSET,
+ &cxl_dstate->device);
}
+static void device_reg_init_common(CXLDeviceState *cxl_dstate) { }
+
void cxl_device_register_init_common(CXLDeviceState *cxl_dstate)
{
uint32_t *cap_hdrs = cxl_dstate->caps_reg_state32;
- const int cap_count = 0;
+ const int cap_count = 1;
/* CXL Device Capabilities Array Register */
ARRAY_FIELD_DP32(cap_hdrs, CXL_DEV_CAP_ARRAY, CAP_ID, 0);
ARRAY_FIELD_DP32(cap_hdrs, CXL_DEV_CAP_ARRAY, CAP_VERSION, 1);
ARRAY_FIELD_DP32(cap_hdrs, CXL_DEV_CAP_ARRAY2, CAP_COUNT, cap_count);
+
+ cxl_device_cap_init(cxl_dstate, DEVICE, 1);
+ device_reg_init_common(cxl_dstate);
}
diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
index 38af43c1a6..3380fc9e7a 100644
--- a/include/hw/cxl/cxl_device.h
+++ b/include/hw/cxl/cxl_device.h
@@ -122,6 +122,22 @@ CXL_DEVICE_CAPABILITY_HEADER_REGISTER(DEVICE,
CXL_DEVICE_CAP_HDR1_OFFSET)
CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MAILBOX, CXL_DEVICE_CAP_HDR1_OFFSET + \
CXL_DEVICE_CAP_REG_SIZE)
+#define cxl_device_cap_init(dstate, reg, cap_id)
\
+ do {
\
+ uint32_t *cap_hdrs = dstate->caps_reg_state32;
\
+ int which = R_CXL_DEV_##reg##_CAP_HDR0;
\
+ cap_hdrs[which] =
\
+ FIELD_DP32(cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0, CAP_ID,
cap_id); \
+ cap_hdrs[which] = FIELD_DP32(
\
+ cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0, CAP_VERSION, 1);
\
+ cap_hdrs[which + 1] =
\
+ FIELD_DP32(cap_hdrs[which + 1], CXL_DEV_##reg##_CAP_HDR1,
\
+ CAP_OFFSET, CXL_##reg##_REGISTERS_OFFSET);
\
+ cap_hdrs[which + 2] =
\
+ FIELD_DP32(cap_hdrs[which + 2], CXL_DEV_##reg##_CAP_HDR2,
\
+ CAP_LENGTH, CXL_##reg##_REGISTERS_LENGTH);
\
+ } while (0)
+
REG32(CXL_DEV_MAILBOX_CAP, 0)
FIELD(CXL_DEV_MAILBOX_CAP, PAYLOAD_SIZE, 0, 5)
FIELD(CXL_DEV_MAILBOX_CAP, INT_CAP, 5, 1)
--
2.30.0
