On 11/19/20 3:56 PM, Peter Maydell wrote: > In v8.0M, on exception entry the registers R0-R3, R12, APSR and EPSR > are zeroed for an exception taken to Non-secure state; for an > exception taken to Secure state they become UNKNOWN, and we chose to > leave them at their previous values. > > In v8.1M the behaviour is specified more tightly and these registers > are always zeroed regardless of the security state that the exception > targets (see rule R_KPZV). Implement this. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > --- > target/arm/m_helper.c | 16 ++++++++++++---- > 1 file changed, 12 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
