On 11/19/20 3:55 PM, Peter Maydell wrote: > v8.1M defines a new FP system register FPSCR_nzcvqc; this behaves > like the existing FPSCR, except that it reads and writes only bits > [31:27] of the FPSCR (the N, Z, C, V and QC flag bits). (Unlike the > FPSCR, the special case for Rt=15 of writing the CPSR.NZCV is not > permitted.) > > Implement the register. Since we don't yet implement MVE, we handle > the QC bit as RES0, with todo comments for where we will need to add > support later. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > --- > target/arm/cpu.h | 13 +++++++++++++ > target/arm/translate-vfp.c.inc | 27 +++++++++++++++++++++++++++ > 2 files changed, 40 insertions(+)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
