Hi Philippe,
-----Original Message-----
From: Philippe Mathieu-Daudé <phi...@redhat.com>
Sent: Monday, November 9, 2020 6:21 AM
To: Joe Komlodi <koml...@xilinx.com>; qemu-devel@nongnu.org; Cédric Le Goater
<c...@kaod.org>; Edgar Iglesias <edg...@xilinx.com>
Cc: Francisco Eduardo Iglesias <figle...@xilinx.com>; alist...@alistair23.me;
philippe.mathieu.da...@gmail.com; qemu-bl...@nongnu.org; mre...@redhat.com
Subject: Re: [PATCH v3 1/3] hw/block/m25p80: Fix Numonyx NVCFG DIO and QIO bit
polarity
On 11/6/20 2:32 AM, Joe Komlodi wrote:
> QIO and DIO modes should be enabled when the bits in NVCFG are set to 0.
> This matches the behavior of the other bits in the NVCFG register.
Is this material for the 5.2 release?
[Joe] If possible, yeah. Otherwise if it's too late for 5.2 I have no problems
pushing it to a later release.
Thanks!
Joe
>
> Signed-off-by: Joe Komlodi <koml...@xilinx.com>
> ---
> hw/block/m25p80.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index
> 483925f..4255a6a 100644
> --- a/hw/block/m25p80.c
> +++ b/hw/block/m25p80.c
> @@ -783,10 +783,10 @@ static void reset_memory(Flash *s)
> s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGTH_DEF;
> s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR;
> s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED;
> - if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) {
> + if (!(s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK)) {
> s->enh_volatile_cfg |= EVCFG_DUAL_IO_ENABLED;
> }
> - if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) {
> + if (!(s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK)) {
> s->enh_volatile_cfg |= EVCFG_QUAD_IO_ENABLED;
> }
> if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) {
>
