QIO and DIO modes should be enabled when the bits in NVCFG are set to 0.
This matches the behavior of the other bits in the NVCFG register.
Signed-off-by: Joe Komlodi <koml...@xilinx.com>
---
hw/block/m25p80.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index 483925f..4255a6a 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -783,10 +783,10 @@ static void reset_memory(Flash *s)
s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGTH_DEF;
s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR;
s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED;
- if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) {
+ if (!(s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK)) {
s->enh_volatile_cfg |= EVCFG_DUAL_IO_ENABLED;
}
- if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) {
+ if (!(s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK)) {
s->enh_volatile_cfg |= EVCFG_QUAD_IO_ENABLED;
}
if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) {
--
2.7.4
