From: Laurent Vivier <laur...@vivier.eu>
This patch modify "mull" to support 64bit result, and to update
CC on 32bit operands.
Signed-off-by: Andreas Schwab <sch...@linux-m68k.org>
Signed-off-by: Laurent Vivier <laur...@vivier.eu>
---
target-m68k/helpers.h | 4 +++
target-m68k/op_helper.c | 66 +++++++++++++++++++++++++++++++++++++++++++++++
target-m68k/translate.c | 36 +++++++++++++++++++++----
3 files changed, 100 insertions(+), 6 deletions(-)
diff --git a/target-m68k/helpers.h b/target-m68k/helpers.h
index a158aee..ca2bf82 100644
--- a/target-m68k/helpers.h
+++ b/target-m68k/helpers.h
@@ -7,6 +7,10 @@ DEF_HELPER_2(divu, void, env, i32)
DEF_HELPER_2(divs, void, env, i32)
DEF_HELPER_1(divu64, void, env)
DEF_HELPER_1(divs64, void, env)
+DEF_HELPER_3(mulu32_cc, i32, env, i32, i32)
+DEF_HELPER_3(muls32_cc, i32, env, i32, i32)
+DEF_HELPER_3(mulu64, i32, env, i32, i32)
+DEF_HELPER_3(muls64, i32, env, i32, i32)
DEF_HELPER_3(addx_cc, i32, env, i32, i32)
DEF_HELPER_3(subx_cc, i32, env, i32, i32)
DEF_HELPER_3(shl_cc, i32, env, i32, i32)
diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c
index 1bffe5d..a6c8148 100644
--- a/target-m68k/op_helper.c
+++ b/target-m68k/op_helper.c
@@ -318,3 +318,69 @@ void HELPER(divs64)(CPUState *env)
}
env->cc_dest = flags;
}
+
+uint32_t HELPER(mulu32_cc)(CPUState *env, uint32_t op1, uint32_t op2)
+{
+ uint64_t res = (uint32_t)op1 * op2;
+ uint32_t flags;
+
+ flags = 0;
+ if (res >> 32)
+ flags |= CCF_V;
+ if ((uint32_t)res == 0)
+ flags |= CCF_Z;
+ if ((int32_t)res < 0)
+ flags |= CCF_N;
+ env->cc_dest = flags;
+
+ return res;
+}
+
+uint32_t HELPER(muls32_cc)(CPUState *env, uint32_t op1, uint32_t op2)
+{
+ int64_t res = (int32_t)op1 * (int32_t)op2;
+ uint32_t flags;
+
+ flags = 0;
+ if (res != (int64_t)(int32_t)res)
+ flags |= CCF_V;
+ if ((uint32_t)res == 0)
+ flags |= CCF_Z;
+ if ((int32_t)res < 0)
+ flags |= CCF_N;
+ env->cc_dest = flags;
+
+ return res;
+}
+
+uint32_t HELPER(mulu64)(CPUState *env, uint32_t op1, uint32_t op2)
+{
+ uint64_t res = (uint64_t)op1 * op2;
+ uint32_t flags;
+
+ env->quadh = res >> 32;
+ flags = 0;
+ if (res == 0)
+ flags |= CCF_Z;
+ if ((int64_t)res < 0)
+ flags |= CCF_N;
+ env->cc_dest = flags;
+
+ return res;
+}
+
+uint32_t HELPER(muls64)(CPUState *env, uint32_t op1, uint32_t op2)
+{
+ int64_t res = (uint64_t)(int32_t)op1 * (int32_t)op2;
+ uint32_t flags;
+
+ env->quadh = res >> 32;
+ flags = 0;
+ if (res == 0)
+ flags |= CCF_Z;
+ if (res < 0)
+ flags |= CCF_N;
+ env->cc_dest = flags;
+
+ return res;
+}
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 1d84081..74faabf 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -1631,22 +1631,45 @@ DISAS_INSN(mull)
TCGv reg;
TCGv src1;
TCGv dest;
+ TCGv regh;
/* The upper 32 bits of the product are discarded, so
muls.l and mulu.l are functionally equivalent. */
ext = lduw_code(s->pc);
s->pc += 2;
- if (ext & 0x87ff) {
- gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
- return;
+ if (ext & 0x400) {
+ if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) {
+ gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
+ return;
+ }
+ reg = DREG(ext, 12);
+ regh = DREG(ext, 0);
+ SRC_EA(src1, OS_LONG, 0, NULL);
+ dest = tcg_temp_new();
+ if (ext & 0x800)
+ gen_helper_muls64(dest, cpu_env, src1, reg);
+ else
+ gen_helper_mulu64(dest, cpu_env, src1, reg);
+ tcg_gen_mov_i32(reg, dest);
+ tcg_gen_mov_i32(regh, QREG_QUADH);
+ s->cc_op = CC_OP_FLAGS;
+ return;
}
reg = DREG(ext, 12);
SRC_EA(src1, OS_LONG, 0, NULL);
dest = tcg_temp_new();
- tcg_gen_mul_i32(dest, src1, reg);
+ if (m68k_feature(s->env, M68K_FEATURE_M68000)) {
+ if (ext & 0x800)
+ gen_helper_muls32_cc(dest, cpu_env, src1, reg);
+ else
+ gen_helper_mulu32_cc(dest, cpu_env, src1, reg);
+ s->cc_op = CC_OP_FLAGS;
+ } else {
+ tcg_gen_mul_i32(dest, src1, reg);
+ /* Unlike m68k, coldfire always clears the overflow bit. */
+ gen_logic_cc(s, dest);
+ }
tcg_gen_mov_i32(reg, dest);
- /* Unlike m68k, coldfire always clears the overflow bit. */
- gen_logic_cc(s, dest);
}
DISAS_INSN(link)
@@ -3028,6 +3051,7 @@ void register_m68k_insns (CPUM68KState *env)
INSN(illegal, 4afc, ffff, CF_ISA_A);
INSN(illegal, 4afc, ffff, M68000);
INSN(mull, 4c00, ffc0, CF_ISA_A);
+ INSN(mull, 4c00, ffc0, LONG_MULDIV);
INSN(divl, 4c40, ffc0, CF_ISA_A);
INSN(divl, 4c40, ffc0, LONG_MULDIV);
INSN(sats, 4c80, fff8, CF_ISA_B);
--
1.7.2.3
