From: Laurent Vivier <laur...@vivier.eu>
Signed-off-by: Laurent Vivier <laur...@vivier.eu>
---
target-m68k/helper.c | 48 ++++++++++++++++++++++++++++++++++++++-
target-m68k/helpers.h | 4 ++-
target-m68k/translate.c | 58 +++++++++++++++++++++++++++++++++++++++++++---
3 files changed, 104 insertions(+), 6 deletions(-)
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index 1c3dd72..60021d7 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -596,7 +596,53 @@ uint32_t HELPER(subx_cc)(CPUState *env, uint32_t op1,
uint32_t op2)
return res;
}
-uint32_t HELPER(addx_cc)(CPUState *env, uint32_t op1, uint32_t op2)
+uint32_t HELPER(addx8_cc)(CPUState *env, uint32_t op1, uint32_t op2)
+{
+ uint8_t res;
+ uint32_t old_flags;
+
+ old_flags = env->cc_dest;
+ if (env->cc_x) {
+ res = (uint8_t)op1 + (uint8_t)op2 + 1;
+ env->cc_x = (res <= (uint8_t)op2);
+ env->cc_op = CC_OP_ADDXB;
+ } else {
+ res = (uint8_t)op1 + (uint8_t)op2;
+ env->cc_x = (res < (uint8_t)op2);
+ env->cc_op = CC_OP_ADDB;
+ }
+ env->cc_dest = res;
+ env->cc_src = (uint8_t)op2;
+ cpu_m68k_flush_flags(env, env->cc_op);
+ /* !Z is sticky. */
+ env->cc_dest &= (old_flags | ~CCF_Z);
+ return (op1 & 0xffffff00) | res;
+}
+
+uint32_t HELPER(addx16_cc)(CPUState *env, uint32_t op1, uint32_t op2)
+{
+ uint16_t res;
+ uint32_t old_flags;
+
+ old_flags = env->cc_dest;
+ if (env->cc_x) {
+ res = (uint16_t)op1 + (uint16_t)op2 + 1;
+ env->cc_x = (res <= (uint16_t)op2);
+ env->cc_op = CC_OP_ADDXW;
+ } else {
+ res = (uint16_t)op1 + (uint16_t)op2;
+ env->cc_x = (res < (uint16_t)op2);
+ env->cc_op = CC_OP_ADDW;
+ }
+ env->cc_dest = res;
+ env->cc_src = (uint16_t)op2;
+ cpu_m68k_flush_flags(env, env->cc_op);
+ /* !Z is sticky. */
+ env->cc_dest &= (old_flags | ~CCF_Z);
+ return (op1 & 0xffff0000) | res;
+}
+
+uint32_t HELPER(addx32_cc)(CPUState *env, uint32_t op1, uint32_t op2)
{
uint32_t res;
uint32_t old_flags;
diff --git a/target-m68k/helpers.h b/target-m68k/helpers.h
index 2e5b8f8..11f1c0b 100644
--- a/target-m68k/helpers.h
+++ b/target-m68k/helpers.h
@@ -14,7 +14,9 @@ DEF_HELPER_3(mulu32_cc, i32, env, i32, i32)
DEF_HELPER_3(muls32_cc, i32, env, i32, i32)
DEF_HELPER_3(mulu64, i32, env, i32, i32)
DEF_HELPER_3(muls64, i32, env, i32, i32)
-DEF_HELPER_3(addx_cc, i32, env, i32, i32)
+DEF_HELPER_3(addx8_cc, i32, env, i32, i32)
+DEF_HELPER_3(addx16_cc, i32, env, i32, i32)
+DEF_HELPER_3(addx32_cc, i32, env, i32, i32)
DEF_HELPER_3(subx_cc, i32, env, i32, i32)
DEF_HELPER_3(shl8_cc, i32, env, i32, i32)
DEF_HELPER_3(shl16_cc, i32, env, i32, i32)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index f743fd2..f2d0fae 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -2160,16 +2160,65 @@ DISAS_INSN(adda)
tcg_gen_add_i32(reg, reg, src);
}
-DISAS_INSN(addx)
+DISAS_INSN(addx_reg)
{
TCGv reg;
TCGv src;
+ int opsize;
+
+ opsize = insn_opsize(insn, 6);
gen_flush_flags(s);
reg = DREG(insn, 9);
src = DREG(insn, 0);
- gen_helper_addx_cc(reg, cpu_env, reg, src);
+ switch(opsize) {
+ case OS_BYTE:
+ gen_helper_addx8_cc(reg, cpu_env, reg, src);
+ break;
+ case OS_WORD:
+ gen_helper_addx16_cc(reg, cpu_env, reg, src);
+ break;
+ case OS_LONG:
+ gen_helper_addx32_cc(reg, cpu_env, reg, src);
+ break;
+ }
+ s->cc_op = CC_OP_FLAGS;
+}
+
+DISAS_INSN(addx_mem)
+{
+ TCGv src;
+ TCGv addr_src;
+ TCGv reg;
+ TCGv addr_reg;
+ int opsize;
+
+ opsize = insn_opsize(insn, 6);
+
+ gen_flush_flags(s);
+
+ addr_src = AREG(insn, 0);
+ tcg_gen_subi_i32(addr_src, addr_src, opsize);
+ src = gen_load(s, opsize, addr_src, 0);
+
+ addr_reg = AREG(insn, 9);
+ tcg_gen_subi_i32(addr_reg, addr_reg, opsize);
+ reg = gen_load(s, opsize, addr_reg, 0);
+
+ switch(opsize) {
+ case OS_BYTE:
+ gen_helper_addx8_cc(reg, cpu_env, reg, src);
+ break;
+ case OS_WORD:
+ gen_helper_addx16_cc(reg, cpu_env, reg, src);
+ break;
+ case OS_LONG:
+ gen_helper_addx32_cc(reg, cpu_env, reg, src);
+ break;
+ }
s->cc_op = CC_OP_FLAGS;
+
+ gen_store(s, opsize, addr_reg, reg);
}
/* TODO: This could be implemented without helper functions. */
@@ -4004,8 +4053,9 @@ void register_m68k_insns (CPUM68KState *env)
INSN(addsub, d000, f000, CF_ISA_A);
INSN(addsub, d000, f000, M68000);
INSN(undef, d0c0, f0c0, CF_ISA_A);
- INSN(addx, d180, f1f8, CF_ISA_A);
- INSN(addx, d100, f138, M68000);
+ INSN(addx_reg, d180, f1f8, CF_ISA_A);
+ INSN(addx_reg, d100, f138, M68000);
+ INSN(addx_mem, d108, f138, M68000);
INSN(adda, d1c0, f1c0, CF_ISA_A);
INSN(adda, d0c0, f0c0, M68000);
INSN(shift_im, e080, f0f0, CF_ISA_A);
--
1.7.2.3
