Hi Philippe, As the label says, these are the host FIFOs. The controller has a mode where DMA is not used, and instead the driver reads the data directly from the FIFOs. I have not implemented this feature yet, but as I recall one of the BSDs uses this in their driver, so I plan to implement this in the future.
Thanks, Paul On Mon, Apr 20, 2020 at 12:25 AM Philippe Mathieu-Daudé <f4...@amsat.org> wrote: > On 3/29/20 1:17 AM, Paul Zimmerman wrote: > > Add the dwc-hsotg (dwc2) USB host controller emulation code. > > Based on hw/usb/hcd-ehci.c and hw/usb/hcd-ohci.c. > > > > Note that to use this with the dwc-otg driver in the Raspbian > > kernel, you must pass the option "dwc_otg.fiq_fsm_enable=0" on > > the kernel command line. > > > > Emulation of slave mode and of descriptor-DMA mode has not been > > implemented yet. These modes are seldom used. > > > > I have used some on-line sources of information while developing > > this emulation, including: > > > > http://www.capital-micro.com/PDF/CME-M7_Family_User_Guide_EN.pdf > > has a pretty complete description of the controller starting on > > page 370. > > > > > https://sourceforge.net/p/wive-ng/wive-ng-mt/ci/master/tree/docs/DataSheets/RT3050_5x_V2.0_081408_0902.pdf > > has a description of the controller registers starting on page > > 130. > > > > Signed-off-by: Paul Zimmerman <pauld...@gmail.com> > > --- > > hw/usb/hcd-dwc2.c | 1301 +++++++++++++++++++++++++++++++++++++++++++ > > hw/usb/trace-events | 47 ++ > > 2 files changed, 1348 insertions(+) > > create mode 100644 hw/usb/hcd-dwc2.c > [...] > > +static void dwc2_hreg2_write(void *ptr, hwaddr addr, uint64_t val, > > + unsigned size) > > +{ > > + uint64_t orig = val; > > + > > + /* TODO - implement FIFOs to support slave mode */ > > + val &= 0xffffffff; > > + trace_usb_dwc2_hreg2_write(addr, addr >> 12, orig, 0, val); > > +} > > + > [...] > + > > +static const MemoryRegionOps dwc2_mmio_hreg2_ops = { > > + .read = dwc2_hreg2_read, > > + .write = dwc2_hreg2_write, > > + .valid.min_access_size = 4, > > + .valid.max_access_size = 4, > > + .endianness = DEVICE_LITTLE_ENDIAN, > > +}; > [...] > > +static void dwc2_init(DWC2State *s, DeviceState *dev) > > +{ > > + s->usb_frame_time = NANOSECONDS_PER_SECOND / 1000; /* > 1000000 */ > > + if (NANOSECONDS_PER_SECOND >= USB_HZ_FS) { > > + s->usb_bit_time = NANOSECONDS_PER_SECOND / USB_HZ_FS; /* 83.3 > */ > > + } else { > > + s->usb_bit_time = 1; > > + } > > + > > + s->fi = 11999; > > + > > + memory_region_init(&s->mem, OBJECT(dev), "dwc2", DWC2_MMIO_SIZE); > > + memory_region_init_io(&s->mem_glbreg, OBJECT(dev), > &dwc2_mmio_glbreg_ops, s, > > + "global", 0x70); > > + memory_region_init_io(&s->mem_fszreg, OBJECT(dev), > &dwc2_mmio_fszreg_ops, s, > > + "hptxfsiz", 0x4); > > + memory_region_init_io(&s->mem_hreg0, OBJECT(dev), > &dwc2_mmio_hreg0_ops, s, > > + "host", 0x44); > > + memory_region_init_io(&s->mem_hreg1, OBJECT(dev), > &dwc2_mmio_hreg1_ops, s, > > + "host channels", 0x20 * NB_CHAN); > > + memory_region_init_io(&s->mem_pcgreg, OBJECT(dev), > &dwc2_mmio_pcgreg_ops, s, > > + "power/clock", 0x8); > > + memory_region_init_io(&s->mem_hreg2, OBJECT(dev), > &dwc2_mmio_hreg2_ops, s, > > + "host fifos", NB_CHAN * 0x1000); > [...] > What is this region used for? 64KB of packet buffer sram? I'm wondering > if this shouldn't be created with a memory_region_init_ram() call actually. > >
