This is the first part of v4 patchset. The changelog of v4 is only coverd
the part1.
Features:
* support specification riscv-v-spec-0.7.1.
* support basic vector extension.
* support Zvlsseg.
* support Zvamo.
* not support Zvediv as it is changing.
* fixed SLEN 128bit.
* element width support 8bit, 16bit, 32bit, 64bit.
Changelog:
v4
* adjust max vlen to 512 bits.
* check maximum on elen(64bits).
* check minimum on vlen(128bits).
* check if rs1 is x0 in vsetvl/vsetvli.
* use gen_goto_tb in vsetvli instead of exit_tb.
* fixup fetch vlmax from rs2, not env->vext.type.
v3
* support VLEN configure from qemu command line.
* support ELEN configure from qemu command line.
* support vector specification version configure from qemu command line.
* only default on for "any" cpu, others turn on from command line.
* use a continous memory block for vector register description.
V2
* use float16_compare{_quiet}
* only use GETPC() in outer most helper
* add ctx.ext_v Property
LIU Zhiwei (4):
target/riscv: add vector extension field in CPURISCVState
target/riscv: configure and turn on vector extension from command line
target/riscv: support vector extension csr
target/riscv: add vector configure instruction
MAINTAINERS | 1 +
target/riscv/Makefile.objs | 2 +-
target/riscv/cpu.c | 48 ++++++++++++++-
target/riscv/cpu.h | 82 ++++++++++++++++++++++---
target/riscv/cpu_bits.h | 15 +++++
target/riscv/csr.c | 72 +++++++++++++++++++++-
target/riscv/helper.h | 2 +
target/riscv/insn32.decode | 5 ++
target/riscv/insn_trans/trans_rvv.inc.c | 69 +++++++++++++++++++++
target/riscv/translate.c | 17 ++++-
target/riscv/vector_helper.c | 49 +++++++++++++++
11 files changed, 346 insertions(+), 16 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c
create mode 100644 target/riscv/vector_helper.c
--
2.23.0
