On Wed, Nov 20, 2019 at 08:13:50AM +0100, Cédric Le Goater wrote:
> On 19/11/2019 18:50, Balamuruhan S wrote:
> > Homer size is 4MB and OCC common area size is 8MB, but currently
> > it is assigned with bar mask value. Also pass on the occ sram
> > size 3 bits right shifted to initialize the size appropriately.
> >
> > Signed-off-by: Cédric Le Goater <c...@kaod.org>
> > Signed-off-by: Balamuruhan S <bal...@linux.ibm.com>
> > ---
> > hw/ppc/pnv_occ.c | 2 +-
> > include/hw/ppc/pnv.h | 8 ++++----
> > 2 files changed, 5 insertions(+), 5 deletions(-)
> >
> > diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c
> > index 785653bb67..05c51c9de0 100644
> > --- a/hw/ppc/pnv_occ.c
> > +++ b/hw/ppc/pnv_occ.c
> > @@ -276,7 +276,7 @@ static void pnv_occ_realize(DeviceState *dev, Error
> > **errp)
> >
> > /* XScom region for OCC SRAM registers */
> > pnv_xscom_region_init(&occ->sram_regs, OBJECT(dev), poc->sram_ops,
> > - occ, "occ-common-area", poc->sram_size);
> > + occ, "occ-common-area", poc->sram_size >> 3);
>
> the OCC common area seems to be accessed through MMIO also. Not only XSCOM.
>
> In skiboot :
>
> bool occ_sensors_init(void)
> {
> ...
> occ_sensor_base = chip->occ_common_base + OCC_SENSOR_DATA_BLOCK_OFFSET;
> ...
> }
>
> OCC would need two regions. One for the XSCOM access and one for the MMIO.
>
> > }
Okay, I will follow it.
> >
> > static void pnv_occ_class_init(ObjectClass *klass, void *data)
> > diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
> > index 0b4c722e6b..e9ed8b928a 100644
> > --- a/include/hw/ppc/pnv.h
> > +++ b/include/hw/ppc/pnv.h
> > @@ -203,12 +203,12 @@ void pnv_bmc_powerdown(IPMIBmc *bmc);
> > #define PNV_XSCOM_BASE(chip) \
> > (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE)
> >
> > -#define PNV_OCC_COMMON_AREA_SIZE 0x0000000000700000ull
> > +#define PNV_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
>
> ok. These are the BAR sizes. Can we deduce the barmask from the size ?
Correct! we can do that, will make the respective change.
>
>
> > #define PNV_OCC_COMMON_AREA(chip) \
> > (0x7fff800000ull + ((uint64_t)PNV_CHIP_INDEX(chip) * \
> > PNV_OCC_COMMON_AREA_SIZE))
> >
> > -#define PNV_HOMER_SIZE 0x0000000000300000ull
> > +#define PNV_HOMER_SIZE 0x0000000000400000ull
> > #define PNV_HOMER_BASE(chip) \
> > (0x7ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV_HOMER_SIZE)
> >
> > @@ -271,12 +271,12 @@ void pnv_bmc_powerdown(IPMIBmc *bmc);
> > #define PNV9_XSCOM_SIZE 0x0000000400000000ull
> > #define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip,
> > 0x00603fc00000000ull)
> >
> > -#define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000700000ull
> > +#define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
> > #define PNV9_OCC_COMMON_AREA(chip) \
> > (0x203fff800000ull + ((uint64_t)PNV_CHIP_INDEX(chip) * \
> > PNV9_OCC_COMMON_AREA_SIZE))
> >
> > -#define PNV9_HOMER_SIZE 0x0000000000300000ull
> > +#define PNV9_HOMER_SIZE 0x0000000000400000ull
> > #define PNV9_HOMER_BASE(chip) \
> > (0x203ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) *
> > PNV9_HOMER_SIZE)
> > #endif /* PPC_PNV_H */
> >
>
