On 19/11/2019 18:50, Balamuruhan S wrote:
> occ common area should be mapped once
It's the same address on each chip.
the question is how the HW knows from which chip the OCC access is
being done ? How does it target the correct OCC if the address is
the same ?
> and disable it for every other chip.
On P8 OpenPOWER systems, the PBA3 registers are still set, not on
tuletas though (different hostboot I suppose). On OpenPOWER systems,
they are still set also.
> Signed-off-by: Cédric Le Goater <c...@kaod.org>
nah. I didn't write any of this :)
> Signed-off-by: Balamuruhan S <bal...@linux.ibm.com>
> ---
> hw/ppc/pnv_xscom.c | 15 ++++++++++++---
> 1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c
> index cb6d6bbcfc..f797a5ec7d 100644
> --- a/hw/ppc/pnv_xscom.c
> +++ b/hw/ppc/pnv_xscom.c
> @@ -98,13 +98,22 @@ static uint64_t xscom_read_default(PnvChip *chip,
> uint32_t pcba)
> return HOMER_SIZE_MASK;
>
> case P9_PBA_BAR2: /* P9 occ common area */
> - return PNV9_OCC_COMMON_AREA(chip);
> + if (!PNV_CHIP_INDEX(chip)) {
Yes that it is the idea. XIVE uses directly 'chip->chip_id'.
> + return PNV9_OCC_COMMON_AREA(chip);
> + }
> + return 0;
> case P8_PBA_BAR3: /* P8 occ common area */
> - return PNV_OCC_COMMON_AREA(chip);
> + if (!PNV_CHIP_INDEX(chip)) {
> + return PNV_OCC_COMMON_AREA(chip);
> + }
> + return 0;
>
> case P9_PBA_BARMASK2: /* P9 occ common area size */
> case P8_PBA_BARMASK3: /* P8 occ common area size */
> - return OCC_SIZE_MASK;
> + if (!PNV_CHIP_INDEX(chip)) {
> + return OCC_SIZE_MASK;
> + }
> + return 0;
>
> case 0x1010c00: /* PIBAM FIR */
> case 0x1010c03: /* PIBAM FIR MASK */
>
