On 05/19/2011 05:04 PM, Anthony Liguori wrote:
Right, the chipset register is mainly used to program the contents of
SMM.
There is a single access pin that has effectively the same semantics
as setting the chipset register.
It's not a per-CPU setting--that's the point. You can't have one CPU
reading SMM memory at the exactly same time as accessing VGA.
But I guess you can never have two simultaneous accesses anyway so
perhaps it's splitting hairs :-)
Exactly - it just works.
btw, a way to implement it would be to have two memory maps, one for SMM
and one for non-SMM, and select between them based on the CPU mode.
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