On Thu, May 19, 2011 at 11:30 AM, Jan Kiszka <jan.kis...@web.de> wrote: > On 2011-05-19 10:26, Gleb Natapov wrote: >> On Wed, May 18, 2011 at 09:27:55PM +0200, Jan Kiszka wrote: >>>> if an I/O is to the APIC page, >>>> it's handled by the APIC >>> >>> That's not that simple. We need to tell apart: >>> - if a cpu issued the request, and which one => forward to APIC >> And cpu mode may affect where access is forwarded to. If cpu is in SMM >> mode access to frame buffer may be forwarded to a memory (depends on >> chipset configuration). > > So we have a second use case for CPU-local I/O regions?
SuperSparc MXCC (memory cache controller) should be CPU specific. Currently we handle this for accesses via ASI, but the registers could be mapped with MMU and then the ASI-less access would not be handled. Another case would be the cache-as-ram mode for some x86 CPUs, which Coreboot people would like to see IIRC.
