Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org>
---
target/mips/insns.decode | 12 ++++++++++++
target/mips/translate.inc.c | 12 ++++++++++++
2 files changed, 24 insertions(+)
diff --git a/target/mips/insns.decode b/target/mips/insns.decode
index 8a1a7acf3a..e256220211 100644
--- a/target/mips/insns.decode
+++ b/target/mips/insns.decode
@@ -2,9 +2,21 @@
#
# From:
# - MIPS32 Architecture For Programmers Volume II-A (Document Number: MD00086)
+# - MIPS64 Architecture For Programmers Volume II-A (Document Number: MD00087)
+
+&rs_rt_rd rs rt rd
+
+@rs_rt_rd ...... rs:5 rt:5 rd:5 00000 ...... &rs_rt_rd
####
# System Instructions
####
synci 000001 ----- 11111 ---------------- >insn=ISA_MIPS32R2
+
+####
+# Special2 Instructions
+####
+
+dclz 011100 ..... ..... ..... ..... 100100 @rs_rt_rd
?ctx->insn_flags&ISA_MIPS64
+dclo 011100 ..... ..... ..... ..... 100101 @rs_rt_rd
?ctx->insn_flags&ISA_MIPS64
diff --git a/target/mips/translate.inc.c b/target/mips/translate.inc.c
index f3dcd32f98..90fe868605 100644
--- a/target/mips/translate.inc.c
+++ b/target/mips/translate.inc.c
@@ -18,3 +18,15 @@ static bool trans_synci(DisasContext *dc, arg_synci *a)
dc->base.is_jmp = DISAS_STOP;
return true;
}
+
+static bool trans_dclz(DisasContext *ctx, arg_rs_rt_rd *a)
+{
+ gen_cl(ctx, OPC_DCLZ, a->rd, a->rs);
+ return true;
+}
+
+static bool trans_dclo(DisasContext *ctx, arg_rs_rt_rd *a)
+{
+ gen_cl(ctx, OPC_DCLO, a->rd, a->rs);
+ return true;
+}
--
2.17.2
