On Tue, Jan 18, 2011 at 12:29:42AM +0100, edgar.igles...@gmail.com wrote: > From: Edgar E. Iglesias <edgar.igles...@gmail.com> > > When reading cp0_count from a timer with a late trigger that should > already have expired, expire it and raise the timer irq. > > This makes it possible for guest code (e.g, Linux) that first read > cp0_count, then compare it with cp0_compare and check for raised > timer interrupt lines to run reliably. > > Signed-off-by: Edgar E. Iglesias <edgar.igles...@gmail.com>
Sorry sent the wrong version of this one. It's supposed to be the following: commit 139330de404209528712fd703952c0b5ad4459a1 Author: Edgar E. Iglesias <edgar.igles...@gmail.com> Date: Tue Jan 18 00:12:22 2011 +0100 mips: Expire late timers when reading cp0_count When reading cp0_count from a timer with a late trigger that should already have expired, expire it and raise the timer irq. This makes it possible for guest code (e.g, Linux) that first read cp0_count, then compare it with cp0_compare and check for raised timer interrupt lines to run reliably. Signed-off-by: Edgar E. Iglesias <edgar.igles...@gmail.com> diff --git a/hw/mips_timer.c b/hw/mips_timer.c index 8c32087..9c95f28 100644 --- a/hw/mips_timer.c +++ b/hw/mips_timer.c @@ -69,9 +69,17 @@ uint32_t cpu_mips_get_count (CPUState *env) if (env->CP0_Cause & (1 << CP0Ca_DC)) { return env->CP0_Count; } else { + uint64_t now; + + now = qemu_get_clock(vm_clock); + if (qemu_timer_pending(env->timer) + && qemu_timer_expired(env->timer, now)) { + /* The timer has already expired. */ + cpu_mips_timer_expire(env); + } + return env->CP0_Count + - (uint32_t)muldiv64(qemu_get_clock(vm_clock), - TIMER_FREQ, get_ticks_per_sec()); + (uint32_t)muldiv64(now, TIMER_FREQ, get_ticks_per_sec()); } }