On Thu, Nov 30, 2017 at 01:44:51PM +0000, Cédric Le Goater wrote:
> On 11/30/2017 04:06 AM, David Gibson wrote:
> > On Wed, Nov 29, 2017 at 10:55:34AM +0100, Cédric Le Goater wrote:
> >> On 11/29/2017 06:11 AM, David Gibson wrote:
> >>> On Thu, Nov 23, 2017 at 02:29:42PM +0100, Cédric Le Goater wrote:
> >>>> The XIVE interrupt presenter exposes a set of rings, also called
> >>>> Thread Interrupt Management Areas (TIMA), to handle priority
> >>>> management and interrupt acknowledgment among other things. There is
> >>>> one ring per level of privilege, four in all. The one we are
> >>>> interested in for the sPAPR machine is the OS ring.
> >>>>
> >>>> The TIMA is mapped at the same address for each CPU. 'current_cpu' is
> >>>> used to retrieve the targeted interrupt presenter object holding the
> >>>> cache data of the registers the model use.
> >>>>
> >>>> Signed-off-by: Cédric Le Goater <c...@kaod.org>
> >>>> ---
> >>>> hw/intc/spapr_xive.c | 271
> >>>> ++++++++++++++++++++++++++++++++++++++++++++
> >>>> hw/intc/xive-internal.h | 89 +++++++++++++++
> >>>> include/hw/ppc/spapr_xive.h | 11 ++
> >>>> 3 files changed, 371 insertions(+)
> >>>>
> >>>> diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
> >>>> index b1e3f8710cff..554b25e0884c 100644
> >>>> --- a/hw/intc/spapr_xive.c
> >>>> +++ b/hw/intc/spapr_xive.c
> >>>> @@ -23,9 +23,166 @@
> >>>> #include "sysemu/dma.h"
> >>>> #include "monitor/monitor.h"
> >>>> #include "hw/ppc/spapr_xive.h"
> >>>> +#include "hw/ppc/xics.h"
> >>>>
> >>>> #include "xive-internal.h"
> >>>>
> >>>> +struct sPAPRXiveICP {
> >>>
> >>> I'd really prefer to avoid calling anything in xive "icp" to avoid
> >>> confusion with xics.
> >>
> >> OK.
> >>
> >> The specs refers to the whole as an IVPE : Interrupt Virtualization
> >> Presentation Engine. In our model, we use the TIMA cached values of
> >> the OS ring and the qemu_irq for the CPU line.
> >>
> >> Would 'sPAPRXivePresenter' be fine ?
> >
> > That'd be ok. Or call if sPAPRIVPE. Or even call it TIMA. I'd be
> > fine with any of those.
>
> In this model, I am making a lot of shortcuts in the XIVE concepts
> (which I don't master completely yet ...)
>
> The IVPE is the part of the overall controller doing the interrupt
> presentation.
>
> The TIMA refers to the MMIO region in which the thread interrupt
> management is done.
>
> The XIVE structure that contains the 'virtual processor' interrupt
> state is the NVT: Notification Virtual Target. An index to an NVT
> is stored in the EQs to do the routing. I did not introduce the NVT
> in sPAPRXive because it's rather big, 128 bytes, and we don't need
> much of it (NSR, CPPR, PIPR, IPB) but we could use a shorten one.
>
> So I think sPAPRXiveNVT, or sPAPRXiveVP (VP for virtual processor)
> would be better names.
Ok. I prefer sPAPRXiveNVT of these two.
>
> We will need more of the NVT structure to support the hcalls
> doing the set and the get of the address of the Reporting Cache
> line (H_INT_{S,G}ET_OS_REPORTING_LINE). We can extend it when
> time comes.
>
> C.
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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