Patches:
01-06 Cleans up the XER split out variables and now the
flag bits are stored in XER at their respective places
07-14 Contains implentation of CA32 and OV32 bits added to the
ISA 3.0. Various fixed-point arithmetic instructions are
updated to take care of the newer flags.
15 Finally the last patch adds new instruction mcrxrx, that helps
reading the carry (CA and CA32) and the overflow (OV and OV32) flags
Booted the POWER8 guest fine, needs more testing as changes are
intrusive in nature.
Changelog:
v3:
* Get rid of cpu_ca, cpu_ov, cpu_so split out variables
* As most of the patches under went changes, dropped the
reviewed-bys(except neg[.] patch)
v2:
* Add missing condition in narrow mode(add/subf), multiply and divide
* Drop nego patch, subf implementation is sufficient for setting OV and OV32
* Retaining neg[.], as the code is simplified.
* Fix OV resetting in compute_ov()
v1:
* Use these ISA 3.0 flag to enable CA32 and OV32
* Re-write ca32 compute routine
* Add setting of flags for "neg." and "nego."
Nikunj A Dadhania (15):
target/ppc: introduce helper_update_ov_legacy
target/ppc: update ov flag from remaining paths
target/ppc: introduce helper_update_ca_legacy
target/ppc: add gen_op_update_ca_legacy() helper
target/ppc: add gen_op_update_ov_legacy() helper
target/ppc: remove xer split-out flags(so, ov, ca)
target/ppc: support for 32-bit carry and overflow
target/ppc: update ca32 in arithmetic add
target/ppc: update ca32 in arithmetic substract
target/ppc: add gen_op_update_ov_isa300()
target/ppc: update OV/OV32 for mull[d,w] insns
target/ppc: update OV/OV32 for divide operations
target/ppc: update OV/OV32 flags for add/sub
target/ppc: use tcg ops for neg instruction
target/ppc: add mcrxrx instruction
target/ppc/cpu.c | 8 +-
target/ppc/cpu.h | 33 ++--
target/ppc/int_helper.c | 90 ++++++-----
target/ppc/translate.c | 396 +++++++++++++++++++++++++++++++++++-------------
4 files changed, 371 insertions(+), 156 deletions(-)
--
2.7.4
