[Qemu-devel] [PATCH v4 7/9] target-mips: Add abs2008 flavor of .

[Aleksandar Markovic]

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com>

Updated handling of instuctions <ABS|NEG>.<S|D>. Note that legacy
(pre-abs2008) ABS and NEG instructions are arithmetic (any NaN operand
signals invalid operation), while abs2008 ones are non-arithmetic, always
changing the sign bit, even for NaN-like operands. Details on these
instructions are documented in [1] p. 35 and 359.

[1] "MIPS® Architecture For Programmers Volume II-A:
    The MIPS64® Instruction Set Reference Manual",
    Imagination Technologies LTD, Revision 6.04, November 13, 2015

Signed-off-by: Thomas Schwinge <tho...@codesourcery.com>
Signed-off-by: Maciej W. Rozycki <ma...@codesourcery.com>
Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com>
---
 target-mips/translate.c |   27 +++++++++++++++++++++++----
 1 file changed, 23 insertions(+), 4 deletions(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index de0b224..1d376fc 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1434,6 +1434,8 @@ typedef struct DisasContext {
     bool vp;
     bool cmgcr;
     bool mrp;
+    bool abs2008;
+
 } DisasContext;
 
 enum {
@@ -8879,7 +8881,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
             TCGv_i32 fp0 = tcg_temp_new_i32();
 
             gen_load_fpr32(ctx, fp0, fs);
-            gen_helper_float_abs_s(fp0, fp0);
+            if (ctx->abs2008) {
+                tcg_gen_andi_i32(fp0, fp0, 0x7fffffffUL);
+            } else {
+                gen_helper_float_abs_s(fp0, fp0);
+            }
             gen_store_fpr32(ctx, fp0, fd);
             tcg_temp_free_i32(fp0);
         }
@@ -8898,7 +8904,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
             TCGv_i32 fp0 = tcg_temp_new_i32();
 
             gen_load_fpr32(ctx, fp0, fs);
-            gen_helper_float_chs_s(fp0, fp0);
+            if (ctx->abs2008) {
+                tcg_gen_xori_i32(fp0, fp0, 1UL << 31);
+            } else {
+                gen_helper_float_chs_s(fp0, fp0);
+            }
             gen_store_fpr32(ctx, fp0, fd);
             tcg_temp_free_i32(fp0);
         }
@@ -9369,7 +9379,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
             TCGv_i64 fp0 = tcg_temp_new_i64();
 
             gen_load_fpr64(ctx, fp0, fs);
-            gen_helper_float_abs_d(fp0, fp0);
+            if (ctx->abs2008) {
+                tcg_gen_andi_i64(fp0, fp0, 0x7fffffffffffffffULL);
+            } else {
+                gen_helper_float_abs_d(fp0, fp0);
+            }
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
@@ -9390,7 +9404,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode 
op1,
             TCGv_i64 fp0 = tcg_temp_new_i64();
 
             gen_load_fpr64(ctx, fp0, fs);
-            gen_helper_float_chs_d(fp0, fp0);
+            if (ctx->abs2008) {
+                tcg_gen_xori_i64(fp0, fp0, 1ULL << 63);
+            } else {
+                gen_helper_float_chs_d(fp0, fp0);
+            }
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
@@ -19775,6 +19793,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct 
TranslationBlock *tb)
              (env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F));
     ctx.vp = (env->CP0_Config5 >> CP0C5_VP) & 1;
     ctx.mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
+    ctx.abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
     restore_cpu_state(env, &ctx);
 #ifdef CONFIG_USER_ONLY
         ctx.mem_idx = MIPS_HFLAG_UM;
-- 
1.7.9.5