On Mon, Oct 26, 2015 at 09:52:12AM +0000, Peter Maydell wrote:
> On 26 October 2015 at 09:20, Edgar E. Iglesias
> <edgar.igles...@xilinx.com> wrote:
> > Yes, sounds good. I've changed the patch to the following:
> >
> > @@ -6521,8 +6521,24 @@ static bool get_phys_addr_lpae(CPUARMState *env,
> > target_ulong address,
> > */
> > int32_t t0sz = extract32(tcr->raw_tcr, 0, 6);
> > if (va_size == 64) {
> > + /* AArch64 translation. */
> > t0sz = MIN(t0sz, 39);
> > t0sz = MAX(t0sz, 16);
> > + } else if (mmu_idx != ARMMMUIdx_S2NS) {
> > + /* AArch32 stage 1 translation. */
> > + t0sz = extract32(t0sz, 0, 3);
> > + } else {
> > + /* AArch32 stage 2 translation. */
> > + bool sext = extract32(t0sz, 4, 1);
> > + bool sign = extract32(t0sz, 3, 1);
> > + t0sz = sextract32(t0sz, 0, 4);
> > +
> > + /* If the sign-extend bit is not the same as t0sz[3], the result
> > + * is unpredictable. Flag this as a guest error. */
> > + if (sign != sext) {
> > + qemu_log_mask(LOG_GUEST_ERROR,
> > + "AArch32: VTCR.S / VTCR.T0SZ[3] missmatch\n");
> > + }
> > }
> >
>
> Looks good, but maybe we should just do all the extracts
> on tcr->raw_tcr, rather than extracting 6 bits of it and
> then re-extracting some subset of bits from that extract
> (for the 32-bit stage 1 case in particular it would be
> simpler).
OK, I've rearranged the code a bit to use raw_tcr.
Thanks,
Edgar
