From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com>
Add support for AArch32 S2 negative t0sz. In preparation for
using 40bit IPAs on AArch32.
Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
---
target-arm/helper.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 4e19838..a8a46db 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -6475,6 +6475,17 @@ static bool get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
if (va_size == 64) {
t0sz = MIN(t0sz, 39);
t0sz = MAX(t0sz, 16);
+ } else {
+ bool sext = extract32(t0sz, 4, 1);
+ bool sign = extract32(t0sz, 3, 1);
+ t0sz = sextract32(t0sz, 0, 4);
+
+ /* If the sign-extend bit is not the same as t0sz[3], the result
+ * is unpredictable. Flag this as a guest error. */
+ if (sign != sext) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "AArch32: VTCR.S / VTCR.T0SZ[3] missmatch\n");
+ }
}
int32_t t1sz = extract32(tcr->raw_tcr, 16, 6);
if (va_size == 64) {
--
1.9.1
