From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> Hi,
Another round of patches towards EL2 support. This one adds partial support for 2-stage MMU. The AArch32/ARMv7 support is untested. Some of the details of error reporting are intentionally missing, I was thinking to add those incrementally as they get quite involved (e.g the register target and memory access size). Comments welcome! Best regards, Edgar v3 -> v4: * Introduce inputsize to simplify and better match ref manuals * Rename granule_sz to stride to better match ref manuals * Add support for AArch32 negative S2 t0sz * Add support for computing the AArch32 S2 PTW starting level. * Add support for trapping on bad S2 starting levels v2 -> v3: * Prettify comments for ARMMMUFaultInfo * Add S2 translation for 32bit S1 PTWs * Add more comments to S2 PTW starting level computation. v1 -> v2: * Fix HPFAR_EL2 access checks * Prettify computation of starting level for S2 PTW * Improve description of ap argument to get_S2prot * Fix EXEC protection in get_S2prot * Improve comments on S2 PTW attribute extraction * Add comment describing ARMMMUFaultInfo Edgar E. Iglesias (13): target-arm: Add HPFAR_EL2 target-arm: lpae: Make t0sz and t1sz signed integers target-arm: Add support for AArch32 S2 negative t0sz target-arm: lpae: Replace tsz with computed inputsize target-arm: lpae: Rename granule_sz to stride target-arm: Add computation of starting level for S2 PTW target-arm: Add support for S2 page-table protection bits target-arm: Avoid inline for get_phys_addr target-arm: Add ARMMMUFaultInfo target-arm: Add S2 translation to 64bit S1 PTWs target-arm: Add S2 translation to 32bit S1 PTWs target-arm: Route S2 MMU faults to EL2 target-arm: Add support for S1 + S2 MMU translations target-arm/cpu.h | 1 + target-arm/helper.c | 375 ++++++++++++++++++++++++++++++++++++++++--------- target-arm/internals.h | 40 +++++- target-arm/op_helper.c | 17 ++- 4 files changed, 361 insertions(+), 72 deletions(-) -- 1.9.1
