On 4 September 2015 at 15:47, Pavel Fedin <p.fe...@samsung.com> wrote: > Hello! > >> It's not clear to me that the TCG version of GICv3 >> emulation should need to have such a link. > > How can it be done otherwise? Should GIC code somehow register > own system register handlers instead?
Well, this comes down to how we want to design the part of the GICv3 that deals with the CPU interface. In hardware this is a clearly separated boundary with a defined protocol between the "GIC proper" and the "CPU interface", which might well be implementations from different companies. We could implement it like that; or we could decide to merge the two into what we call a single GIC device, where that GIC device registers a set of system registers in each CPU. I'm not sure what the right answer is; it depends a bit on how the kernel ends up deciding to export the GIC state which is in the CPU interface. Having a fused single GIC device makes it easier to slot in gicv2 vs gicv3 in our board models, though modelling it like hardware would be cleaner in some ways. >> The original >> emulation patchset was definitely not handling the >> GIC-to-CPU connection in the right way > > But it seems to be very convenient to reuse what already exists, > isn't it? What already exists in QEMU is often legacy and not necessarily a very good model for anything. > Well, if you just don't want, then you don't want, i'm fine with > this. This series might be the right approach (I think if we do want a property the CPU owns which points at the interrupt controller it's good code to do that). But it needs to be part of the patchset which adds the GICv3 emulation support that requires it, so that we can review the whole design and see if it makes sense as a whole. thanks -- PMM
