Hi! This message is mainly for Peter. I say you reviewed my major sets, but looks like missed this one. If it is OK, we could apply it, and i could successfully bring back the missing part in vGICv3-enabled hw/arm/virt.c which attaches irqchip to CPUs. This would make us more ready for TCG version of GICv3.
Kind regards, Pavel Fedin Expert Engineer Samsung Electronics Research center Russia > -----Original Message----- > From: qemu-devel-bounces+p.fedin=samsung....@nongnu.org [mailto:qemu-devel- > bounces+p.fedin=samsung....@nongnu.org] On Behalf Of Pavel Fedin > Sent: Tuesday, August 25, 2015 3:18 PM > To: qemu-devel@nongnu.org > Cc: Peter Maydell; Shlomo Pongratz; Shlomo Pongratz > Subject: [Qemu-devel] [PATCH v2 0/2] cpu_arm: Implement irqchip property for > ARM CPU > > ARMv7m CPU needs a link to NVIC instance for processing interrupts. > Similarly ARMv8 needs a link to GICv3 for its CPU interface. > > This series builds upon existing mechanism for linking irqchip and > CPU, bringing the code up to date and making it reusable. Another small > step towards complete GICv3 implementation. > > v1 => v2: > - Set link to nvic after it has been initialized > - Changed object type to "sys-bus-device" because GICv2 and GICv3 do not > share common ancestors above that. > > Pavel Fedin (2): > cpu_arm: Rename 'nvic' to 'irqchip' > armv7m: Use irqchip property instead of direct assignment > > hw/arm/armv7m.c | 5 ++--- > target-arm/cpu.c | 6 ++++++ > target-arm/cpu.h | 5 ++++- > target-arm/helper.c | 12 ++++++------ > 4 files changed, 18 insertions(+), 10 deletions(-) > > -- > 1.9.5.msysgit.0
