On 15 September 2014 09:02, Martin Galvan <martin.gal...@tallertechnologies.com> wrote: > I did a bit more research on how Cortex-M handles nested interrupts. > In particular, I noticed if we were to have an invalid instruction > inside the exception handler itself, trying to single-step it would > again cause Qemu not to return control back to gdb. Reading up a bit I > found out that when the CPU is handling an exception, all other > exceptions with the same or lower priority will be blocked. > > Qemu seems to implement this by setting the exception as pending, yet > not changing cpu->interrupt_request so that we modify the PC in the > second call to do_interrupt. That seems fine to me, but since the > translation block is the same as before (and if that one contained an > exception_with_syndrome ending in a call to cpu_loop_exit) we'll be > stuck in the loop and we'll never return control to Gdb. > > Therefore I have two questions: > 1) Is this a bug? > 2) If it is, what should the behaviour be? I think we should return > control back to gdb, but we shouldn't try to translate that > instruction again. How could we handle this in a clean way?
Our handling of exceptions and exception priorities for Cortex-M CPUs is totally wrong. We attempt to reuse the GIC priority handling code for interrupts, which then leaves the exceptions without the correct priority handling. Ideally we should rewrite this completely to give the M profile cores the architecturally mandated exception priority handling and masking, and stop trying to reuse the A/R profile core code at all. The two profiles are just too different for that to make sense. Any bugs or weirdness in the current code are likely symptoms of attempting to shoehorn M profile into the A/R profile handling. -- PMM
